diff --git a/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk/p10bmc/ips.json b/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk/p10bmc/ips.json
new file mode 100644
index 0000000..6c7a258
--- /dev/null
+++ b/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk/p10bmc/ips.json
@@ -0,0 +1,126 @@
+{
+    "name": "p10bmc",
+    "version": "A3",
+    "data_region": {
+        "ecc_region": true,
+        "key": [
+            {
+                "types": "rsa_pub_oem",
+                "key_pem": "rsa_pub_oem_dss_key.pem",
+                "offset": "0x40",
+                "number_id": 0,
+                "sha_mode": "SHA512"
+            },
+            {
+                "types": "rsa_pub_oem",
+                "key_pem": "IPS_P10BMCAspeedSBPubKey_1.pem",
+                "offset": "0x240",
+                "number_id": 1,
+                "sha_mode": "SHA512"
+            },
+            {
+                "types": "rsa_pub_oem",
+                "key_pem": "IPS_P10BMCAspeedSBPubKey_2.pem",
+                "offset": "0x440",
+                "number_id": 2,
+                "sha_mode": "SHA512"
+            },
+            {
+                "types": "rsa_pub_oem",
+                "key_pem": "IPS_P10BMCAspeedSBPubKey_3.pem",
+                "offset": "0x640",
+                "number_id": 2,
+                "sha_mode": "SHA512"
+            }
+        ]
+    },
+    "config_region": {
+        "Disable OTP Memory BIST Mode":                 true,
+        "Enable Secure Boot":                           false,
+        "User region ECC enable":                       true,
+        "Secure Region ECC enable":                     false,
+        "Disable low security key":                     false,
+        "Ignore Secure Boot hardware strap":            false,
+        "Secure Boot Mode":                             "Mode_2",
+        "Disable Uart Message of ROM code":             false,
+        "Secure crypto RSA length":                     "RSA4096",
+        "Hash mode":                                    "SHA512",
+        "Disable patch code":                           true,
+        "Disable Boot from Uart":                       false,
+        "Secure Region size":                           "0x0",
+        "Write Protect: Secure Region":                 true,
+        "Write Protect: User region":                   true,
+        "Write Protect: Configure region":              true,
+        "Write Protect: OTP strap region":              true,
+        "Copy Boot Image to Internal SRAM":             true,
+        "Enable image encryption":                      false,
+        "Enable write Protect of OTP key retire bits":  false,
+        "Disable Auto Boot from UART or VUART":         false,
+        "OTP memory lock enable":                       false,
+        "Key Revision":                                 "0x0",
+        "Secure boot header offset":                    "0x0",
+        "Boot From UART Port Selection":                "UART5",
+        "Disable Auto Boot from UART":                  false,
+        "Disable Auto Boot from VUART2 over PCIE":      true,
+        "Disable Auto Boot from VUART2 over LPC":       true,
+        "Disable ROM code based programming control":   true,
+        "Rollback prevention shift bit number":         "0x0",
+        "Extra Data Write Protection Region Size":      "0x0",
+        "Erase signature data after secure boot check": false,
+        "Erase RSA public key after secure boot check": false,
+        "Keys Retire ID":                               0,
+        "User define data: random number low":          "0x0",
+        "User define data: random number high":         "0x0",
+        "Manifest ID":                                  "0x0",
+        "Patch code location":                          "0x0",
+        "Patch code size":                              "0x0"
+    },
+    "otp_strap": {
+        "Enable secure boot":                           { "value": false },
+        "Enable boot from eMMC":                        { "value": true },
+        "Boot from debug SPI":                          { "value": false },
+        "Disable ARM CM3":                              { "value": true },
+        "Enable dedicated VGA BIOS ROM":                { "value": false },
+        "MAC 1 RMII mode":                              { "value": "RMII/NCSI" },
+        "MAC 2 RMII mode":                              { "value": "RMII/NCSI" },
+        "CPU frequency":                                { "value": "1.2GHz" },
+        "HCLK ratio":                                   { "value": "default" },
+        "VGA memory size":                              { "value": "16MB" },
+        "CPU/AXI clock ratio":                          { "value": "2:1" },
+        "Disable ARM JTAG debug":                       { "value": true },
+        "VGA class code":                               { "value": "vga_device" },
+        "Disable debug 0":                              { "value": false },
+        "Boot from eMMC speed mode":                    { "value": "normal" },
+        "Enable PCIe EHCI":                             { "value": false },
+        "Disable ARM JTAG trust world debug":           { "value": true },
+        "Disable dedicated BMC function":               { "value": false },
+        "Enable dedicate PCIe RC reset":                { "value": false },
+        "Disable watchdog to reset full chip":          { "value": false },
+        "Internal bridge speed selection":              { "value": "1x" },
+        "Disable RVAS function":                        { "value": false },
+        "MAC 3 RMII mode":                              { "value": "RMII/NCSI" },
+        "MAC 4 RMII mode":                              { "value": "RMII/NCSI" },
+        "SuperIO configuration address selection":      { "value": "0x2e" },
+        "Disable LPC to decode SuperIO":                { "value": true },
+        "Disable debug 1":                              { "value": false },
+        "Enable ACPI":                                  { "value": false },
+        "Select LPC/eSPI":                              { "value": "LPC" },
+        "Enable SAFS":                                  { "value": false },
+        "Enable boot from uart5":                       { "value": false },
+        "Enable boot SPI 3B address mode auto-clear":   { "value": false },
+        "Enable SPI 3B/4B address mode auto detection": { "value": false },
+        "Enable boot SPI or eMMC ABR":                  { "value": true },
+        "Boot SPI ABR Mode":                            { "value": "dual" },
+        "Boot SPI flash size":                          { "value": "0" },
+        "Enable host SPI ABR":                          { "value": false },
+        "Enable host SPI ABR mode select pin":          { "value": false },
+        "Host SPI ABR Mode":                            { "value": "dual" },
+        "Host SPI flash size":                          { "value": "0" },
+        "Enable boot SPI auxiliary control pins":       { "value": false },
+        "Boot SPI CRTM size":                           { "value": "0" },
+        "Host SPI CRTM size":                           { "value": "0" },
+        "Enable host SPI auxiliary control pins":       { "value": false },
+        "Enable GPIO Pass Through":                     { "value": false },
+        "Enable Dedicate GPIO Strap Pins":              { "value": false }
+    }
+}
diff --git a/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk/p10bmc/keys/IPS_P10BMCAspeedSBPubKey_1.pem b/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk/p10bmc/keys/IPS_P10BMCAspeedSBPubKey_1.pem
new file mode 100644
index 0000000..201494c
--- /dev/null
+++ b/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk/p10bmc/keys/IPS_P10BMCAspeedSBPubKey_1.pem
@@ -0,0 +1,14 @@
+-----BEGIN PUBLIC KEY-----
+MIICIjANBgkqhkiG9w0BAQEFAAOCAg8AMIICCgKCAgEAoJC0oCngd6B3hfyv+UwZ
+P6PuJ1K/eM2jaW+g01c+r9Qr/btmLPG1UK/UWZEesL5by9a42JK5LIz4yKOhfoE3
+kt6WWMC45dvuG6E3KyCBm/wwdv5GqF3gV+4KAO3ua8qjjYqRKm8JdMfa0cw2SDnz
+qDrBfuxz75g0dOnFJ6dMO6/gD4k1EXVUBqv9ltQ1v01jhfiboc0tp4AUsw2Q/jzI
+2upo5tmnjsRaqDXnAcEn9C7AdZkBlKKSjds7j9brlVY3Yqo10siVZu3ZFqum5rZF
+8EuuQYT1svPobxogDunr2s9P6c+FrqsbJLvjhGxzl0zLDHrG2ZRV/vMRh9yzYkz6
++Bo9ZM2qnIiSc+uxDUpWFAHvZMDKF2nNvjNSstxN5pYw7V0zcZIvz7PVdgcpd1tR
+yEduVlvS/cUrp+pi+3LbZNLmTXreSquaOin8hGRyQHP9z2hDlS8kjcZlt8TPZ2w2
+POrN0HDSAhYFpI3ELGdUnkV/U/XC/T5tTU6OoWuZMcNEzOlniprVhXyU42GqBf4w
+wI3ciuLQueD2ndmQbZKUdWOajxH0v28jS7Bvo4kpymphNcAhkjAzNwXjo6WBDHUg
+rvoPLOKL3V8k5A8gpxxjMqaheM28FFgggqVZv3IypKLF2mcInWskt5A2gDiCsbmb
+xrIf6Mocoh928gr4au6+pzcCAwEAAQ==
+-----END PUBLIC KEY-----
diff --git a/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk/p10bmc/keys/IPS_P10BMCAspeedSBPubKey_2.pem b/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk/p10bmc/keys/IPS_P10BMCAspeedSBPubKey_2.pem
new file mode 100644
index 0000000..88c13b5
--- /dev/null
+++ b/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk/p10bmc/keys/IPS_P10BMCAspeedSBPubKey_2.pem
@@ -0,0 +1,14 @@
+-----BEGIN PUBLIC KEY-----
+MIICIjANBgkqhkiG9w0BAQEFAAOCAg8AMIICCgKCAgEAkcYbcy89Tx1JGyUnHaOU
+t5KpvI/H4+aeHO+gtM33DMjnUfbe5mN7hbLJbTaFoDUSSkU4dFiBB/JiKI+nitWa
+E1UI0ZsBNbVeqrcLC6DzUbQgu12gxhV/2fQ6yZe/+9N9IOZUUengHg+L+naLJ7sr
+R3YPiB7uJP+Sot5wCSi41NnOWzsjg2DGeesksfvo/iY1WEeOsq6try/3mRAOFIDB
+zZXcLO6eHPOpGcjbVTffQBgyHTNMl0k5IBzKJw15fC1UxrRhEBXD95/B40UuY1qi
+1+4PnH5Cl2luYjgGRXtNNIECfAzH+NC/dxrjPC3XqtWQiWm/vep7C40YtqeRyz0c
+TgXVvR0YT6h+YrggDjeG7KgFlQfnK6ht6W1+eBG5Anb5WneqwM67C9h+qJZYI7vO
+tYWX67exPpeyBgzOqtT+mFATWp2msQS0eFwtIfAWu38t564oK4MObEG3kiZhK35/
+re1Ftlb744RsJNFkhloujZIwcJZeOaxYFTHwu2EiQxDy8qZaZV96j8RNop2yNav/
+IS2NhRLboxYjZ9Myk47feU9Gc10WkgC3YxyvLOVDlQCwVn1hH9jbCR+xga6UFM/o
+ukK30b8w8EKd1ZYst0L635Y9+IW+IgT2PCPLPekgquzCRQ9cfj4SZQz0e2cLB9WJ
+geDhL/US8m3G5fRh0sXn02MCAwEAAQ==
+-----END PUBLIC KEY-----
diff --git a/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk/p10bmc/keys/IPS_P10BMCAspeedSBPubKey_3.pem b/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk/p10bmc/keys/IPS_P10BMCAspeedSBPubKey_3.pem
new file mode 100644
index 0000000..62104fa
--- /dev/null
+++ b/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk/p10bmc/keys/IPS_P10BMCAspeedSBPubKey_3.pem
@@ -0,0 +1,14 @@
+-----BEGIN PUBLIC KEY-----
+MIICIjANBgkqhkiG9w0BAQEFAAOCAg8AMIICCgKCAgEAmbmPMF8HfylRxBULIBSK
+PO48gseXXNAfy+rlHFO+kOm5cM0AEdgp28NlQ/ndeGxHK3MNAJFGalGqVx4CkFIg
+2T12XYYPY5sZTkfPVfmGY3htiBU0BjRPTG5tEDwKHqs1ztUX2QSO6uwial6/mCF1
+uv6CDjBDvFkvrwec51d6bYXp6QxUjY/QWcQYEKcMHXsPqrsbsRUUAoCg0im5ZR1Y
+z1xVbXmtqxy9mI98bgwnwPdsPZR0dfOC35wMCx/YfUIXrT4/onTMe+YHGTnWU0yg
+mpmbiiac0YQeRm7q3P3ca2WCPz3I943m99R++/uvfsR9syb2UXesKzj/sNbjDbhz
+1KLmVtOP91FSY1bVNLCWzXBuIilPs/wXZsS8pKOqTJIKJ3fp0kLUumBZ+DRJz4Zy
+idDTldffc5lh1CbT8Y56b+sXHB+M02Qg36zUv1MpZ6nmCvyQ+kaptqi51uMrocyA
+KDhp8d1/LnCEmJAvxQVl4Xalkmi5hZoCUjF9JAS9MFAYL7LK1zncQGLBVGWY/UD8
+yiAJZU1BGeoWhmYuNNItUQrOYYn9tU31uOVLHK0hUuAkVsxtZV/rTbluusa0x3sc
+Kdhh28R26JZxGoYyQMVp7a97gCHY8HIyxlFZgLK5iG5Y7LVIjap7XOTptOc7fQnN
+aH4bDyp679CUv/qzBPtKxw8CAwEAAQ==
+-----END PUBLIC KEY-----
diff --git a/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk_2019.04.bbappend b/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk_2019.04.bbappend
index c323789..b805587 100644
--- a/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk_2019.04.bbappend
+++ b/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk_2019.04.bbappend
@@ -1,8 +1,8 @@
 FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:"
 
-SRC_URI:append:p10bmc = " file://ibm.json file://keys/"
+SRC_URI:append:p10bmc = " file://ibm.json file://ips.json file://keys/"
 
-OTPTOOL_CONFIGS:p10bmc = "${WORKDIR}/ibm.json"
+OTPTOOL_CONFIGS:p10bmc = "${WORKDIR}/ibm.json ${WORKDIR}/ips.json"
 OTPTOOL_KEY_DIR:p10bmc = "${WORKDIR}/keys/"
 
 # !!! Do not copy p10bmc's use of little-endian key ordering !!!