commit 1282039d5fbe1c720a84021ea9e5db27795dc309
author Joel Stanley <joel@jms.id.au> Tue Sep 10 15:41:53 2019 +0100
committer Brad Bishop <bradleyb@fuzziesquirrel.com> Mon Sep 16 07:40:55 2019 -0400
tree 3bba0c50a4e2ac07545fcc3f3674cfc34099b470
parent 697f17de7a71b3dd9a6a0f37a2394b5525970c1c

aspeed-u-boot-sdk: Update to latest dev commit

Chia-Wei, Wang (3):
      ast2600: add CA7 cache and SRAM parity check
      ast2600: revise the boot initialization flow
      wdt: aspeed: fix compile warning

Dylan Hung (7):
      [update] revise memory reservation
      [debug] apply DDR4 100M setting
      [update] add config for DDR-400
      [update] slower HPLL
      [update] adjust cpu timer according to the HPLL
      [update] fine tune DDR-PHY param
      [fix] fix DDR-PHY training hangup

ryan_chen (6):
      update pcie driver
      add pcie rc pinctrl
      add two pcie rc
      add support two
      add default pcie at ast2600-evb dts
      update ast2600 fmc interrupt #no

(From meta-aspeed rev: 7daf7145abdd5499da5ebb25f4f214712b596562)

Change-Id: I0cf2c21a605683472f9dcdc4516d7c4f5d7858e5
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>

meta-aspeed/recipes-bsp/u-boot/u-boot-common-aspeed-sdk_2019.04.inc

diff --git a/meta-aspeed/recipes-bsp/u-boot/u-boot-common-aspeed-sdk_2019.04.inc b/meta-aspeed/recipes-bsp/u-boot/u-boot-common-aspeed-sdk_2019.04.inc
index c25bb6d..83341e4 100644
--- a/meta-aspeed/recipes-bsp/u-boot/u-boot-common-aspeed-sdk_2019.04.inc
+++ b/meta-aspeed/recipes-bsp/u-boot/u-boot-common-aspeed-sdk_2019.04.inc
@@ -8,7 +8,7 @@
 
 # We use the revision in order to avoid having to fetch it from the
 # repo during parse
-SRCREV = "9b5fc98374593c49133b709f71119222ecfff3eb"
+SRCREV = "4d29b04c7aca4121d542b759575fbb93e52aef47"
 
 UBRANCH = "aspeed-dev-v2019.04"
 SRC_URI = "git://github.com/AspeedTech-BMC/u-boot;branch=${UBRANCH};protocol=https"