commit 38642242445c33ace515302e24c95bbc31eeb2f7
author Andrew Geissler <openbmcbump-github@yahoo.com> Tue Mar 10 22:50:31 2020 +0000
committer Andrew Geissler <geissonator@yahoo.com> Tue Mar 17 09:03:04 2020 -0500
tree a01bfe2474c0b8334ba75795b96d67779418142e
parent 05d82c8093d2cfe6db1dcd17ba94fb4b2d2cbc14

intel-ipmi-oem: srcrev bump 32825a2332..eaeb6cb06c

Yong Li (3):
      Enable sensitive ME commands in MFG mode
      Add clear cmos OEM command into white list
      Change CPLD clear cmos command register is changed to 0x61

(From meta-intel rev: 63ec0a9ab49aff56d87b4f15e1c146af947379a1)

Change-Id: Ie8147e37d3694b7150d282b178145b33a5219204
Signed-off-by: Andrew Geissler <openbmcbump-github@yahoo.com>
Signed-off-by: Andrew Geissler <geissonator@yahoo.com>

meta-intel/meta-common/recipes-intel/ipmi/intel-ipmi-oem_git.bb

diff --git a/meta-intel/meta-common/recipes-intel/ipmi/intel-ipmi-oem_git.bb b/meta-intel/meta-common/recipes-intel/ipmi/intel-ipmi-oem_git.bb
index 4d26553..9fd481a 100755
--- a/meta-intel/meta-common/recipes-intel/ipmi/intel-ipmi-oem_git.bb
+++ b/meta-intel/meta-common/recipes-intel/ipmi/intel-ipmi-oem_git.bb
@@ -5,7 +5,7 @@
 LIC_FILES_CHKSUM = "file://LICENSE;md5=a6a4edad4aed50f39a66d098d74b265b"
 
 SRC_URI = "git://github.com/openbmc/intel-ipmi-oem"
-SRCREV = "32825a23324c2cf051bb5608348b8ea2109a36b5"
+SRCREV = "eaeb6cb06c9826bc18dd7d4251cefb63905f2d5d"
 
 S = "${WORKDIR}/git"
 PV = "0.1+git${SRCPV}"