commit 4f0996c93c0a1231756a2561477e991016de8a4a
author Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com> Thu Jan 11 17:44:43 2024 +0800
committer Patrick Williams <patrick@stwcx.xyz> Fri Jan 12 15:24:17 2024 +0000
tree 3a22238bfbfce1cd9c86e004e3903b1a7d34bbe0
parent 9db76818cbdcae900f5eea1b070abda29ae6784c

meta-facebook: yosemite4: Revise i/o config for medusa board's schematic changes

Revise medusa board i/o initialization for EVT schematic changes

Tested: Verified with yosemite4 POC/EVT medusa board

Change-Id: Iae1809de1b0ada79425a59f124387b974e22d168
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>

meta-facebook/meta-yosemite4/recipes-yosemite4/plat-svc/files/yosemite4-schematic-init

diff --git a/meta-facebook/meta-yosemite4/recipes-yosemite4/plat-svc/files/yosemite4-schematic-init b/meta-facebook/meta-yosemite4/recipes-yosemite4/plat-svc/files/yosemite4-schematic-init
new file mode 100644
index 0000000..a68839e
--- /dev/null
+++ b/meta-facebook/meta-yosemite4/recipes-yosemite4/plat-svc/files/yosemite4-schematic-init
@@ -0,0 +1,45 @@
+#!/bin/bash -e
+# shellcheck source=meta-facebook/meta-yosemite4/recipes-yosemite4/plat-tool/files/yosemite4-common-functions
+source /usr/libexec/yosemite4-common-functions
+
+# probe devices behind mux for management board cpld
+
+stage=$(busctl introspect xyz.openbmc_project.FruDevice /xyz/openbmc_project/FruDevice/Medusa_Board | grep '.PRODUCT_VERSION' | awk -F\" '{print $2}')
+
+# set initial value for pca9555 i/o pins on medusa board
+if [ -z "$stage" ]; then
+    echo "Failed to check medusa board fru info, all I/O pins are keeping default input"
+elif [ "$stage" = "POC" ]; then
+    set_gpio P48V_OCP_GPIO1       0
+    set_gpio P48V_OCP_GPIO2       0
+    set_gpio P48V_OCP_GPIO3       0
+    set_gpio RST_MUX_R_N          1
+    set_gpio RST_LED_CONTROL_FAN_BOARD_0_N 1
+    set_gpio RST_LED_CONTROL_FAN_BOARD_1_N 1
+    set_gpio RST_IOEXP_FAN_BOARD_0_N       1
+    set_gpio RST_IOEXP_FAN_BOARD_1_N       1
+    set_gpio HSC_OCP_SLOT_ODD_GPIO3        1
+    set_gpio HSC_OCP_SLOT_EVEN_GPIO1       1
+    set_gpio MEDUSA_BOARD_REV_0   0
+    set_gpio MEDUSA_BOARD_REV_1   0
+    set_gpio MEDUSA_BOARD_REV_2   0
+    set_gpio MEDUSA_BOARD_TYPE    0
+    set_gpio DELTA_MODULE_TYPE    0
+    set_gpio P12V_HSC_TYPE        0
+else
+    set_gpio P48V_OCP_GPIO1       0
+    set_gpio P48V_OCP_GPIO2       0
+    set_gpio P48V_OCP_GPIO3       0
+    set_gpio RST_MUX_R_N          1
+    set_gpio RST_LED_CONTROL_FAN_BOARD_0_N 1
+    set_gpio RST_LED_CONTROL_FAN_BOARD_1_N 1
+    set_gpio RST_IOEXP_FAN_BOARD_0_N       1
+    set_gpio RST_IOEXP_FAN_BOARD_1_N       1
+    set_gpio HSC_OCP_SLOT_ODD_GPIO1        0
+    set_gpio HSC_OCP_SLOT_ODD_GPIO2        0
+    set_gpio HSC_OCP_SLOT_ODD_GPIO3        0
+    set_gpio HSC_OCP_SLOT_EVEN_GPIO1       0
+    set_gpio HSC_OCP_SLOT_EVEN_GPIO2       0
+    set_gpio HSC_OCP_SLOT_EVEN_GPIO3       0
+fi
+exit 0