commit 5f77a546b9be0d7dad7ddf905742575896a92ed2
author Benjamin Fair <benjaminfair@google.com> Fri Dec 16 06:44:56 2022 +0000
committer Benjamin Fair <benjaminfair@google.com> Mon Dec 19 04:44:04 2022 +0000
tree f7ddaf3f4746b099f0ef6c8610ae079bbec762ef
parent 586f5116beeea6a17a626cb05e4214e7d4c4b86b

meta-nuvoton: npcm8xx-bootblock: update to 0.2.8

Changelog:

version 0.2.8     - Nov 22 2022
=============
- Bug fix: disable RECALIB in DDR, after training, before sweep phase.
- eSPI: enable auto handshake.

Version 0.2.6     - Oct 26 2022
=============
- Bug fix: If DRAM is 2GB and max DRAM size in header is smaller, GMMAP
  should be set according to header, not according to the physical
  device.

Version 0.2.4     - Oct 18 2022
=============
- MC: Support 2GB DRAM
- MC: Updated TRFC default to 2GB DRAM and fixed value for 1600/1G
- CLK: always set PLLs by bootblock. Set all dividers in PORST.
- SPI-X: upper limit of 33MHz.

Signed-off-by: Benjamin Fair <benjaminfair@google.com>
Change-Id: Ia82fba195139d245ccb7f62218a900069c575e2c

meta-nuvoton/recipes-bsp/images/npcm8xx-bootblock_0.2.8.bb

diff --git a/meta-nuvoton/recipes-bsp/images/npcm8xx-bootblock_0.2.8.bb b/meta-nuvoton/recipes-bsp/images/npcm8xx-bootblock_0.2.8.bb
new file mode 100644
index 0000000..9ef8e65
--- /dev/null
+++ b/meta-nuvoton/recipes-bsp/images/npcm8xx-bootblock_0.2.8.bb
@@ -0,0 +1,6 @@
+SRCREV = "4002b2f086f6d2177ec36bed507241386d604f6b"
+RELEASE = "A35_BootBlock_0.2.8"
+
+SRC_URI[bin.sha256sum] = "164c5e57d02accd61c14b6e13dff3dbbbe1d64375ca6ee97da50b9850dfb7f49"
+
+require npcm8xx-bootblock.inc