diff --git a/meta-ampere/meta-jade/conf/machine/mtjade.conf b/meta-ampere/meta-jade/conf/machine/mtjade.conf
index b425575..a47ebef 100644
--- a/meta-ampere/meta-jade/conf/machine/mtjade.conf
+++ b/meta-ampere/meta-jade/conf/machine/mtjade.conf
@@ -5,6 +5,7 @@
 require conf/machine/include/ast2500.inc
 require conf/machine/include/obmc-bsp-common.inc
 require conf/distro/include/phosphor-isolation.inc
+require conf/distro/include/phosphor-aspeed-spi-master-mode.inc
 
 # Reformat SPI flash layout to 64MB
 FLASH_SIZE = "65536"
diff --git a/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0004-aspeed-add-gpio-support.patch b/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0004-aspeed-add-gpio-support.patch
deleted file mode 100644
index 2f8ff45..0000000
--- a/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0004-aspeed-add-gpio-support.patch
+++ /dev/null
@@ -1,518 +0,0 @@
-From 7372552ae247e4870fb6dc80df7610f86d736a57 Mon Sep 17 00:00:00 2001
-From: Chanh Nguyen <chanh@os.amperecomputing.com>
-Date: Tue, 9 Mar 2021 11:04:56 +0700
-Subject: [PATCH] aspeed: add gpio support
-
-This is an initial support for the parallel GPIO pins directly connected
-to the AHB on the Aspeed 2400/2500.
-
-This brings the functions and a shell command to manipulate the GPIO
-state. The GPIO value reading and writing work in non interrupt mode
-only.
-
-This is back ported from the patch file from
-meta-yadro/meta-nicole/recipes-bsp/u-boot/files/0003-aspeed-add-gpio-support.patch
-to support GPIO configuration
-
-Signed-off-by: Alexander Filippov <a.filippov@yadro.com>
-Signed-off-by: Thang Q. Nguyen <thangqn@amperecomputing.com>
-Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com>
----
- arch/arm/include/asm/arch-aspeed/gpio.h |  65 ++++
- drivers/gpio/Makefile                   |   2 +
- drivers/gpio/aspeed_gpio.c              | 386 ++++++++++++++++++++++++
- include/configs/ast-g5-phy.h            |   1 +
- 4 files changed, 454 insertions(+)
- create mode 100644 arch/arm/include/asm/arch-aspeed/gpio.h
- create mode 100644 drivers/gpio/aspeed_gpio.c
-
-diff --git a/arch/arm/include/asm/arch-aspeed/gpio.h b/arch/arm/include/asm/arch-aspeed/gpio.h
-new file mode 100644
-index 0000000000..c63987e917
---- /dev/null
-+++ b/arch/arm/include/asm/arch-aspeed/gpio.h
-@@ -0,0 +1,65 @@
-+/*
-+ * SPDX-License-Identifier: GPL-2.0+
-+ * Copyright (C) 2020 YADRO.
-+ */
-+#ifndef _ASPEED_GPIO_H
-+#define _ASPEED_GPIO_H
-+
-+#define ASPEED_GPIO_PORT_A 0
-+#define ASPEED_GPIO_PORT_B 1
-+#define ASPEED_GPIO_PORT_C 2
-+#define ASPEED_GPIO_PORT_D 3
-+#define ASPEED_GPIO_PORT_E 4
-+#define ASPEED_GPIO_PORT_F 5
-+#define ASPEED_GPIO_PORT_G 6
-+#define ASPEED_GPIO_PORT_H 7
-+#define ASPEED_GPIO_PORT_I 8
-+#define ASPEED_GPIO_PORT_J 9
-+#define ASPEED_GPIO_PORT_K 10
-+#define ASPEED_GPIO_PORT_L 11
-+#define ASPEED_GPIO_PORT_M 12
-+#define ASPEED_GPIO_PORT_N 13
-+#define ASPEED_GPIO_PORT_O 14
-+#define ASPEED_GPIO_PORT_P 15
-+#define ASPEED_GPIO_PORT_Q 16
-+#define ASPEED_GPIO_PORT_R 17
-+#define ASPEED_GPIO_PORT_S 18
-+#define ASPEED_GPIO_PORT_T 19
-+#define ASPEED_GPIO_PORT_U 20
-+#define ASPEED_GPIO_PORT_V 21
-+#define ASPEED_GPIO_PORT_W 22
-+#define ASPEED_GPIO_PORT_X 23
-+#define ASPEED_GPIO_PORT_Y 24
-+#define ASPEED_GPIO_PORT_Z 25
-+#define ASPEED_GPIO_PORT_AA 26
-+#define ASPEED_GPIO_PORT_AB 27
-+#define ASPEED_GPIO_PORT_AC 28
-+
-+#define ASPEED_GPIO_PORT_SHIFT 3
-+#define ASPEED_GPIO_PIN_MASK 0x7
-+#define ASPEED_GPIO(port, pin)                                                 \
-+    ((ASPEED_GPIO_PORT_##port << ASPEED_GPIO_PORT_SHIFT) |                     \
-+     (pin & ASPEED_GPIO_PIN_MASK))
-+
-+/* Direction values */
-+#define ASPEED_GPIO_INPUT 0
-+#define ASPEED_GPIO_OUTPUT 1
-+
-+/* Trigger values */
-+#define ASPEED_GPIO_FALLING_EDGE 0
-+#define ASPEED_GPIO_RISING_EDGE 1
-+#define ASPEED_GPIO_LOW_LEVEL 2
-+#define ASPEED_GPIO_HIGH_LEVEL 3
-+#define ASPEED_GPIO_DUAL_EDGE 4
-+
-+/* Debounce values */
-+#define ASPEED_GPIO_DEBOUNCE_NONE 0
-+#define ASPEED_GPIO_DEBOUNCE_1 1
-+#define ASPEED_GPIO_DEBOUNCE_2 2
-+#define ASPEED_GPIO_DEBOUNCE_3 3
-+
-+#define gpio_status() gpio_info()
-+
-+extern void gpio_info(void);
-+
-+#endif /* #ifndef _ASPEED_GPIO_H */
-diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
-index 792d19186a..5f043e07ce 100644
---- a/drivers/gpio/Makefile
-+++ b/drivers/gpio/Makefile
-@@ -14,6 +14,8 @@ obj-$(CONFIG_DM_GPIO)		+= gpio-uclass.o
- obj-$(CONFIG_DM_PCA953X)	+= pca953x_gpio.o
- obj-$(CONFIG_DM_74X164)		+= 74x164_gpio.o
- 
-+obj-$(CONFIG_ARCH_AST2400)	+= aspeed_gpio.o
-+obj-$(CONFIG_ARCH_AST2500)	+= aspeed_gpio.o
- obj-$(CONFIG_AT91_GPIO)	+= at91_gpio.o
- obj-$(CONFIG_ATMEL_PIO4)	+= atmel_pio4.o
- obj-$(CONFIG_INTEL_ICH6_GPIO)	+= intel_ich6_gpio.o
-diff --git a/drivers/gpio/aspeed_gpio.c b/drivers/gpio/aspeed_gpio.c
-new file mode 100644
-index 0000000000..dc07f5a520
---- /dev/null
-+++ b/drivers/gpio/aspeed_gpio.c
-@@ -0,0 +1,386 @@
-+/*
-+ * SPDX-License-Identifier: GPL-2.0+
-+ * Copyright (C) 2020 YADRO.
-+ */
-+
-+#include <common.h>
-+
-+#include <asm/arch/gpio.h>
-+#include <asm/arch/platform.h>
-+#include <asm/io.h>
-+#include <linux/ctype.h>
-+
-+typedef struct _ast_gpio_regs
-+{
-+    uint32_t base;     /* data and direction registers */
-+    uint32_t intcfg;   /* interrupt config */
-+    uint32_t debounce; /* debounce config */
-+    uint32_t cmdsrc;   /* command source config */
-+    uint32_t data;     /* data read register */
-+} ast_gpio_regs_t;
-+
-+static ast_gpio_regs_t ast_gpio_regs[] = {
-+    /* A/B/C/D */
-+    {AST_GPIO_BASE + 0x0000, AST_GPIO_BASE + 0x0008, AST_GPIO_BASE + 0x0040,
-+     AST_GPIO_BASE + 0x0060, AST_GPIO_BASE + 0x00C0},
-+    /* E/F/G/H */
-+    {AST_GPIO_BASE + 0x0020, AST_GPIO_BASE + 0x0028, AST_GPIO_BASE + 0x0048,
-+     AST_GPIO_BASE + 0x0068, AST_GPIO_BASE + 0x00C4},
-+    /* I/J/K/L */
-+    {AST_GPIO_BASE + 0x0070, AST_GPIO_BASE + 0x0098, AST_GPIO_BASE + 0x00B0,
-+     AST_GPIO_BASE + 0x0090, AST_GPIO_BASE + 0x00C8},
-+    /* M/N/O/P */
-+    {AST_GPIO_BASE + 0x0078, AST_GPIO_BASE + 0x00E8, AST_GPIO_BASE + 0x0100,
-+     AST_GPIO_BASE + 0x00E0, AST_GPIO_BASE + 0x00CC},
-+    /* Q/R/S/T */
-+    {AST_GPIO_BASE + 0x0080, AST_GPIO_BASE + 0x0118, AST_GPIO_BASE + 0x0130,
-+     AST_GPIO_BASE + 0x0110, AST_GPIO_BASE + 0x00D0},
-+    /* U/V/W/X */
-+    {AST_GPIO_BASE + 0x0088, AST_GPIO_BASE + 0x0148, AST_GPIO_BASE + 0x0160,
-+     AST_GPIO_BASE + 0x0140, AST_GPIO_BASE + 0x00D4},
-+    /* Y/Z/AA/AB */
-+    {AST_GPIO_BASE + 0x01E0, AST_GPIO_BASE + 0x0178, AST_GPIO_BASE + 0x0190,
-+     AST_GPIO_BASE + 0x0170, AST_GPIO_BASE + 0x00D8},
-+    /* AC */
-+    {AST_GPIO_BASE + 0x01E8, AST_GPIO_BASE + 0x01A8, AST_GPIO_BASE + 0x01C0,
-+     AST_GPIO_BASE + 0x01A0, AST_GPIO_BASE + 0x00DC},
-+};
-+
-+#define AST_GPIO_PINS_PER_PORT 8
-+#define AST_GPIO_PORTS_PER_REGISTER 4
-+
-+#define AST_GPIO_PORT(gpio) (gpio >> ASPEED_GPIO_PORT_SHIFT)
-+#define AST_GPIO_PIN(gpio) (gpio & ASPEED_GPIO_PIN_MASK)
-+#define AST_GPIO_SHIFT(gpio)                                                   \
-+    ((AST_GPIO_PORT(gpio) % AST_GPIO_PORTS_PER_REGISTER) *                     \
-+         AST_GPIO_PINS_PER_PORT +                                              \
-+     AST_GPIO_PIN(gpio))
-+
-+#define AST_GPIO_REG_INDEX(gpio)                                               \
-+    (AST_GPIO_PORT(gpio) / AST_GPIO_PORTS_PER_REGISTER)
-+
-+/**
-+ * @return Pointer to corresponding item from ast_gpio_regs table.
-+ */
-+#define AST_GPIO_REGS(gpio)                                                    \
-+    ((AST_GPIO_REG_INDEX(gpio) < ARRAY_SIZE(ast_gpio_regs))                    \
-+         ? (ast_gpio_regs + AST_GPIO_REG_INDEX(gpio))                          \
-+         : NULL)
-+
-+/**
-+ * @brief Set a corresponding bit in specified register.
-+ *
-+ * @param val - Required bit value
-+ * @param base - Register address
-+ * @param shift - Bit index.
-+ */
-+#define AST_GPIO_WRITE(val, base, shift)                                       \
-+    writel(((val) ? readl(base) | (1 << (shift))                               \
-+                  : readl(base) & ~(1 << (shift))),                            \
-+           base)
-+
-+/**
-+ * @brief Get value of corresponging bit from specified register.
-+ *
-+ * @param base - Register address
-+ * @param shift - Bit index
-+ *
-+ * @return Bit value
-+ */
-+#define AST_GPIO_READ(base, shift) ((readl(base) >> (shift)) & 1)
-+
-+#define IS_VALID_GPIO(gpio)                                                    \
-+    ((gpio) >= ASPEED_GPIO(A, 0) && (gpio) <= ASPEED_GPIO(AC, 7))
-+
-+#define AST_GPIO_DIRECTION 0x04
-+#define AST_GPIO_INT_SENS0 0x04
-+#define AST_GPIO_INT_SENS1 0x08
-+#define AST_GPIO_INT_SENS2 0x0C
-+#define AST_GPIO_INT_STATUS 0x10
-+#define AST_GPIO_DEBOUNCE0 0x00
-+#define AST_GPIO_DEBOUNCE1 0x04
-+#define AST_GPIO_CMD_SRC0 0x00
-+#define AST_GPIO_CMD_SRC1 0x04
-+
-+/**
-+ * @brief Set a GPIO direction
-+ *
-+ * @param gpio      GPIO line
-+ * @param direction GPIO direction (0 for input or 1 for output)
-+ *
-+ * @return 0 if ok, -1 on error
-+ */
-+static int ast_gpio_set_direction(unsigned gpio, unsigned direction)
-+{
-+    ast_gpio_regs_t *regs = AST_GPIO_REGS(gpio);
-+    if (!regs)
-+    {
-+        printf("%s: Invalid GPIO!\n", __func__);
-+        return -1;
-+    }
-+
-+    AST_GPIO_WRITE(direction, regs->base + AST_GPIO_DIRECTION,
-+                   AST_GPIO_SHIFT(gpio));
-+    return 0;
-+}
-+
-+/**
-+ * The 6 following functions are generic u-boot gpio implementation.
-+ * They are declared in `include/asm-generic/gpio.h`
-+ */
-+
-+int gpio_request(unsigned gpio, const char *label)
-+{
-+    return (IS_VALID_GPIO(gpio) ? 0 : -1);
-+}
-+
-+int gpio_free(unsigned gpio)
-+{
-+    return (IS_VALID_GPIO(gpio) ? 0 : -1);
-+}
-+
-+int gpio_get_value(unsigned gpio)
-+{
-+    ast_gpio_regs_t *regs = AST_GPIO_REGS(gpio);
-+    if (!regs)
-+    {
-+        printf("%s: Invalid GPIO!\n", __func__);
-+        return -1;
-+    }
-+
-+    return AST_GPIO_READ(regs->base, AST_GPIO_SHIFT(gpio));
-+}
-+
-+int gpio_set_value(unsigned gpio, int value)
-+{
-+    ast_gpio_regs_t *regs = AST_GPIO_REGS(gpio);
-+    if (!regs)
-+    {
-+        printf("%s: Invalid GPIO!\n", __func__);
-+        return -1;
-+    }
-+
-+    AST_GPIO_WRITE(value, regs->base, AST_GPIO_SHIFT(gpio));
-+    return 0;
-+}
-+
-+int gpio_direction_input(unsigned gpio)
-+{
-+    return ast_gpio_set_direction(gpio, ASPEED_GPIO_INPUT);
-+}
-+
-+int gpio_direction_output(unsigned gpio, int value)
-+{
-+    int rc = ast_gpio_set_direction(gpio, ASPEED_GPIO_OUTPUT);
-+    return (rc == 0 ? gpio_set_value(gpio, value) : rc);
-+}
-+
-+/**
-+ * @brief Convert a string to GPIO line. Used by `do_gpio()` from `cmd/gpio.c`
-+ *
-+ * @param str a GPIO name or line number
-+ *
-+ * @return GPIO line if ok, -1 on error
-+ */
-+int name_to_gpio(const char *str)
-+{
-+    int gpio = -1;
-+
-+    if (str)
-+    {
-+        if (isalpha(*str))
-+        {
-+            gpio = (toupper(*str) - 'A') << ASPEED_GPIO_PORT_SHIFT;
-+
-+            if (toupper(*str) == 'A' && toupper(*(str + 1)) >= 'A' &&
-+                toupper(*(str + 1)) <= 'C')
-+            {
-+                str++;
-+                gpio = (ASPEED_GPIO_PORT_AA + toupper(*str) - 'A')
-+                       << ASPEED_GPIO_PORT_SHIFT;
-+            }
-+
-+            str++;
-+            if (*str >= '0' && *str <= '7' && !*(str + 1))
-+            {
-+                gpio += *str - '0';
-+            }
-+            else
-+            {
-+                gpio = -1;
-+            }
-+        }
-+        else if (isdigit(*str))
-+        {
-+            gpio = simple_strtoul(str, NULL, 0);
-+        }
-+    }
-+
-+    return gpio;
-+}
-+
-+/**
-+ * @return A GPIO direction in human readable format.
-+ */
-+static const char *ast_gpio_direction(unsigned gpio)
-+{
-+    ast_gpio_regs_t *regs = AST_GPIO_REGS(gpio);
-+    if (regs)
-+    {
-+        int direction = AST_GPIO_READ(regs->base + AST_GPIO_DIRECTION,
-+                                      AST_GPIO_SHIFT(gpio));
-+        switch (direction)
-+        {
-+            case ASPEED_GPIO_INPUT:
-+                return "input";
-+            case ASPEED_GPIO_OUTPUT:
-+                return "output";
-+            default:
-+                break;
-+        }
-+    }
-+    return "error";
-+}
-+
-+/**
-+ * @return An interrupt trigger settings in human readable format.
-+ */
-+static const char *ast_gpio_trigger(unsigned gpio)
-+{
-+    ast_gpio_regs_t *regs = AST_GPIO_REGS(gpio);
-+    if (regs)
-+    {
-+        unsigned shift = AST_GPIO_SHIFT(gpio);
-+        unsigned trigger =
-+            (AST_GPIO_READ(regs->intcfg + AST_GPIO_INT_SENS0, shift) << 0) |
-+            (AST_GPIO_READ(regs->intcfg + AST_GPIO_INT_SENS1, shift) << 1) |
-+            (AST_GPIO_READ(regs->intcfg + AST_GPIO_INT_SENS2, shift) << 2);
-+
-+        switch (trigger)
-+        {
-+            case ASPEED_GPIO_FALLING_EDGE:
-+                return "fall";
-+            case ASPEED_GPIO_RISING_EDGE:
-+                return "rise";
-+            case ASPEED_GPIO_LOW_LEVEL:
-+                return "low ";
-+            case ASPEED_GPIO_HIGH_LEVEL:
-+                return "high";
-+            default:
-+                return "both";
-+        }
-+    }
-+    return "error";
-+}
-+
-+/**
-+ * @return An interrupt status in human readable format.
-+ */
-+static const char *ast_gpio_int_status(unsigned gpio)
-+{
-+    ast_gpio_regs_t *regs = AST_GPIO_REGS(gpio);
-+    if (regs)
-+    {
-+        unsigned shift = AST_GPIO_SHIFT(gpio);
-+        if (AST_GPIO_READ(regs->intcfg, shift))
-+        {
-+            return AST_GPIO_READ(regs->intcfg + AST_GPIO_INT_STATUS, shift)
-+                       ? "pending"
-+                       : "cleaned";
-+        }
-+        return "disabled";
-+    }
-+
-+    return "error";
-+}
-+
-+/**
-+ * @return A debounce value in human readable format.
-+ */
-+static const char *ast_gpio_debounce(unsigned gpio)
-+{
-+    ast_gpio_regs_t *regs = AST_GPIO_REGS(gpio);
-+    if (regs)
-+    {
-+        unsigned shift = AST_GPIO_SHIFT(gpio);
-+        unsigned debounce =
-+            (AST_GPIO_READ(regs->debounce + AST_GPIO_DEBOUNCE0, shift) << 0) |
-+            (AST_GPIO_READ(regs->debounce + AST_GPIO_DEBOUNCE1, shift) << 1);
-+        switch (debounce)
-+        {
-+            case ASPEED_GPIO_DEBOUNCE_NONE:
-+                return "none";
-+            case ASPEED_GPIO_DEBOUNCE_1:
-+                return "timer1";
-+            case ASPEED_GPIO_DEBOUNCE_2:
-+                return "timer2";
-+            case ASPEED_GPIO_DEBOUNCE_3:
-+                return "timer3";
-+            default:
-+                break;
-+        }
-+    }
-+
-+    return "error";
-+}
-+
-+/**
-+ * @return A command source value in human readable format.
-+ */
-+static const char *ast_gpio_command_source(unsigned gpio)
-+{
-+    ast_gpio_regs_t *regs = AST_GPIO_REGS(gpio);
-+    if (regs)
-+    {
-+        /* Used one bit per gpio port */
-+        unsigned shift = AST_GPIO_SHIFT(gpio) - AST_GPIO_PIN(gpio);
-+        unsigned cmdsrc =
-+            (AST_GPIO_READ(regs->cmdsrc + AST_GPIO_CMD_SRC0, shift) << 0) |
-+            (AST_GPIO_READ(regs->cmdsrc + AST_GPIO_CMD_SRC1, shift) << 1);
-+
-+        switch (cmdsrc)
-+        {
-+            /* The single place where these values are used is here. */
-+            case 0x0:
-+                return "ARM";
-+            case 0x1:
-+                return "LPC";
-+            case 0x2:
-+                return "CoCPU";
-+            default:
-+                return "Unknown";
-+        }
-+    }
-+
-+    return "error";
-+}
-+
-+/**
-+ * @brief Show all GPIO pins statuses. Used by `do_gpio()` in `cmd/gpio.c`
-+ */
-+void gpio_info(void)
-+{
-+    unsigned first = ASPEED_GPIO(A, 0);
-+    unsigned last = ASPEED_GPIO(AC, 7);
-+    for (unsigned gpio = first; gpio <= last; gpio++)
-+    {
-+        unsigned port = AST_GPIO_PORT(gpio);
-+        unsigned pin = AST_GPIO_PIN(gpio);
-+        unsigned shift = AST_GPIO_SHIFT(gpio);
-+        ast_gpio_regs_t *regs = AST_GPIO_REGS(gpio);
-+        if (!regs)
-+        {
-+            printf("gpio %u is invalid!\n", gpio);
-+            continue;
-+        }
-+
-+        printf("gpio %c%c%c line %3d: %s, int: %s, %s, deb: %s, src: %s, "
-+               "val: %d/%d\n",
-+               (port >= ASPEED_GPIO_PORT_AA ? 'A' : ' '),
-+               ('A' + port % ASPEED_GPIO_PORT_AA), ('0' + pin), gpio,
-+               ast_gpio_direction(gpio), ast_gpio_trigger(gpio),
-+               ast_gpio_int_status(gpio), ast_gpio_debounce(gpio),
-+               ast_gpio_command_source(gpio), gpio_get_value(gpio),
-+               AST_GPIO_READ(regs->data, shift));
-+    }
-+}
-diff --git a/include/configs/ast-g5-phy.h b/include/configs/ast-g5-phy.h
-index 5443a26cab..ea7c66716a 100644
---- a/include/configs/ast-g5-phy.h
-+++ b/include/configs/ast-g5-phy.h
-@@ -32,5 +32,6 @@
- 
- /* Call board_late_init */
- #define CONFIG_BOARD_LATE_INIT		1
-+#define CONFIG_CMD_GPIO                1        /* Enable gpio command in shell */
- 
- #endif	/* __AST_G5_PHY_CONFIG_H */
--- 
-2.17.1
-
diff --git a/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0005-aspeed-Enable-SPI-master-mode.patch b/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0005-aspeed-Enable-SPI-master-mode.patch
deleted file mode 100644
index 0dd736f..0000000
--- a/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0005-aspeed-Enable-SPI-master-mode.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 0bf84de2a9db749bd61064cd47b96ef457725f54 Mon Sep 17 00:00:00 2001
-From: Chanh Nguyen <chanh@os.amperecomputing.com>
-Date: Wed, 10 Mar 2021 00:02:17 +0700
-Subject: [PATCH] aspeed: Enable SPI master mode
-
-Currently, some systems design the strap pin,
-which was shared pin with another function.
-That makes the board strapping does not reflect the intended use of the system.
-
-This patch will enable SPI master mode by default.
-
-Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com>
----
- board/aspeed/ast-g5/ast-g5.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c
-index 9e27bce0f5..ed83d65136 100644
---- a/board/aspeed/ast-g5/ast-g5.c
-+++ b/board/aspeed/ast-g5/ast-g5.c
-@@ -125,6 +125,9 @@ int board_late_init(void)
- 		update_bootargs_cmd("resetreason", value);
- 	}
- 
-+	/* enable SPI master */
-+	ast_scu_spi_master(1);
-+
- 	return 0;
- }
- #endif
--- 
-2.17.1
-
diff --git a/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0006-aspeed-support-Mt.Jade-platform-init.patch b/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0006-aspeed-support-Mt.Jade-platform-init.patch
deleted file mode 100644
index 02a4783..0000000
--- a/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed/0006-aspeed-support-Mt.Jade-platform-init.patch
+++ /dev/null
@@ -1,175 +0,0 @@
-From 2c9ab641f2a7ea146a468ec4301c416010badff7 Mon Sep 17 00:00:00 2001
-From: Chanh Nguyen <chanh@os.amperecomputing.com>
-Date: Wed, 17 Mar 2021 14:11:18 +0700
-Subject: [PATCH] aspeed: support Mt.Jade platform init
-
-This commit adds platform init for Mt.Jade platform.
-
-Signed-off-by: Thang Q. Nguyen <thang@os.amperecomputing.com>
-Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com>
----
- arch/arm/include/asm/arch-aspeed/ast_scu.h  |  1 +
- arch/arm/include/asm/arch-aspeed/regs-scu.h |  4 ++
- arch/arm/mach-aspeed/ast-scu.c              | 18 +++++
- board/aspeed/ast-g5/ast-g5.c                | 76 +++++++++++++++++++++
- include/configs/ast-g5-phy.h                |  3 +
- 5 files changed, 102 insertions(+)
-
-diff --git a/arch/arm/include/asm/arch-aspeed/ast_scu.h b/arch/arm/include/asm/arch-aspeed/ast_scu.h
-index f5c9126ec0..e2d06ccc1f 100644
---- a/arch/arm/include/asm/arch-aspeed/ast_scu.h
-+++ b/arch/arm/include/asm/arch-aspeed/ast_scu.h
-@@ -46,5 +46,6 @@ extern void ast_scu_init_eth(u8 num);
- extern void ast_scu_multi_func_eth(u8 num);
- extern void ast_scu_multi_func_romcs(u8 num);
- extern void ast_scu_switch_pwm_to_gpio_mode(void);
-+extern void ast_scu_switch_espi_to_gpio_mode(void);
- 
- #endif
-diff --git a/arch/arm/include/asm/arch-aspeed/regs-scu.h b/arch/arm/include/asm/arch-aspeed/regs-scu.h
-index b714fa9234..704ad75b4e 100644
---- a/arch/arm/include/asm/arch-aspeed/regs-scu.h
-+++ b/arch/arm/include/asm/arch-aspeed/regs-scu.h
-@@ -76,6 +76,7 @@
- #define AST_SCU_FUN_PIN_CTRL7	0xA0	/* Multi-function Pin Control#7*/
- #define AST_SCU_FUN_PIN_CTRL8	0xA4	/* Multi-function Pin Control#8*/
- #define AST_SCU_FUN_PIN_CTRL9	0xA8	/* Multi-function Pin Control#9*/
-+#define AST_SCU_FUN_PIN_CTRL10	0xAC	/* Multi-function Pin Control#10*/
- #define AST_SCU_MAC_CLK_DELAY_100M	0xB8	/* MAC interface clock delay 100M setting*/
- #define AST_SCU_MAC_CLK_DELAY_10M	0xBC	/* MAC interface clock delay 10M setting*/
- #define AST_SCU_PWR_SAVING_EN	0xC0	/* Power Saving Wakeup Enable*/
-@@ -921,6 +922,9 @@
- #define SCU_FUN_PIN_ROMA19		(0x1 << 1)
- #define SCU_FUN_PIN_ROMA18		(0x1)
- 
-+/* AST_SCU_FUN_PIN_CTRL10		0xAC - Multi-function Pin Control#10 */
-+#define SCU_FUN_PIN_ESPI(x)             (0x1 << (x))
-+
- /* AST_SCU_PWR_SAVING_EN		0xC0 - Power Saving Wakeup Enable */
- /* AST_SCU_PWR_SAVING_CTRL		0xC4 - Power Saving Wakeup Control */
- /* AST_SCU_HW_STRAP2			0xD0 - Haardware strapping register set 2 */
-diff --git a/arch/arm/mach-aspeed/ast-scu.c b/arch/arm/mach-aspeed/ast-scu.c
-index c7ab66415f..71c043d3e8 100644
---- a/arch/arm/mach-aspeed/ast-scu.c
-+++ b/arch/arm/mach-aspeed/ast-scu.c
-@@ -554,3 +554,21 @@ void ast_scu_get_who_init_dram(void)
- 		break;
- 	}
- }
-+
-+void ast_scu_switch_espi_to_gpio_mode(void)
-+{
-+	/*
-+	* This Function to set the ESPI pin to GPIO mode
-+	* This allow to setting AC5_READY
-+	*/
-+	ast_scu_write(ast_scu_read(AST_SCU_FUN_PIN_CTRL10) &
-+					 ~SCU_FUN_PIN_ESPI(0) &
-+					 ~SCU_FUN_PIN_ESPI(1) &
-+					 ~SCU_FUN_PIN_ESPI(2) &
-+					 ~SCU_FUN_PIN_ESPI(3) &
-+					 ~SCU_FUN_PIN_ESPI(4) &
-+					 ~SCU_FUN_PIN_ESPI(5) &
-+					 ~SCU_FUN_PIN_ESPI(6) &
-+					 ~SCU_FUN_PIN_ESPI(7),
-+					  AST_SCU_FUN_PIN_CTRL10);
-+}
-diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c
-index ed83d65136..edf7f050a8 100644
---- a/board/aspeed/ast-g5/ast-g5.c
-+++ b/board/aspeed/ast-g5/ast-g5.c
-@@ -163,3 +163,79 @@ void hw_watchdog_reset(void)
- 	writel(0x4755, AST_WDT2_BASE + 0x08);
- }
- #endif /* CONFIG_WATCHDOG */
-+
-+#ifdef CONFIG_BOARD_EARLY_INIT_F
-+int board_gpio_init(void)
-+{
-+	int pgood = 0;
-+
-+	/* GPIO_BMC_PSU_PG */
-+	pgood = gpio_get_value(44);
-+	/* GPIO_BMC_OCP_AUX_PWREN */
-+	gpio_direction_output(139, 1);
-+
-+	if (pgood)
-+	{
-+		/* GPIO_BMC_SYS_ATX_PSON_L */
-+		gpio_direction_output(42, 0);
-+		/* GPIO_BMC_OCP_MAIN_PWREN */
-+		gpio_direction_output(140, 1);
-+	}
-+	else
-+	{
-+		/* GPIO_BMC_SYS_ATX_PSON_L */
-+		gpio_direction_output(42, 1);
-+		/* GPIO_BMC_OCP_MAIN_PWREN */
-+		gpio_direction_output(140, 0);
-+	}
-+
-+	/* GPIOH7 GPIO_BMC_I2C6_RESET_L */
-+	gpio_direction_output(63, 1);
-+
-+	/* GPIOM4 S0_I2C9_ALERT_L */
-+	gpio_direction_input(100);
-+
-+	/* GPIOM5 S1_I2C9_ALERT_L */
-+	gpio_direction_input(101);
-+
-+	/* GPIOQ7 GPIO_BMC_VGA_FRONT_PRES_L */
-+	gpio_direction_input(135);
-+
-+	/* GPIOR1 GPIO_BMC_JTAG_SRST_L */
-+	gpio_direction_output(137, 1);
-+
-+	/* BMC_GPIOR2_EXT_HIGHTEMP_L */
-+	gpio_direction_output(138, 1);
-+
-+	/* GPIOS0 GPIO_S0_VRHOT_L */
-+	gpio_direction_input(144);
-+
-+	/* GPIOS1 GPIO_S1_VRHOT_L */
-+	gpio_direction_input(145);
-+
-+	/* GPIOS5 GPIO_BMC_VR_PMBUS_SEL_L */
-+	gpio_direction_output(149, 1);
-+
-+	/* GPIOY3 BMC_VGA_SEL */
-+	gpio_direction_output(195, 1);
-+
-+	/* GPIOAC1 GPIO_BMC_PCA9554_INT_L */
-+	gpio_direction_input(225);
-+
-+	/* GPIO_BMC_READY */
-+	gpio_direction_output(229, 1);
-+
-+	/* Enable I2C4 device access */
-+	gpio_direction_output(194, 1);
-+
-+	return 0;
-+}
-+
-+int board_early_init_f(void)
-+{
-+	ast_scu_switch_espi_to_gpio_mode();
-+	board_gpio_init();
-+
-+	return 0;
-+}
-+#endif /* CONFIG_BOARD_EARLY_INIT_F */
-diff --git a/include/configs/ast-g5-phy.h b/include/configs/ast-g5-phy.h
-index ea7c66716a..a5e389616b 100644
---- a/include/configs/ast-g5-phy.h
-+++ b/include/configs/ast-g5-phy.h
-@@ -34,4 +34,7 @@
- #define CONFIG_BOARD_LATE_INIT		1
- #define CONFIG_CMD_GPIO                1        /* Enable gpio command in shell */
- 
-+/* Call board_early_init_f */
-+#define CONFIG_BOARD_EARLY_INIT_F	1
-+
- #endif	/* __AST_G5_PHY_CONFIG_H */
--- 
-2.17.1
-
diff --git a/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend b/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend
index bda3d9d..6d0a5f8 100644
--- a/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend
+++ b/meta-ampere/meta-jade/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend
@@ -4,7 +4,4 @@
             file://0001-aspeed-scu-Switch-PWM-pin-to-GPIO-input-mode.patch \
             file://0002-aspeed-Disable-internal-PD-resistors-for-GPIOs.patch \
             file://0003-aspeed-support-passing-system-reset-status-to-kernel.patch \
-            file://0004-aspeed-add-gpio-support.patch \
-            file://0005-aspeed-Enable-SPI-master-mode.patch \
-            file://0006-aspeed-support-Mt.Jade-platform-init.patch \
            "