meta-facebook: minerva: revise the blade number sequence
In response to the request from the RTP team, the blade number sequence will be changed from 0-15 to 1-16 (for compute blades), 0-5 to 1-6 (for network blades), and the FCB numbering from top 0/1, mid 0/1, bottom 0/1 to FCB1-6, to align with the silkscreen labels on the rack.
Change-Id: If8967c26ff0105b588c38eb8267a21221d18712d
Signed-off-by: Yang Chen <yang.chen@quantatw.com>
diff --git a/meta-facebook/meta-minerva/recipes-minerva/plat-svc/files/minerva-early-sys-init b/meta-facebook/meta-minerva/recipes-minerva/plat-svc/files/minerva-early-sys-init
index 606790e..e22adc5 100644
--- a/meta-facebook/meta-minerva/recipes-minerva/plat-svc/files/minerva-early-sys-init
+++ b/meta-facebook/meta-minerva/recipes-minerva/plat-svc/files/minerva-early-sys-init
@@ -7,7 +7,6 @@
}
# set initial value for GPIO output pins
-set_gpio PWREN_MTIA_BLADE0_EN_N 0
set_gpio PWREN_MTIA_BLADE1_EN_N 0
set_gpio PWREN_MTIA_BLADE2_EN_N 0
set_gpio PWREN_MTIA_BLADE3_EN_N 0
@@ -23,15 +22,15 @@
set_gpio PWREN_MTIA_BLADE13_EN_N 0
set_gpio PWREN_MTIA_BLADE14_EN_N 0
set_gpio PWREN_MTIA_BLADE15_EN_N 0
+set_gpio PWREN_MTIA_BLADE16_EN_N 0
-set_gpio PWREN_NW_BLADE0_EN_N 0
set_gpio PWREN_NW_BLADE1_EN_N 0
set_gpio PWREN_NW_BLADE2_EN_N 0
set_gpio PWREN_NW_BLADE3_EN_N 0
set_gpio PWREN_NW_BLADE4_EN_N 0
set_gpio PWREN_NW_BLADE5_EN_N 0
+set_gpio PWREN_NW_BLADE6_EN_N 0
-set_gpio PWREN_MTIA_BLADE0_HSC_EN_N 0
set_gpio PWREN_MTIA_BLADE1_HSC_EN_N 0
set_gpio PWREN_MTIA_BLADE2_HSC_EN_N 0
set_gpio PWREN_MTIA_BLADE3_HSC_EN_N 0
@@ -47,29 +46,31 @@
set_gpio PWREN_MTIA_BLADE13_HSC_EN_N 0
set_gpio PWREN_MTIA_BLADE14_HSC_EN_N 0
set_gpio PWREN_MTIA_BLADE15_HSC_EN_N 0
+set_gpio PWREN_MTIA_BLADE16_HSC_EN_N 0
-set_gpio PWREN_NW_BLADE0_HSC_EN_N 0
set_gpio PWREN_NW_BLADE1_HSC_EN_N 0
set_gpio PWREN_NW_BLADE2_HSC_EN_N 0
set_gpio PWREN_NW_BLADE3_HSC_EN_N 0
set_gpio PWREN_NW_BLADE4_HSC_EN_N 0
set_gpio PWREN_NW_BLADE5_HSC_EN_N 0
+set_gpio PWREN_NW_BLADE6_HSC_EN_N 0
-set_gpio PWREN_FCB_TOP_0_EN_N 0
-set_gpio PWREN_FCB_TOP_1_EN_N 0
-set_gpio PWREN_FCB_MIDDLE_0_EN_N 0
-set_gpio PWREN_FCB_MIDDLE_1_EN_N 0
-set_gpio PWREN_FCB_BOTTOM_1_EN_N 0
-set_gpio PWREN_FCB_BOTTOM_0_EN_N 0
+set_gpio PWREN_SGPIO_FCB_1_EN_N 0
+set_gpio PWREN_SGPIO_FCB_2_EN_N 0
+set_gpio PWREN_SGPIO_FCB_3_EN_N 0
+set_gpio PWREN_SGPIO_FCB_4_EN_N 0
+set_gpio PWREN_SGPIO_FCB_5_EN_N 0
+set_gpio PWREN_SGPIO_FCB_6_EN_N 0
-set_gpio FM_CMM_AC_CYCLE_N 1
+set_gpio FM_BMC_RST_RTCRST_R 0
+set_gpio ERR_INJECT_CMM_PWR_FAIL_N 1
-set_gpio RST_I2CRST_FCB_BOTTOM_1_N 1
-set_gpio RST_I2CRST_FCB_BOTTOM_0_N 1
-set_gpio RST_I2CRST_FCB_MIDDLE_0_N 1
-set_gpio RST_I2CRST_FCB_MIDDLE_1_N 1
-set_gpio RST_I2CRST_FCB_TOP_0_N 1
-set_gpio RST_I2CRST_FCB_TOP_1_N 1
+set_gpio RST_I2CRST_FCB_1_N 1
+set_gpio RST_I2CRST_FCB_2_N 1
+set_gpio RST_I2CRST_FCB_3_N 1
+set_gpio RST_I2CRST_FCB_4_N 1
+set_gpio RST_I2CRST_FCB_5_N 1
+set_gpio RST_I2CRST_FCB_6_N 1
set_gpio FM_MDIO_SW_SEL 0
set_gpio FM_88E6393X_BIN_UPDATE_EN_N 1