| commit | a9ff2b33c004367b3dbded5d54d7a272ed76f68f | [log] [tgz] |
|---|---|---|
| author | Andrew Geissler <geissonator@yahoo.com> | Fri Oct 16 10:11:54 2020 -0500 |
| committer | Andrew Geissler <geissonator@yahoo.com> | Fri Oct 16 10:11:54 2020 -0500 |
| tree | a3c47ab3a1b1af411639ea6221a680f5f3cb490d | |
| parent | 9129b24a007278f4002886e4734bc217603f14ce [diff] [blame] |
reset meta-xilinx subtree on master HEAD(874b9cee5e) Change-Id: Ic0716e95ff53e7d63c54dc5fce6ee42fc99ed424
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/soc-versal.inc b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/soc-versal.inc index c32880b..d15f490 100644 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/soc-versal.inc +++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/soc-versal.inc
@@ -2,9 +2,11 @@ SOC_FAMILY ?= "versal" # Available SOC_VARIANT's for versal: -# virt +# "-prime" - Versal deafult Prime Devices +# "-ai-core" - Versal AI-core Devices +# "-premium" - Versal Premium Devices -SOC_VARIANT ?= "s80" +SOC_VARIANT ?= "-prime" require soc-tune-include.inc require xilinx-soc-family.inc