commit e8918846593aef4108d3256bb1d784fecc97153d
author Rohit PAI <ropai@nvidia.com> Tue Jun 10 09:46:33 2025 +0530
committer Rohit PAI <ropai@nvidia.com> Thu Jun 19 08:34:07 2025 +0530
tree 87e8fd4af6c76418e5aa6d7d6b4e31eded8d3136
parent b55847f2a3c973678eecded0ba6fbc6064ee82b4

WIP - Encode/decode APIs for NSM Inventory information

Added APIs to encode and decode NSM type 3 inventory information with
unit tests.

Change-Id: I9e5afbe356b64fd7ae4f7a2a65043f3eeffa3807
Signed-off-by: Rohit PAI <ropai@nvidia.com>

src/nvidia-gpu/NvidiaGpuMctpVdm.hpp

diff --git a/src/nvidia-gpu/NvidiaGpuMctpVdm.hpp b/src/nvidia-gpu/NvidiaGpuMctpVdm.hpp
index e378cfc..5bb335a 100644
--- a/src/nvidia-gpu/NvidiaGpuMctpVdm.hpp
+++ b/src/nvidia-gpu/NvidiaGpuMctpVdm.hpp
@@ -10,6 +10,9 @@
 
 #include <cstdint>
 #include <span>
+#include <string>
+#include <variant>
+#include <vector>
 
 namespace gpu
 {
@@ -33,6 +36,7 @@
     READ_THERMAL_PARAMETERS = 0x02,
     GET_CURRENT_POWER_DRAW = 0x03,
     GET_CURRENT_ENERGY_COUNTER = 0x06,
+    GET_INVENTORY_INFORMATION = 0x0C,
     GET_VOLTAGE = 0x0F,
 };
 
@@ -41,6 +45,49 @@
     DEVICE_GPU = 0
 };
 
+enum class InventoryPropertyId : uint8_t
+{
+    BOARD_PART_NUMBER = 0,
+    SERIAL_NUMBER = 1,
+    MARKETING_NAME = 2,
+    DEVICE_PART_NUMBER = 3,
+    FRU_PART_NUMBER = 4,
+    MEMORY_VENDOR = 5,
+    MEMORY_PART_NUMBER = 6,
+    MAX_MEMORY_CAPACITY = 7,
+    BUILD_DATE = 8,
+    FIRMWARE_VERSION = 9,
+    DEVICE_GUID = 10,
+    INFOROM_VERSION = 11,
+    PRODUCT_LENGTH = 12,
+    PRODUCT_WIDTH = 13,
+    PRODUCT_HEIGHT = 14,
+    RATED_DEVICE_POWER_LIMIT = 15,
+    MIN_DEVICE_POWER_LIMIT = 16,
+    MAX_DEVICE_POWER_LIMIT = 17,
+    MAX_MODULE_POWER_LIMIT = 18,
+    MIN_MODULE_POWER_LIMIT = 19,
+    RATED_MODULE_POWER_LIMIT = 20,
+    DEFAULT_BOOST_CLOCKS = 21,
+    DEFAULT_BASE_CLOCKS = 22,
+    DEFAULT_EDPP_SCALING = 23,
+    MIN_EDPP_SCALING = 24,
+    MAX_EDPP_SCALING = 25,
+    MIN_GRAPHICS_CLOCK = 26,
+    MAX_GRAPHICS_CLOCK = 27,
+    MIN_MEMORY_CLOCK = 28,
+    MAX_MEMORY_CLOCK = 29,
+    INFINIBAND_GUID = 30,
+    RACK_GUID = 31,
+    RACK_SLOT_NUMBER = 32,
+    COMPUTE_SLOT_INDEX = 33,
+    NODE_INDEX = 34,
+    GPU_NODE_ID = 35,
+    NVLINK_PEER_TYPE = 36,
+    FPGA_IMAGE_VERSION = 128,
+    FPGA_MCTP_BRIDGE_UUID = 129,
+};
+
 struct QueryDeviceIdentificationRequest
 {
     ocp::accelerator_management::CommonRequest hdr;
@@ -103,6 +150,21 @@
     ocp::accelerator_management::CommonResponse hdr;
     uint32_t voltage;
 } __attribute__((packed));
+struct GetInventoryInformationRequest
+{
+    ocp::accelerator_management::CommonRequest hdr;
+    uint8_t property_id;
+} __attribute__((packed));
+
+constexpr size_t MAX_INVENTORY_DATA_SIZE = 256;
+
+struct GetInventoryInformationResponse
+{
+    ocp::accelerator_management::CommonResponse hdr;
+    uint8_t data[MAX_INVENTORY_DATA_SIZE];
+} __attribute__((packed));
+
+using InventoryInfo = std::variant<std::string, std::vector<uint8_t>>;
 
 int packHeader(const ocp::accelerator_management::BindingPciVidInfo& hdr,
                ocp::accelerator_management::BindingPciVid& msg);
@@ -154,4 +216,12 @@
 int decodeGetVoltageResponse(std::span<const uint8_t> buf,
                              ocp::accelerator_management::CompletionCode& cc,
                              uint16_t& reasonCode, uint32_t& voltage);
+int encodeGetInventoryInformationRequest(uint8_t instanceId, uint8_t propertyId,
+                                         std::span<uint8_t> buf);
+
+int decodeGetInventoryInformationResponse(
+    std::span<const uint8_t> buf,
+    ocp::accelerator_management::CompletionCode& cc, uint16_t& reasonCode,
+    InventoryPropertyId propertyId, InventoryInfo& info);
+
 } // namespace gpu