configurations: yosemite4: revise sensors' name in fan table
The PLDM sensor name format was changed to prepend the terminus name in
the latest pldmd service.
Therefore, revised the sensors' name in fan control config of Sentinel
Dome and Wailua Falls board.
Tested:
Checked all the fan tables of Sentinel Dome and Wailua Falls are
correct.
Change-Id: I533c9902f5371b1f74e07f5d660379558b99013c
Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
diff --git a/configurations/yosemite4_sentineldome_t1.json b/configurations/yosemite4_sentineldome_t1.json
index e3acc30..85a68c7 100644
--- a/configurations/yosemite4_sentineldome_t1.json
+++ b/configurations/yosemite4_sentineldome_t1.json
@@ -10,18 +10,18 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "MB_DIMM_A_TEMP_C_5 $bus % 15 * 10",
- "MB_DIMM_B_TEMP_C_6 $bus % 15 * 10",
- "MB_DIMM_C_TEMP_C_7 $bus % 15 * 10",
- "MB_DIMM_D_TEMP_C_8 $bus % 15 * 10",
- "MB_DIMM_E_TEMP_C_9 $bus % 15 * 10",
- "MB_DIMM_G_TEMP_C_11 $bus % 15 * 10",
- "MB_DIMM_H_TEMP_C_12 $bus % 15 * 10",
- "MB_DIMM_I_TEMP_C_13 $bus % 15 * 10",
- "MB_DIMM_J_TEMP_C_14 $bus % 15 * 10",
- "MB_DIMM_K_TEMP_C_15 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_A_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_B_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_C_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_D_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_E_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_G_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_H_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_I_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_J_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_K_TEMP_C"
],
- "Name": "PID_MB_DIMM $bus % 15 * 10",
+ "Name": "PID_MB_DIMM_Slot $bus % 15",
"NegativeHysteresis": 2.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -45,9 +45,9 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "MB_CPU_TEMP_C_4 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_CPU_TEMP_C"
],
- "Name": "PID_MB_CPU $bus % 15 * 10",
+ "Name": "PID_MB_CPU_Slot $bus % 15",
"NegativeHysteresis": 3.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -71,9 +71,9 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "MB_SSD_BOOT_TEMP_C_17 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_SSD_BOOT_TEMP_C"
],
- "Name": "PID_MB_SSD_BOOT $bus % 15 * 10",
+ "Name": "PID_MB_SSD_BOOT_Slot $bus % 15",
"NegativeHysteresis": 2.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -97,13 +97,13 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "MB_VR_CPU0_TEMP_C_19 $bus % 15 * 10",
- "MB_VR_SOC_TEMP_C_20 $bus % 15 * 10",
- "MB_VR_CPU1_TEMP_C_21 $bus % 15 * 10",
- "MB_VR_PVDDIO_TEMP_C_22 $bus % 15 * 10",
- "MB_VR_PVDD11_TEMP_C_23 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_CPU0_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_SOC_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_CPU1_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_PVDDIO_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_PVDD11_TEMP_C"
],
- "Name": "PID_SD_VR $bus % 15 * 10",
+ "Name": "PID_MB_VR_Slot $bus % 15",
"NegativeHysteresis": 3.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -120,10 +120,10 @@
{
"Class": "temp",
"Inputs": [
- "MB_INLET_TEMP_C_1 $bus % 15 * 10",
- "MB_OUTLET_TEMP_C_2 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_INLET_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_OUTLET_TEMP_C"
],
- "Name": "Stepwise_MB_INLET_OUTLET_TEMP $bus % 15 * 10",
+ "Name": "Stepwise_MB_INLET_OUTLET_TEMP_Slot $bus % 15",
"NegativeHysteresis": 0,
"Output": [
20.0
@@ -140,9 +140,9 @@
{
"Class": "temp",
"Inputs": [
- "Calibrated_MB_FIO_TEMP_C_3 $bus % 15 * 10"
+ "Calibrated_Sentinel_Dome_Slot $bus % 15 MB_FIO_TEMP_C"
],
- "Name": "Stepwise_MB_FIO $bus % 15 * 10",
+ "Name": "Stepwise_MB_FIO_Slot $bus % 15",
"NegativeHysteresis": 2,
"Output": [
20.0,
@@ -197,18 +197,18 @@
{
"Class": "temp",
"Inputs": [
- "MB_DIMM_A_TEMP_C_5 $bus % 15 * 10",
- "MB_DIMM_B_TEMP_C_6 $bus % 15 * 10",
- "MB_DIMM_C_TEMP_C_7 $bus % 15 * 10",
- "MB_DIMM_D_TEMP_C_8 $bus % 15 * 10",
- "MB_DIMM_E_TEMP_C_9 $bus % 15 * 10",
- "MB_DIMM_G_TEMP_C_11 $bus % 15 * 10",
- "MB_DIMM_H_TEMP_C_12 $bus % 15 * 10",
- "MB_DIMM_I_TEMP_C_13 $bus % 15 * 10",
- "MB_DIMM_J_TEMP_C_14 $bus % 15 * 10",
- "MB_DIMM_K_TEMP_C_15 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_A_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_B_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_C_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_D_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_E_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_G_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_H_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_I_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_J_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_K_TEMP_C"
],
- "Name": "Stepwise_MB_DIMM $bus % 15 * 10",
+ "Name": "Stepwise_MB_DIMM_Slot $bus % 15",
"NegativeHysteresis": 2,
"Output": [
20.0,
@@ -235,9 +235,9 @@
{
"Class": "temp",
"Inputs": [
- "MB_CPU_TEMP_C_4 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_CPU_TEMP_C"
],
- "Name": "Stepwise_MB_CPU $bus % 15 * 10",
+ "Name": "Stepwise_MB_CPU_Slot $bus % 15",
"NegativeHysteresis": 3,
"Output": [
20.0,
@@ -270,9 +270,9 @@
{
"Class": "temp",
"Inputs": [
- "MB_SSD_BOOT_TEMP_C_17 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_SSD_BOOT_TEMP_C"
],
- "Name": "Stepwise_MB_SSD_BOOT $bus % 15 * 10",
+ "Name": "Stepwise_MB_SSD_BOOT_Slot $bus % 15",
"NegativeHysteresis": 2,
"Output": [
20.0,
@@ -299,13 +299,13 @@
{
"Class": "temp",
"Inputs": [
- "MB_VR_CPU0_TEMP_C_19 $bus % 15 * 10",
- "MB_VR_SOC_TEMP_C_20 $bus % 15 * 10",
- "MB_VR_CPU1_TEMP_C_21 $bus % 15 * 10",
- "MB_VR_PVDDIO_TEMP_C_22 $bus % 15 * 10",
- "MB_VR_PVDD11_TEMP_C_23 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_CPU0_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_SOC_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_CPU1_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_PVDDIO_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_PVDD11_TEMP_C"
],
- "Name": "Stepwise_SD_VR $bus % 15 * 10",
+ "Name": "Stepwise_MB_VR_Slot $bus % 15",
"NegativeHysteresis": 3,
"Output": [
20.0,
diff --git a/configurations/yosemite4_sentineldome_t1_retimer.json b/configurations/yosemite4_sentineldome_t1_retimer.json
index dc914e2..36e0f97 100644
--- a/configurations/yosemite4_sentineldome_t1_retimer.json
+++ b/configurations/yosemite4_sentineldome_t1_retimer.json
@@ -10,18 +10,18 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "MB_DIMM_A_TEMP_C_5 $bus % 15 * 10",
- "MB_DIMM_B_TEMP_C_6 $bus % 15 * 10",
- "MB_DIMM_C_TEMP_C_7 $bus % 15 * 10",
- "MB_DIMM_D_TEMP_C_8 $bus % 15 * 10",
- "MB_DIMM_E_TEMP_C_9 $bus % 15 * 10",
- "MB_DIMM_G_TEMP_C_11 $bus % 15 * 10",
- "MB_DIMM_H_TEMP_C_12 $bus % 15 * 10",
- "MB_DIMM_I_TEMP_C_13 $bus % 15 * 10",
- "MB_DIMM_J_TEMP_C_14 $bus % 15 * 10",
- "MB_DIMM_K_TEMP_C_15 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_A_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_B_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_C_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_D_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_E_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_G_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_H_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_I_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_J_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_K_TEMP_C"
],
- "Name": "PID_MB_DIMM $bus % 15 * 10",
+ "Name": "PID_MB_DIMM_Slot $bus % 15",
"NegativeHysteresis": 2.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -45,9 +45,9 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "MB_CPU_TEMP_C_4 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_CPU_TEMP_C"
],
- "Name": "PID_MB_CPU $bus % 15 * 10",
+ "Name": "PID_MB_CPU_Slot $bus % 15",
"NegativeHysteresis": 3.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -71,9 +71,9 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "MB_SSD_BOOT_TEMP_C_17 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_SSD_BOOT_TEMP_C"
],
- "Name": "PID_MB_SSD_BOOT $bus % 15 * 10",
+ "Name": "PID_MB_SSD_BOOT_Slot $bus % 15",
"NegativeHysteresis": 2.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -97,13 +97,13 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "MB_VR_CPU0_TEMP_C_19 $bus % 15 * 10",
- "MB_VR_SOC_TEMP_C_20 $bus % 15 * 10",
- "MB_VR_CPU1_TEMP_C_21 $bus % 15 * 10",
- "MB_VR_PVDDIO_TEMP_C_22 $bus % 15 * 10",
- "MB_VR_PVDD11_TEMP_C_23 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_CPU0_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_SOC_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_CPU1_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_PVDDIO_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_PVDD11_TEMP_C"
],
- "Name": "PID_SD_VR $bus % 15 * 10",
+ "Name": "PID_MB_VR_Slot $bus % 15",
"NegativeHysteresis": 3.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -120,10 +120,10 @@
{
"Class": "temp",
"Inputs": [
- "MB_INLET_TEMP_C_1 $bus % 15 * 10",
- "MB_OUTLET_TEMP_C_2 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_INLET_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_OUTLET_TEMP_C"
],
- "Name": "Stepwise_MB_INLET_OUTLET_TEMP $bus % 15 * 10",
+ "Name": "Stepwise_MB_INLET_OUTLET_TEMP_Slot $bus % 15",
"NegativeHysteresis": 0,
"Output": [
20.0
@@ -140,9 +140,9 @@
{
"Class": "temp",
"Inputs": [
- "MB_X8_RETIMER_TEMP_C_24 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_X8_RETIMER_TEMP_C"
],
- "Name": "Stepwise_MB_RETIMER_TEMP $bus % 15 * 10",
+ "Name": "Stepwise_MB_RETIMER_TEMP_Slot $bus % 15",
"NegativeHysteresis": 0,
"Output": [
20.0
@@ -159,9 +159,9 @@
{
"Class": "temp",
"Inputs": [
- "Calibrated_MB_FIO_TEMP_C_3 $bus % 15 * 10"
+ "Calibrated_Sentinel_Dome_Slot $bus % 15 MB_FIO_TEMP_C"
],
- "Name": "Stepwise_MB_FIO $bus % 15 * 10",
+ "Name": "Stepwise_MB_FIO_Slot $bus % 15",
"NegativeHysteresis": 2,
"Output": [
20.0,
@@ -216,18 +216,18 @@
{
"Class": "temp",
"Inputs": [
- "MB_DIMM_A_TEMP_C_5 $bus % 15 * 10",
- "MB_DIMM_B_TEMP_C_6 $bus % 15 * 10",
- "MB_DIMM_C_TEMP_C_7 $bus % 15 * 10",
- "MB_DIMM_D_TEMP_C_8 $bus % 15 * 10",
- "MB_DIMM_E_TEMP_C_9 $bus % 15 * 10",
- "MB_DIMM_G_TEMP_C_11 $bus % 15 * 10",
- "MB_DIMM_H_TEMP_C_12 $bus % 15 * 10",
- "MB_DIMM_I_TEMP_C_13 $bus % 15 * 10",
- "MB_DIMM_J_TEMP_C_14 $bus % 15 * 10",
- "MB_DIMM_K_TEMP_C_15 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_A_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_B_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_C_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_D_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_E_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_G_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_H_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_I_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_J_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_K_TEMP_C"
],
- "Name": "Stepwise_MB_DIMM $bus % 15 * 10",
+ "Name": "Stepwise_MB_DIMM_Slot $bus % 15",
"NegativeHysteresis": 2,
"Output": [
20.0,
@@ -254,9 +254,9 @@
{
"Class": "temp",
"Inputs": [
- "MB_CPU_TEMP_C_4 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_CPU_TEMP_C"
],
- "Name": "Stepwise_MB_CPU $bus % 15 * 10",
+ "Name": "Stepwise_MB_CPU_Slot $bus % 15",
"NegativeHysteresis": 3,
"Output": [
20.0,
@@ -289,9 +289,9 @@
{
"Class": "temp",
"Inputs": [
- "MB_SSD_BOOT_TEMP_C_17 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_SSD_BOOT_TEMP_C"
],
- "Name": "Stepwise_MB_SSD_BOOT $bus % 15 * 10",
+ "Name": "Stepwise_MB_SSD_BOOT_Slot $bus % 15",
"NegativeHysteresis": 2,
"Output": [
20.0,
@@ -318,13 +318,13 @@
{
"Class": "temp",
"Inputs": [
- "MB_VR_CPU0_TEMP_C_19 $bus % 15 * 10",
- "MB_VR_SOC_TEMP_C_20 $bus % 15 * 10",
- "MB_VR_CPU1_TEMP_C_21 $bus % 15 * 10",
- "MB_VR_PVDDIO_TEMP_C_22 $bus % 15 * 10",
- "MB_VR_PVDD11_TEMP_C_23 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_CPU0_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_SOC_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_CPU1_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_PVDDIO_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_PVDD11_TEMP_C"
],
- "Name": "Stepwise_SD_VR $bus % 15 * 10",
+ "Name": "Stepwise_MB_VR_Slot $bus % 15",
"NegativeHysteresis": 3,
"Output": [
20.0,
diff --git a/configurations/yosemite4_sentineldome_t2.json b/configurations/yosemite4_sentineldome_t2.json
index db0ca4d..8c5e034 100644
--- a/configurations/yosemite4_sentineldome_t2.json
+++ b/configurations/yosemite4_sentineldome_t2.json
@@ -10,20 +10,20 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "MB_DIMM_A_TEMP_C_5 $bus % 15 * 10",
- "MB_DIMM_B_TEMP_C_6 $bus % 15 * 10",
- "MB_DIMM_C_TEMP_C_7 $bus % 15 * 10",
- "MB_DIMM_D_TEMP_C_8 $bus % 15 * 10",
- "MB_DIMM_E_TEMP_C_9 $bus % 15 * 10",
- "MB_DIMM_F_TEMP_C_10 $bus % 15 * 10",
- "MB_DIMM_G_TEMP_C_11 $bus % 15 * 10",
- "MB_DIMM_H_TEMP_C_12 $bus % 15 * 10",
- "MB_DIMM_I_TEMP_C_13 $bus % 15 * 10",
- "MB_DIMM_J_TEMP_C_14 $bus % 15 * 10",
- "MB_DIMM_K_TEMP_C_15 $bus % 15 * 10",
- "MB_DIMM_L_TEMP_C_16 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_A_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_B_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_C_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_D_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_E_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_F_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_G_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_H_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_I_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_J_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_K_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_L_TEMP_C"
],
- "Name": "PID_MB_DIMM $bus % 15 * 10",
+ "Name": "PID_MB_DIMM_Slot $bus % 15",
"NegativeHysteresis": 2.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -47,9 +47,9 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "MB_CPU_TEMP_C_4 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_CPU_TEMP_C"
],
- "Name": "PID_MB_CPU $bus % 15 * 10",
+ "Name": "PID_MB_CPU_Slot $bus % 15",
"NegativeHysteresis": 3.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -73,9 +73,9 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "MB_SSD_BOOT_TEMP_C_17 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_SSD_BOOT_TEMP_C"
],
- "Name": "PID_MB_SSD_BOOT $bus % 15 * 10",
+ "Name": "PID_MB_SSD_BOOT_Slot $bus % 15",
"NegativeHysteresis": 2.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -99,9 +99,9 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "MB_SSD_DATA_TEMP_C_18 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_SSD_DATA_TEMP_C"
],
- "Name": "PID_MB_SSD_DATA $bus % 15 * 10",
+ "Name": "PID_MB_SSD_DATA_Slot $bus % 15",
"NegativeHysteresis": 2.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -125,13 +125,13 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "MB_VR_CPU0_TEMP_C_19 $bus % 15 * 10",
- "MB_VR_SOC_TEMP_C_20 $bus % 15 * 10",
- "MB_VR_CPU1_TEMP_C_21 $bus % 15 * 10",
- "MB_VR_PVDDIO_TEMP_C_22 $bus % 15 * 10",
- "MB_VR_PVDD11_TEMP_C_23 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_CPU0_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_SOC_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_CPU1_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_PVDDIO_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_PVDD11_TEMP_C"
],
- "Name": "PID_SD_VR $bus % 15 * 10",
+ "Name": "PID_MB_VR_Slot $bus % 15",
"NegativeHysteresis": 3.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -148,10 +148,10 @@
{
"Class": "temp",
"Inputs": [
- "MB_INLET_TEMP_C_1 $bus % 15 * 10",
- "MB_OUTLET_TEMP_C_2 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_INLET_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_OUTLET_TEMP_C"
],
- "Name": "Stepwise_MB_INLET_OUTLET_TEMP $bus % 15 * 10",
+ "Name": "Stepwise_MB_INLET_OUTLET_TEMP_Slot $bus % 15",
"NegativeHysteresis": 0,
"Output": [
20.0
@@ -168,9 +168,9 @@
{
"Class": "temp",
"Inputs": [
- "Calibrated_MB_FIO_TEMP_C_3 $bus % 15 * 10"
+ "Calibrated_Sentinel_Dome_Slot $bus % 15 MB_FIO_TEMP_C"
],
- "Name": "Stepwise_MB_FIO $bus % 15 * 10",
+ "Name": "Stepwise_MB_FIO_Slot $bus % 15",
"NegativeHysteresis": 2,
"Output": [
20.0,
@@ -225,20 +225,20 @@
{
"Class": "temp",
"Inputs": [
- "MB_DIMM_A_TEMP_C_5 $bus % 15 * 10",
- "MB_DIMM_B_TEMP_C_6 $bus % 15 * 10",
- "MB_DIMM_C_TEMP_C_7 $bus % 15 * 10",
- "MB_DIMM_D_TEMP_C_8 $bus % 15 * 10",
- "MB_DIMM_E_TEMP_C_9 $bus % 15 * 10",
- "MB_DIMM_F_TEMP_C_10 $bus % 15 * 10",
- "MB_DIMM_G_TEMP_C_11 $bus % 15 * 10",
- "MB_DIMM_H_TEMP_C_12 $bus % 15 * 10",
- "MB_DIMM_I_TEMP_C_13 $bus % 15 * 10",
- "MB_DIMM_J_TEMP_C_14 $bus % 15 * 10",
- "MB_DIMM_K_TEMP_C_15 $bus % 15 * 10",
- "MB_DIMM_L_TEMP_C_16 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_A_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_B_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_C_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_D_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_E_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_F_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_G_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_H_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_I_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_J_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_K_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_L_TEMP_C"
],
- "Name": "Stepwise_MB_DIMM $bus % 15 * 10",
+ "Name": "Stepwise_MB_DIMM_Slot $bus % 15",
"NegativeHysteresis": 2,
"Output": [
20.0,
@@ -265,9 +265,9 @@
{
"Class": "temp",
"Inputs": [
- "MB_CPU_TEMP_C_4 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_CPU_TEMP_C"
],
- "Name": "Stepwise_MB_CPU $bus % 15 * 10",
+ "Name": "Stepwise_MB_CPU_Slot $bus % 15",
"NegativeHysteresis": 3,
"Output": [
20.0,
@@ -300,9 +300,9 @@
{
"Class": "temp",
"Inputs": [
- "MB_SSD_BOOT_TEMP_C_17 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_SSD_BOOT_TEMP_C"
],
- "Name": "Stepwise_MB_SSD_BOOT $bus % 15 * 10",
+ "Name": "Stepwise_MB_SSD_BOOT_Slot $bus % 15",
"NegativeHysteresis": 2,
"Output": [
20.0,
@@ -329,9 +329,9 @@
{
"Class": "temp",
"Inputs": [
- "MB_SSD_DATA_TEMP_C_18 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_SSD_DATA_TEMP_C"
],
- "Name": "Stepwise_MB_SSD_DATA $bus % 15 * 10",
+ "Name": "Stepwise_MB_SSD_DATA_Slot $bus % 15",
"NegativeHysteresis": 2,
"Output": [
20.0,
@@ -358,13 +358,13 @@
{
"Class": "temp",
"Inputs": [
- "MB_VR_CPU0_TEMP_C_19 $bus % 15 * 10",
- "MB_VR_SOC_TEMP_C_20 $bus % 15 * 10",
- "MB_VR_CPU1_TEMP_C_21 $bus % 15 * 10",
- "MB_VR_PVDDIO_TEMP_C_22 $bus % 15 * 10",
- "MB_VR_PVDD11_TEMP_C_23 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_CPU0_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_SOC_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_CPU1_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_PVDDIO_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_PVDD11_TEMP_C"
],
- "Name": "Stepwise_SD_VR $bus % 15 * 10",
+ "Name": "Stepwise_MB_VR_Slot $bus % 15",
"NegativeHysteresis": 3,
"Output": [
20.0,
diff --git a/configurations/yosemite4_sentineldome_t2_retimer.json b/configurations/yosemite4_sentineldome_t2_retimer.json
index ca27594..c33bd4d 100644
--- a/configurations/yosemite4_sentineldome_t2_retimer.json
+++ b/configurations/yosemite4_sentineldome_t2_retimer.json
@@ -10,20 +10,20 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "MB_DIMM_A_TEMP_C_5 $bus % 15 * 10",
- "MB_DIMM_B_TEMP_C_6 $bus % 15 * 10",
- "MB_DIMM_C_TEMP_C_7 $bus % 15 * 10",
- "MB_DIMM_D_TEMP_C_8 $bus % 15 * 10",
- "MB_DIMM_E_TEMP_C_9 $bus % 15 * 10",
- "MB_DIMM_F_TEMP_C_10 $bus % 15 * 10",
- "MB_DIMM_G_TEMP_C_11 $bus % 15 * 10",
- "MB_DIMM_H_TEMP_C_12 $bus % 15 * 10",
- "MB_DIMM_I_TEMP_C_13 $bus % 15 * 10",
- "MB_DIMM_J_TEMP_C_14 $bus % 15 * 10",
- "MB_DIMM_K_TEMP_C_15 $bus % 15 * 10",
- "MB_DIMM_L_TEMP_C_16 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_A_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_B_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_C_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_D_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_E_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_F_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_G_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_H_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_I_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_J_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_K_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_L_TEMP_C"
],
- "Name": "PID_MB_DIMM $bus % 15 * 10",
+ "Name": "PID_MB_DIMM_Slot $bus % 15",
"NegativeHysteresis": 2.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -47,9 +47,9 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "MB_CPU_TEMP_C_4 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_CPU_TEMP_C"
],
- "Name": "PID_MB_CPU $bus % 15 * 10",
+ "Name": "PID_MB_CPU_Slot $bus % 15",
"NegativeHysteresis": 3.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -73,9 +73,9 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "MB_SSD_BOOT_TEMP_C_17 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_SSD_BOOT_TEMP_C"
],
- "Name": "PID_MB_SSD_BOOT $bus % 15 * 10",
+ "Name": "PID_MB_SSD_BOOT_Slot $bus % 15",
"NegativeHysteresis": 2.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -99,9 +99,9 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "MB_SSD_DATA_TEMP_C_18 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_SSD_DATA_TEMP_C"
],
- "Name": "PID_MB_SSD_DATA $bus % 15 * 10",
+ "Name": "PID_MB_SSD_DATA_Slot $bus % 15",
"NegativeHysteresis": 2.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -125,13 +125,13 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "MB_VR_CPU0_TEMP_C_19 $bus % 15 * 10",
- "MB_VR_SOC_TEMP_C_20 $bus % 15 * 10",
- "MB_VR_CPU1_TEMP_C_21 $bus % 15 * 10",
- "MB_VR_PVDDIO_TEMP_C_22 $bus % 15 * 10",
- "MB_VR_PVDD11_TEMP_C_23 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_CPU0_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_SOC_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_CPU1_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_PVDDIO_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_PVDD11_TEMP_C"
],
- "Name": "PID_SD_VR $bus % 15 * 10",
+ "Name": "PID_MB_VR_Slot $bus % 15",
"NegativeHysteresis": 3.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -148,10 +148,10 @@
{
"Class": "temp",
"Inputs": [
- "MB_INLET_TEMP_C_1 $bus % 15 * 10",
- "MB_OUTLET_TEMP_C_2 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_INLET_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_OUTLET_TEMP_C"
],
- "Name": "Stepwise_MB_INLET_OUTLET_TEMP $bus % 15 * 10",
+ "Name": "Stepwise_MB_INLET_OUTLET_TEMP_Slot $bus % 15",
"NegativeHysteresis": 0,
"Output": [
20.0
@@ -168,9 +168,9 @@
{
"Class": "temp",
"Inputs": [
- "MB_X8_RETIMER_TEMP_C_24 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_X8_RETIMER_TEMP_C"
],
- "Name": "Stepwise_MB_RETIMER_TEMP $bus % 15 * 10",
+ "Name": "Stepwise_MB_RETIMER_TEMP_Slot $bus % 15",
"NegativeHysteresis": 0,
"Output": [
20.0
@@ -187,9 +187,9 @@
{
"Class": "temp",
"Inputs": [
- "Calibrated_MB_FIO_TEMP_C_3 $bus % 15 * 10"
+ "Calibrated_Sentinel_Dome_Slot $bus % 15 MB_FIO_TEMP_C"
],
- "Name": "Stepwise_MB_FIO $bus % 15 * 10",
+ "Name": "Stepwise_MB_FIO_Slot $bus % 15",
"NegativeHysteresis": 2,
"Output": [
20.0,
@@ -244,20 +244,20 @@
{
"Class": "temp",
"Inputs": [
- "MB_DIMM_A_TEMP_C_5 $bus % 15 * 10",
- "MB_DIMM_B_TEMP_C_6 $bus % 15 * 10",
- "MB_DIMM_C_TEMP_C_7 $bus % 15 * 10",
- "MB_DIMM_D_TEMP_C_8 $bus % 15 * 10",
- "MB_DIMM_E_TEMP_C_9 $bus % 15 * 10",
- "MB_DIMM_F_TEMP_C_10 $bus % 15 * 10",
- "MB_DIMM_G_TEMP_C_11 $bus % 15 * 10",
- "MB_DIMM_H_TEMP_C_12 $bus % 15 * 10",
- "MB_DIMM_I_TEMP_C_13 $bus % 15 * 10",
- "MB_DIMM_J_TEMP_C_14 $bus % 15 * 10",
- "MB_DIMM_K_TEMP_C_15 $bus % 15 * 10",
- "MB_DIMM_L_TEMP_C_16 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_A_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_B_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_C_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_D_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_E_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_F_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_G_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_H_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_I_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_J_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_K_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_DIMM_L_TEMP_C"
],
- "Name": "Stepwise_MB_DIMM $bus % 15 * 10",
+ "Name": "Stepwise_MB_DIMM_Slot $bus % 15",
"NegativeHysteresis": 2,
"Output": [
20.0,
@@ -284,9 +284,9 @@
{
"Class": "temp",
"Inputs": [
- "MB_CPU_TEMP_C_4 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_CPU_TEMP_C"
],
- "Name": "Stepwise_MB_CPU $bus % 15 * 10",
+ "Name": "Stepwise_MB_CPU_Slot $bus % 15",
"NegativeHysteresis": 3,
"Output": [
20.0,
@@ -319,9 +319,9 @@
{
"Class": "temp",
"Inputs": [
- "MB_SSD_BOOT_TEMP_C_17 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_SSD_BOOT_TEMP_C"
],
- "Name": "Stepwise_MB_SSD_BOOT $bus % 15 * 10",
+ "Name": "Stepwise_MB_SSD_BOOT_Slot $bus % 15",
"NegativeHysteresis": 2,
"Output": [
20.0,
@@ -348,9 +348,9 @@
{
"Class": "temp",
"Inputs": [
- "MB_SSD_DATA_TEMP_C_18 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_SSD_DATA_TEMP_C"
],
- "Name": "Stepwise_MB_SSD_DATA $bus % 15 * 10",
+ "Name": "Stepwise_MB_SSD_DATA_Slot $bus % 15",
"NegativeHysteresis": 2,
"Output": [
20.0,
@@ -377,13 +377,13 @@
{
"Class": "temp",
"Inputs": [
- "MB_VR_CPU0_TEMP_C_19 $bus % 15 * 10",
- "MB_VR_SOC_TEMP_C_20 $bus % 15 * 10",
- "MB_VR_CPU1_TEMP_C_21 $bus % 15 * 10",
- "MB_VR_PVDDIO_TEMP_C_22 $bus % 15 * 10",
- "MB_VR_PVDD11_TEMP_C_23 $bus % 15 * 10"
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_CPU0_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_SOC_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_CPU1_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_PVDDIO_TEMP_C",
+ "Sentinel_Dome_Slot $bus % 15 MB_VR_PVDD11_TEMP_C"
],
- "Name": "Stepwise_SD_VR $bus % 15 * 10",
+ "Name": "Stepwise_MB_VR_Slot $bus % 15",
"NegativeHysteresis": 3,
"Output": [
20.0,
diff --git a/configurations/yosemite4_wailuafalls.json b/configurations/yosemite4_wailuafalls.json
index 24eafa1..dd722a2 100644
--- a/configurations/yosemite4_wailuafalls.json
+++ b/configurations/yosemite4_wailuafalls.json
@@ -10,16 +10,16 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "WF_ASIC1_DIMM_A_TEMP_C_12 $bus % 15 * 10 + 2",
- "WF_ASIC1_DIMM_B_TEMP_C_13 $bus % 15 * 10 + 2",
- "WF_ASIC1_DIMM_C_TEMP_C_14 $bus % 15 * 10 + 2",
- "WF_ASIC1_DIMM_D_TEMP_C_15 $bus % 15 * 10 + 2",
- "WF_ASIC2_DIMM_A_TEMP_C_16 $bus % 15 * 10 + 2",
- "WF_ASIC2_DIMM_B_TEMP_C_17 $bus % 15 * 10 + 2",
- "WF_ASIC2_DIMM_C_TEMP_C_18 $bus % 15 * 10 + 2",
- "WF_ASIC2_DIMM_D_TEMP_C_19 $bus % 15 * 10 + 2"
+ "Wailua_Falls_Slot $bus % 15 WF_ASIC1_DIMM_A_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_ASIC1_DIMM_B_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_ASIC1_DIMM_C_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_ASIC1_DIMM_D_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_ASIC2_DIMM_A_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_ASIC2_DIMM_B_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_ASIC2_DIMM_C_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_ASIC2_DIMM_D_TEMP_C"
],
- "Name": "PID_WF_DIMM $bus % 15 * 10 + 2",
+ "Name": "PID_WF_DIMM_Slot $bus % 15",
"NegativeHysteresis": 2.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -43,9 +43,9 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "WF_E1S_TEMP_C_20 $bus % 15 * 10 + 2"
+ "Wailua_Falls_Slot $bus % 15 WF_E1S_TEMP_C"
],
- "Name": "PID_WF_E1S $bus % 15 * 10 + 2",
+ "Name": "PID_WF_E1S_Slot $bus % 15",
"NegativeHysteresis": 2.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -69,10 +69,10 @@
"ILimitMax": 100,
"ILimitMin": -50,
"Inputs": [
- "WF_CXL1_CNTR_TEMP_C_2 $bus % 15 * 10 + 2",
- "WF_CXL2_CNTR_TEMP_C_3 $bus % 15 * 10 + 2"
+ "Wailua_Falls_Slot $bus % 15 WF_CXL1_CNTR_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_CXL2_CNTR_TEMP_C"
],
- "Name": "PID_WF_CXL $bus % 15 * 10 + 2",
+ "Name": "PID_WF_CXL_Slot $bus % 15",
"NegativeHysteresis": 3.0,
"OutLimitMax": 100,
"OutLimitMin": 0,
@@ -89,17 +89,17 @@
{
"Class": "temp",
"Inputs": [
- "WF_1OU_BOARD_INLET_TEMP_C_1 $bus % 15 * 10 + 2",
- "WF_VR_P0V8_ASIC1_TEMP_C_4 $bus % 15 * 10 + 2",
- "WF_VR_PVDDQ_CD_ASIC1_TEMP_C_5 $bus % 15 * 10 + 2",
- "WF_VR_P0V85_ASIC1_TEMP_C_6 $bus % 15 * 10 + 2",
- "WF_VR_PVDDQ_AB_ASIC1_TEMP_C_7 $bus % 15 * 10 + 2",
- "WF_VR_P0V8_ASIC2_TEMP_C_8 $bus % 15 * 10 + 2",
- "WF_VR_PVDDQ_CD_ASIC2_TEMP_C_9 $bus % 15 * 10 + 2",
- "WF_VR_P0V85_ASIC2_TEMP_C_10 $bus % 15 * 10 + 2",
- "WF_VR_PVDDQ_AB_ASIC2_TEMP_C_11 $bus % 15 * 10 + 2"
+ "Wailua_Falls_Slot $bus % 15 WF_1OU_BOARD_INLET_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_VR_P0V8_ASIC1_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_VR_PVDDQ_CD_ASIC1_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_VR_P0V85_ASIC1_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_VR_PVDDQ_AB_ASIC1_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_VR_P0V8_ASIC2_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_VR_PVDDQ_CD_ASIC2_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_VR_P0V85_ASIC2_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_VR_PVDDQ_AB_ASIC2_TEMP_C"
],
- "Name": "WF_Non_Critical_Sensors $bus % 15 * 10 + 2",
+ "Name": "Stepwise_WF_Non_Critical_Sensors_Slot $bus % 15",
"NegativeHysteresis": 0,
"Output": [
20.0
@@ -116,16 +116,16 @@
{
"Class": "temp",
"Inputs": [
- "WF_ASIC1_DIMM_A_TEMP_C_12 $bus % 15 * 10 + 2",
- "WF_ASIC1_DIMM_B_TEMP_C_13 $bus % 15 * 10 + 2",
- "WF_ASIC1_DIMM_C_TEMP_C_14 $bus % 15 * 10 + 2",
- "WF_ASIC1_DIMM_D_TEMP_C_15 $bus % 15 * 10 + 2",
- "WF_ASIC2_DIMM_A_TEMP_C_16 $bus % 15 * 10 + 2",
- "WF_ASIC2_DIMM_B_TEMP_C_17 $bus % 15 * 10 + 2",
- "WF_ASIC2_DIMM_C_TEMP_C_18 $bus % 15 * 10 + 2",
- "WF_ASIC2_DIMM_D_TEMP_C_19 $bus % 15 * 10 + 2"
+ "Wailua_Falls_Slot $bus % 15 WF_ASIC1_DIMM_A_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_ASIC1_DIMM_B_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_ASIC1_DIMM_C_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_ASIC1_DIMM_D_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_ASIC2_DIMM_A_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_ASIC2_DIMM_B_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_ASIC2_DIMM_C_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_ASIC2_DIMM_D_TEMP_C"
],
- "Name": "Stepwise_WF_DIMM $bus % 15 * 10 + 2",
+ "Name": "Stepwise_WF_DIMM_Slot $bus % 15",
"NegativeHysteresis": 2,
"Output": [
20.0,
@@ -152,9 +152,9 @@
{
"Class": "temp",
"Inputs": [
- "WF_E1S_TEMP_C_20 $bus % 15 * 10 + 2"
+ "Wailua_Falls_Slot $bus % 15 WF_E1S_TEMP_C"
],
- "Name": "Stepwise_WF_E1S $bus % 15 * 10 + 2",
+ "Name": "Stepwise_WF_E1S_Slot $bus % 15",
"NegativeHysteresis": 2,
"Output": [
20.0,
@@ -181,10 +181,10 @@
{
"Class": "temp",
"Inputs": [
- "WF_CXL1_CNTR_TEMP_C_2 $bus % 15 * 10 + 2",
- "WF_CXL2_CNTR_TEMP_C_3 $bus % 15 * 10 + 2"
+ "Wailua_Falls_Slot $bus % 15 WF_CXL1_CNTR_TEMP_C",
+ "Wailua_Falls_Slot $bus % 15 WF_CXL2_CNTR_TEMP_C"
],
- "Name": "Stepwise_WF_CXL $bus % 15 * 10 + 2",
+ "Name": "Stepwise_WF_CXL_Slot $bus % 15",
"NegativeHysteresis": 2,
"Output": [
20.0,