Move ERR0 and ERR1 monitor to the new architecture
Add an error monitor for CPU_ERR0 and CPU_ERR1 that polls to check
if it is asserted through the timeout and logs the event. If it is
ever not asserted, it will wait for an interrupt to start polling
again.
Change-Id: I16eb5500f4c08226b7e4e879eb7732caa5262db1
Signed-off-by: Jason M. Bills <jason.m.bills@intel.com>
diff --git a/include/host_error_monitor.hpp b/include/host_error_monitor.hpp
index eee1fab..90a946e 100644
--- a/include/host_error_monitor.hpp
+++ b/include/host_error_monitor.hpp
@@ -92,4 +92,19 @@
"com.intel.crashdump.Stored", "GenerateStoredLog", triggerType);
}
+static inline bool peciError(EPECIStatus peciStatus, uint8_t cc)
+{
+ return (
+ peciStatus != PECI_CC_SUCCESS ||
+ (cc != PECI_DEV_CC_SUCCESS && cc != PECI_DEV_CC_FATAL_MCA_DETECTED));
+}
+
+static void printPECIError(const std::string& reg, const size_t addr,
+ const EPECIStatus peciStatus, const size_t cc)
+{
+ std::cerr << "Failed to read " << reg << " on CPU address " << addr
+ << ". Error: " << peciStatus << ": cc: 0x" << std::hex << cc
+ << "\n";
+}
+
} // namespace host_error_monitor