commit c90570ab1ad57ac824edf7b5d0f8a89afbcf0c09
author Jason M. Bills <jason.m.bills@intel.com> Tue Sep 22 15:24:58 2020 -0700
committer Jason M. Bills <jason.m.bills@intel.com> Wed Sep 23 16:44:25 2020 -0700
tree af63bf3715835a758c8552e1cd05dd596a7240f7
parent 8064f8b59b272fd1bdcbf8bf94e1fbd58866e034

Correct model-specific error code checks for IERR logging

The model-specific error code holds a byte value that is a
specific code.  The current logic incorrectly checks if bits
are set rather than checking the full code.

This changes the code to extract the error code byte and compare
the full value with the expected error codes.

Tested:
Injected an IERR and confirmed that the model-specific error code
is correctly checked.

Change-Id: I671109aecf1ae5bbf707adaefaf47e95f09ca248
Signed-off-by: Jason M. Bills <jason.m.bills@intel.com>

src/host_error_monitor.cpp

diff --git a/src/host_error_monitor.cpp b/src/host_error_monitor.cpp
index b4a8c72..d52a5dc 100644
--- a/src/host_error_monitor.cpp
+++ b/src/host_error_monitor.cpp
@@ -559,9 +559,8 @@
                     // MCA_SVID_VCCIN_VR_ICC_MAX_FAILURE (0x40),
                     // MCA_SVID_VCCIN_VR_VOUT_FAILURE (0x42), or
                     // MCA_SVID_CPU_VR_CAPABILITY_ERROR (0x43)
-                    if ((mc4Status & (0x40 << 24)) ||
-                        (mc4Status & (0x42 << 24)) ||
-                        (mc4Status & (0x43 << 24)))
+                    uint64_t msec = (mc4Status >> 24) & 0xFF;
+                    if (msec == 0x40 || msec == 0x42 || msec == 0x43)
                     {
                         cpuIERRLog(cpu, "CPU/VR Mismatch");
                         continue;
@@ -611,8 +610,7 @@
                     // MCA_FIVR_CATAS_OVERCUR_FAULT (0x52), then log it as an
                     // uncore FIVR fault
                     if (!coreFIVRErrLog && !uncoreFIVRErrLog &&
-                        ((mc4Status & (0x51 << 24)) ||
-                         (mc4Status & (0x52 << 24))))
+                        (msec == 0x51 || msec == 0x52))
                     {
                         cpuIERRLog(cpu, "Uncore FIVR Fault");
                         continue;
@@ -648,14 +646,12 @@
                         printPECIError("IA32_MC4_STATUS", addr, peciStatus, cc);
                         continue;
                     }
-                    // TODO: Update MSEC/MSCOD_31_24 check
                     // Check MSEC bits 31:24 for
                     // MCA_SVID_VCCIN_VR_ICC_MAX_FAILURE (0x40),
                     // MCA_SVID_VCCIN_VR_VOUT_FAILURE (0x42), or
                     // MCA_SVID_CPU_VR_CAPABILITY_ERROR (0x43)
-                    if ((mc4Status & (0x40 << 24)) ||
-                        (mc4Status & (0x42 << 24)) ||
-                        (mc4Status & (0x43 << 24)))
+                    uint64_t msec = (mc4Status >> 24) & 0xFF;
+                    if (msec == 0x40 || msec == 0x42 || msec == 0x43)
                     {
                         cpuIERRLog(cpu, "CPU/VR Mismatch");
                         continue;
@@ -716,9 +712,7 @@
                     // MCA_FIVR_CATAS_OVERCUR_FAULT (0x52), then log it as an
                     // uncore FIVR fault
                     if (!coreFIVRErrLog0 && !coreFIVRErrLog1 &&
-                        !uncoreFIVRErrLog &&
-                        ((mc4Status & (0x51 << 24)) ||
-                         (mc4Status & (0x52 << 24))))
+                        !uncoreFIVRErrLog && (msec == 0x51 || msec == 0x52))
                     {
                         cpuIERRLog(cpu, "Uncore FIVR Fault");
                         continue;