diff --git a/include/oemcommands.hpp b/include/oemcommands.hpp
index 777dba4..c664a48 100644
--- a/include/oemcommands.hpp
+++ b/include/oemcommands.hpp
@@ -81,6 +81,7 @@
 namespace platform
 {
 static constexpr Cmd cmdCfgHostSerialPortSpeed = 0x90;
+static constexpr Cmd cmdClearCMOS = 0x91;
 } // namespace platform
 
 namespace app
diff --git a/src/manufacturingcommands.cpp b/src/manufacturingcommands.cpp
index 8b8adab..eefdc76 100644
--- a/src/manufacturingcommands.cpp
+++ b/src/manufacturingcommands.cpp
@@ -784,6 +784,26 @@
 
     return ipmi::responseSuccess(readBuf);
 }
+
+ipmi::RspType<> clearCMOS()
+{
+    // There is an i2c device on bus 4, the slave address is 0x70. Based on the
+    // spec, writing 0x1 to address 0x60 on this device, will trigger the clear
+    // CMOS action.
+    constexpr uint8_t slaveAddr = 0x70;
+    std::string i2cBus = "/dev/i2c-4";
+    std::vector<uint8_t> writeData = {0x60, 0x1};
+    std::vector<uint8_t> readBuf(0);
+
+    // TODO Needs to enhance the below security checking
+    if (mtm.getAccessLvl() < MtmLvl::mtmAvailable)
+    {
+        return ipmi::responseInsufficientPrivilege();
+    }
+
+    ipmi::Cc retI2C = ipmi::i2cWriteRead(i2cBus, slaveAddr, writeData, readBuf);
+    return ipmi::response(retI2C);
+}
 } // namespace ipmi
 
 void register_mtm_commands() __attribute__((constructor));
@@ -815,6 +835,10 @@
                           ipmi::Privilege::Admin,
                           ipmi::appSlotI2CMasterWriteRead);
 
+    ipmi::registerHandler(ipmi::prioOemBase, ipmi::intel::netFnPlatform,
+                          ipmi::intel::platform::cmdClearCMOS,
+                          ipmi::Privilege::Admin, ipmi::clearCMOS);
+
     ipmi::registerFilter(ipmi::prioOemBase,
                          [](ipmi::message::Request::ptr request) {
                              return ipmi::mfgFilterMessage(request);