diff --git a/include/bridgingcommands.hpp b/include/bridgingcommands.hpp
index b771bfd..73b4486 100644
--- a/include/bridgingcommands.hpp
+++ b/include/bridgingcommands.hpp
@@ -28,7 +28,7 @@
  */
 constexpr uint8_t ipmbLunMask = 0x03;
 constexpr uint8_t ipmbSeqMask = 0x3F;
-constexpr uint8_t ipmbMeSlaveAddress = 0x2C;
+constexpr uint8_t ipmbMeTargetAddress = 0x2C;
 constexpr uint8_t ipmbMeChannelNum = 1;
 
 /**
diff --git a/include/multinodecommands.hpp b/include/multinodecommands.hpp
index b704912..ae8f3ef 100644
--- a/include/multinodecommands.hpp
+++ b/include/multinodecommands.hpp
@@ -24,7 +24,7 @@
 enum class NodeRole : uint8_t
 {
     single,
-    master,
-    slave,
+    controller,
+    target,
     arbitrating
 };
diff --git a/include/oemcommands.hpp b/include/oemcommands.hpp
index 0047517..4f8166f 100644
--- a/include/oemcommands.hpp
+++ b/include/oemcommands.hpp
@@ -43,7 +43,7 @@
 static constexpr Cmd cmdDisableBMCSystemReset = 0x42;
 static constexpr Cmd cmdGetBMCResetDisables = 0x43;
 static constexpr Cmd cmdSendEmbeddedFWUpdStatus = 0x44;
-static constexpr Cmd cmdSlotI2CMasterWriteRead = 0x52;
+static constexpr Cmd cmdSlotI2CControllerWriteRead = 0x52;
 static constexpr Cmd cmdSetPowerRestoreDelay = 0x54;
 static constexpr Cmd cmdGetPowerRestoreDelay = 0x55;
 static constexpr Cmd cmdSetFaultIndication = 0x57;
diff --git a/include/storagecommands.hpp b/include/storagecommands.hpp
index 42cc85b..7fb5ce7 100644
--- a/include/storagecommands.hpp
+++ b/include/storagecommands.hpp
@@ -99,7 +99,7 @@
 struct Type12Record
 {
     get_sdr::SensorDataRecordHeader header;
-    uint8_t slaveAddress;
+    uint8_t targetAddress;
     uint8_t channelNumber;
     uint8_t powerStateNotification;
     uint8_t deviceCapabilities;
@@ -116,7 +116,7 @@
                  uint8_t pwrStateNotification, uint8_t capabilities,
                  uint8_t eid, uint8_t entityInst, uint8_t mfrDefined,
                  const std::string& sensorname) :
-        slaveAddress(address),
+        targetAddress(address),
         channelNumber(chNumber), powerStateNotification(pwrStateNotification),
         deviceCapabilities(capabilities), reserved{}, entityID(eid),
         entityInstance(entityInst), oem(mfrDefined)
@@ -143,7 +143,7 @@
     uint8_t oemID2;
     uint8_t subType;
     uint8_t version;
-    uint8_t slaveAddress;
+    uint8_t targetAddress;
     uint8_t channelNumber;
     uint8_t healthEventSensor;
     uint8_t exceptionEventSensor;
diff --git a/ipmi-allowlist.conf b/ipmi-allowlist.conf
index 5a3f154..792e38f 100644
--- a/ipmi-allowlist.conf
+++ b/ipmi-allowlist.conf
@@ -79,7 +79,7 @@
 0x06:0x4e:0xff7f   //<App>:<Get Channel Payload Support>
 0x06:0x4f:0xff7f   //<App>:<Get Channel Payload Version>
 0x06:0x50:0xff7f   //<App>:<Get Channel OEM Payload Info>
-0x06:0x52:0x7f7f   //<App>:<Master Write Read I2C>
+0x06:0x52:0x7f7f   //<App>:<Controller Write Read I2C>
 0x06:0x54:0xff7f   //<App>:<Get Channel Cipher Suites>
 0x06:0x55:0xff7f   //<App>:<Suspend Payload Encryption>
 0x06:0x56:0xff7f   //<App>:<Set Channel Security Keys>
@@ -192,8 +192,8 @@
 0x30:0x19:0xff7f   //<Intel General Application>:<Read LAN Channel Port Value>
 0x30:0x1a:0xff7f   //<Intel General Application>:<Get NIC Info>
 0x30:0x1b:0xff7f   //<Intel General Application>:<Get LAN Available>
-0x30:0x1c:0x7f7f   //<Intel General Application>:<Set Master MAC>
-0x30:0x1d:0xff7f   //<Intel General Application>:<Get Master MAC>
+0x30:0x1c:0x7f7f   //<Intel General Application>:<Set Controller MAC>
+0x30:0x1d:0xff7f   //<Intel General Application>:<Get Controller MAC>
 0x30:0x1f:0xff7f   //<Intel General Application>:<Get Secure Mode>
 0x30:0x20:0xff7f   //<Intel General Application>:<OEM Get SEL info>
 0x30:0x21:0xff7f   //<Intel General Application>:<OEM Get SEL Allocation Info>
@@ -340,9 +340,9 @@
 0x3e:0x44:0xff7f   //<Intel Managed Data Region>:<Exit Platform Debug Log file transfer mode>
 0x3e:0x47:0x7f7f   //<Intel Managed Data Region>:<Get/Set BMC Application Fault Management Config>
 0x3e:0x48:0x7f7f   //<Intel Managed Data Region>:<Get/Set BMC Boot Fault Management Config>
-0x3e:0x50:0xff7f   //<Intel Managed Data Region>:<Node IPMB slave address>
+0x3e:0x50:0xff7f   //<Intel Managed Data Region>:<Node IPMB target address>
 0x3e:0x51:0xff7f   //<Intel Managed Data Region>:<Slot IPMB>
-0x3e:0x52:0xff7f   //<Intel Managed Data Region>:<Slot I2C Master Write Read>
+0x3e:0x52:0xff7f   //<Intel Managed Data Region>:<Slot I2C Controller Write Read>
 0x3e:0x70:0x7f7f   //<Intel Managed Data Region>:<SDR Configuration File control>
 0x3e:0x71:0x7f7f   //<Intel Managed Data Region>:<SDR Configuration File Write>
 0x3e:0x72:0x7f7f   //<Intel Managed Data Region>:<SDR Configuration File Read>
diff --git a/src/allowlist-filter.cpp b/src/allowlist-filter.cpp
index fa9eb26..aed090c 100644
--- a/src/allowlist-filter.cpp
+++ b/src/allowlist-filter.cpp
@@ -449,7 +449,7 @@
             Allowlisted = false;
             break;
         }
-        default: // for Allowlist and blacklist
+        default: // for Allowlist and Blocklist
             return ipmi::ccInsufficientPrivilege;
     }
 
diff --git a/src/bridgingcommands.cpp b/src/bridgingcommands.cpp
index f6fc02f..405db62 100644
--- a/src/bridgingcommands.cpp
+++ b/src/bridgingcommands.cpp
@@ -213,14 +213,14 @@
     constexpr uint8_t cmdMeOemReadMemSmbus = 0x47;
     constexpr uint8_t cmdMeOemWriteMemSmbus = 0x48;
     constexpr uint8_t cmdMeOemSlotIpmb = 0x51;
-    constexpr uint8_t cmdMeOemSlotI2cMasterWriteRead = 0x52;
+    constexpr uint8_t cmdMeOemSlotI2cControllerWriteRead = 0x52;
     constexpr uint8_t cmdMeOemSendRawPmbus = 0xD9;
     constexpr uint8_t cmdMeOemUnlockMeRegion = 0xE7;
     constexpr uint8_t cmdMeOemAggSendRawPmbus = 0xEC;
 
     switch (makeCmdKey(netFn, cmd))
     {
-        // Restrict ME Master write command
+        // Restrict ME Controller write command
         case makeCmdKey(ipmi::netFnApp, ipmi::app::cmdMasterWriteRead):
         // Restrict ME OEM commands
         case makeCmdKey(netFnMeOEM, cmdMeOemSendRawPeci):
@@ -230,7 +230,7 @@
         case makeCmdKey(netFnMeOEM, cmdMeOemReadMemSmbus):
         case makeCmdKey(netFnMeOEM, cmdMeOemWriteMemSmbus):
         case makeCmdKey(netFnMeOEMGeneral, cmdMeOemSlotIpmb):
-        case makeCmdKey(netFnMeOEMGeneral, cmdMeOemSlotI2cMasterWriteRead):
+        case makeCmdKey(netFnMeOEMGeneral, cmdMeOemSlotI2cControllerWriteRead):
         case makeCmdKey(netFnMeOEM, cmdMeOemSendRawPmbus):
         case makeCmdKey(netFnMeOEM, cmdMeOemUnlockMeRegion):
         case makeCmdKey(netFnMeOEM, cmdMeOemAggSendRawPmbus):
@@ -264,7 +264,7 @@
     auto sendMsgReqData = reinterpret_cast<const ipmbHeader*>(msgData.data());
 
     // allow bridging to ME only
-    if (sendMsgReqData->Header.Req.address != ipmbMeSlaveAddress)
+    if (sendMsgReqData->Header.Req.address != ipmbMeTargetAddress)
     {
         phosphor::logging::log<phosphor::logging::level::INFO>(
             "handleIpmbChannel, IPMB address invalid");
diff --git a/src/manufacturingcommands.cpp b/src/manufacturingcommands.cpp
index 6376eee..644a2e2 100644
--- a/src/manufacturingcommands.cpp
+++ b/src/manufacturingcommands.cpp
@@ -840,7 +840,7 @@
     // Restricted commands, must be executed only in Manufacturing mode
     switch (makeCmdKey(request->ctx->netFn, request->ctx->cmd))
     {
-        // i2c master write read command needs additional checking
+        // i2c controller write read command needs additional checking
         case makeCmdKey(ipmi::netFnApp, ipmi::app::cmdMasterWriteRead):
             if (request->payload.size() > 4)
             {
@@ -1163,7 +1163,7 @@
     return ipmi::responseSuccess(validData, ethData);
 }
 
-/** @brief implements slot master write read IPMI command which can be used
+/** @brief implements slot controller write read IPMI command which can be used
  * for low-level I2C/SMBus write, read or write-read access for PCIE slots
  * @param reserved - skip 3 bit
  * @param muxType - mux type
@@ -1171,16 +1171,16 @@
  * @param bbSlotNum - baseboard slot number
  * @param riserSlotNum - riser slot number
  * @param reserved2 - skip 2 bit
- * @param slaveAddr - slave address
+ * @param targetAddr - target address
  * @param readCount - number of bytes to be read
  * @param writeData - data to be written
  *
  * @returns IPMI completion code plus response data
  */
 
-ipmi::RspType<std::vector<uint8_t>> appSlotI2CMasterWriteRead(
+ipmi::RspType<std::vector<uint8_t>> appSlotI2CControllerWriteRead(
     uint3_t reserved, uint3_t muxType, uint2_t addressType, uint3_t bbSlotNum,
-    uint3_t riserSlotNum, uint2_t reserved2, uint8_t slaveAddr,
+    uint3_t riserSlotNum, uint2_t reserved2, uint8_t targetAddr,
     uint8_t readCount, std::vector<uint8_t> writeData)
 {
     if (reserved || reserved2)
@@ -1226,7 +1226,7 @@
         }
         else
         {
-            lg2::error("Master write read command: Cannot get BusID");
+            lg2::error("Controller write read command: Cannot get BusID");
             return ipmi::responseInvalidFieldRequest();
         }
     }
@@ -1238,7 +1238,7 @@
     }
     else
     {
-        lg2::error("Master write read command: invalid request");
+        lg2::error("Controller write read command: invalid request");
         return ipmi::responseInvalidFieldRequest();
     }
 
@@ -1254,19 +1254,20 @@
 
     if (readCount > slotI2CMaxReadSize)
     {
-        lg2::error("Master write read command: Read count exceeds limit");
+        lg2::error("Controller write read command: Read count exceeds limit");
         return ipmi::responseParmOutOfRange();
     }
 
     if (!readCount && !writeCount)
     {
-        lg2::error("Master write read command: Read & write count are 0");
+        lg2::error("Controller write read command: Read & write count are 0");
         return ipmi::responseInvalidFieldRequest();
     }
 
     std::vector<uint8_t> readBuf(readCount);
 
-    ipmi::Cc retI2C = ipmi::i2cWriteRead(i2cBus, slaveAddr, writeData, readBuf);
+    ipmi::Cc retI2C =
+        ipmi::i2cWriteRead(i2cBus, targetAddr, writeData, readBuf);
     if (retI2C != ipmi::ccSuccess)
     {
         return ipmi::response(retI2C);
@@ -1277,15 +1278,16 @@
 
 ipmi::RspType<> clearCMOS()
 {
-    // There is an i2c device on bus 4, the slave address is 0x38. Based on
+    // There is an i2c device on bus 4, the target address is 0x38. Based on
     // the spec, writing 0x1 to address 0x61 on this device, will trigger
     // the clear CMOS action.
-    constexpr uint8_t slaveAddr = 0x38;
+    constexpr uint8_t targetAddr = 0x38;
     std::string i2cBus = "/dev/i2c-4";
     std::vector<uint8_t> writeData = {0x61, 0x1};
     std::vector<uint8_t> readBuf(0);
 
-    ipmi::Cc retI2C = ipmi::i2cWriteRead(i2cBus, slaveAddr, writeData, readBuf);
+    ipmi::Cc retI2C =
+        ipmi::i2cWriteRead(i2cBus, targetAddr, writeData, readBuf);
     return ipmi::response(retI2C);
 }
 
@@ -1522,9 +1524,9 @@
                           ipmi::Privilege::Admin, ipmi::mtmBMCFeatureControl);
 
     ipmi::registerHandler(ipmi::prioOemBase, ipmi::intel::netFnApp,
-                          ipmi::intel::general::cmdSlotI2CMasterWriteRead,
+                          ipmi::intel::general::cmdSlotI2CControllerWriteRead,
                           ipmi::Privilege::Admin,
-                          ipmi::appSlotI2CMasterWriteRead);
+                          ipmi::appSlotI2CControllerWriteRead);
 
     ipmi::registerHandler(ipmi::prioOemBase, ipmi::intel::netFnPlatform,
                           ipmi::intel::platform::cmdClearCMOS,
diff --git a/src/multinodecommands.cpp b/src/multinodecommands.cpp
index 20a1841..d6712b3 100644
--- a/src/multinodecommands.cpp
+++ b/src/multinodecommands.cpp
@@ -62,9 +62,9 @@
         if (valueStr == "single")
             value = static_cast<uint8_t>(NodeRole::single);
         else if (valueStr == "master")
-            value = static_cast<uint8_t>(NodeRole::master);
+            value = static_cast<uint8_t>(NodeRole::controller);
         else if (valueStr == "slave")
-            value = static_cast<uint8_t>(NodeRole::slave);
+            value = static_cast<uint8_t>(NodeRole::target);
         else if (valueStr == "arbitrating")
             value = static_cast<uint8_t>(NodeRole::arbitrating);
         else
diff --git a/src/oemcommands.cpp b/src/oemcommands.cpp
index cb506c9..11dab6f 100644
--- a/src/oemcommands.cpp
+++ b/src/oemcommands.cpp
@@ -171,7 +171,7 @@
 {
 static uint8_t bus = 4;
 static std::string i2cBus = "/dev/i2c-" + std::to_string(bus);
-static uint8_t slaveAddr = 56;
+static uint8_t targetAddr = 56;
 static constexpr auto systemRoot = "/xyz/openbmc_project/inventory/system";
 static constexpr auto sessionIntf = "xyz.openbmc_project.Configuration.PFR";
 const std::string match = "Baseboard/PFR";
@@ -258,7 +258,7 @@
 
         bus = static_cast<int>(*i2cBusNum);
         i2cBus = "/dev/i2c-" + std::to_string(bus);
-        slaveAddr = static_cast<int>(*address);
+        targetAddr = static_cast<int>(*address);
 
         i2cConfigLoaded = true;
     }
@@ -270,7 +270,8 @@
     // trigger the write FIFO operation.
     std::vector<uint8_t> writeData = {cmdReg, val};
     std::vector<uint8_t> readBuf(0);
-    ipmi::Cc retI2C = ipmi::i2cWriteRead(i2cBus, slaveAddr, writeData, readBuf);
+    ipmi::Cc retI2C =
+        ipmi::i2cWriteRead(i2cBus, targetAddr, writeData, readBuf);
 }
 
 } // namespace mailbox
@@ -809,7 +810,7 @@
 ipmi::RspType<uint8_t, std::vector<uint8_t>>
     ipmiOEMSlotIpmb(ipmi::Context::ptr ctx, uint6_t reserved1,
                     uint2_t slotNumber, uint3_t baseBoardSlotNum,
-                    uint3_t riserSlotNum, uint2_t reserved2, uint8_t slaveAddr,
+                    uint3_t riserSlotNum, uint2_t reserved2, uint8_t targetAddr,
                     uint8_t netFn, uint8_t cmd,
                     std::optional<std::vector<uint8_t>> writeData)
 {
@@ -825,7 +826,7 @@
         ctx->yield, ec, "xyz.openbmc_project.Ipmi.Channel.Ipmb",
         "/xyz/openbmc_project/Ipmi/Channel/Ipmb", "org.openbmc.Ipmb",
         "SlotIpmbRequest", static_cast<uint8_t>(slotNumber),
-        static_cast<uint8_t>(baseBoardSlotNum), slaveAddr, netFn, cmd,
+        static_cast<uint8_t>(baseBoardSlotNum), targetAddr, netFn, cmd,
         *writeData);
     if (ec)
     {
@@ -3720,11 +3721,11 @@
         return ipmi::responseResponseError();
     }
 
-    for (const auto& slaveAddr : addrTable)
+    for (const auto& targetAddr : addrTable)
     {
         std::vector<uint8_t> writeData = {psuRevision};
         std::vector<uint8_t> readBuf(verLen);
-        uint8_t addr = static_cast<uint8_t>(slaveAddr) + addrOffset;
+        uint8_t addr = static_cast<uint8_t>(targetAddr) + addrOffset;
         std::string i2cBus = "/dev/i2c-" + std::to_string(bus);
 
         auto retI2C = ipmi::i2cWriteRead(i2cBus, addr, writeData, readBuf);
@@ -3879,7 +3880,7 @@
     {
 
         phosphor::logging::log<phosphor::logging::level::ERR>(
-            "Calling PFR Load Configuration Function to Get I2C Bus and Slave "
+            "Calling PFR Load Configuration Function to Get I2C Bus and Target "
             "Address ");
 
         ipmi::mailbox::loadPfrConfig(ctx, ipmi::mailbox::i2cConfigLoaded);
@@ -3923,7 +3924,7 @@
                 {
 
                     ipmi::Cc ret = ipmi::i2cWriteRead(ipmi::mailbox::i2cBus,
-                                                      ipmi::mailbox::slaveAddr,
+                                                      ipmi::mailbox::targetAddr,
                                                       writeData, readBuf);
                     if (ret != ipmi::ccSuccess)
                     {
@@ -3952,7 +3953,7 @@
             std::vector<uint8_t> readBuf(numOfBytes);
 
             ipmi::Cc ret = ipmi::i2cWriteRead(ipmi::mailbox::i2cBus,
-                                              ipmi::mailbox::slaveAddr,
+                                              ipmi::mailbox::targetAddr,
                                               writeData, readBuf);
             if (ret != ipmi::ccSuccess)
             {
diff --git a/src/storagecommands.cpp b/src/storagecommands.cpp
index 96e2d2b..ec8df36 100644
--- a/src/storagecommands.cpp
+++ b/src/storagecommands.cpp
@@ -1331,7 +1331,7 @@
         nm.oemID2 = 0x0;
         nm.subType = 0x0D;
         nm.version = 0x1;
-        nm.slaveAddress = 0x2C;
+        nm.targetAddress = 0x2C;
         nm.channelNumber = 0x60;
         nm.healthEventSensor = 0x19;
         nm.exceptionEventSensor = 0x18;