Shift test file, add CXL protocol fields.
diff --git a/sections/cper-section-cxl-protocol.c b/sections/cper-section-cxl-protocol.c
index 41b6ee5..b902cc7 100644
--- a/sections/cper-section-cxl-protocol.c
+++ b/sections/cper-section-cxl-protocol.c
@@ -6,6 +6,7 @@
**/
#include <stdio.h>
#include "json.h"
+#include "b64.h"
#include "../edk/Cper.h"
#include "../cper-utils.h"
#include "cper-section-cxl-protocol.h"
@@ -70,7 +71,13 @@
if (cxl_protocol_error->CxlAgentType == CXL_PROTOCOL_ERROR_DEVICE_AGENT)
{
json_object_object_add(section_ir, "deviceSerial", json_object_new_uint64(cxl_protocol_error->DeviceSerial));
- //todo: add generic parser for PCI capability structure (see Cper.h)
+
+ //The PCIe capability structure provided here could either be PCIe 1.1 Capability Structure
+ //(36-byte, padded to 60 bytes) or PCIe 2.0 Capability Structure (60-byte). There does not seem
+ //to be a way to differentiate these, so this is left as a b64 dump.
+ char* encoded = b64_encode(cxl_protocol_error->CapabilityStructure.PcieCap, 60);
+ json_object_object_add(section_ir, "capabilityStructure", json_object_new_uint64(cxl_protocol_error->DeviceSerial));
+ free(encoded);
}
//CXL DVSEC & error log length.
@@ -78,11 +85,17 @@
json_object_object_add(section_ir, "errorLogLength", json_object_new_int(cxl_protocol_error->CxlErrorLogLength));
//CXL DVSEC
- //todo: for CXL 1.1 devices, implement this as the "CXL DVSEC For Flex Bus Device" structure as in CXL 1.1 spec.
- //todo: for CXL 1.1 host downstream port, implement this as "CXL DVSEC For Flex Bus Port" structure as in CXL 1.1 spec.
+ //For CXL 1.1 devices, this is the "CXL DVSEC For Flex Bus Device" structure as in CXL 1.1 spec.
+ unsigned char* cur_pos = (unsigned char*)(cxl_protocol_error + 1);
+ char* encoded = b64_encode(cur_pos, cxl_protocol_error->CxlDvsecLength);
+ json_object_object_add(section_ir, "capabilityStructure", json_object_new_uint64(cxl_protocol_error->DeviceSerial));
+ free(encoded);
+ cur_pos += cxl_protocol_error->CxlDvsecLength;
+
+ //For CXL 1.1 host downstream ports, this is the "CXL DVSEC For Flex Bus Port" structure as in CXL 1.1 spec.
//CXL Error Log
- //todo: implement this as the "CXL RAS Capability Structure" as in CXL 1.1 spec.
+ //This as the "CXL RAS Capability Structure" as in CXL 1.1 spec.
return section_ir;
}
\ No newline at end of file