diff --git a/CMakeLists.txt b/CMakeLists.txt
index d1a284a..4330659 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -27,7 +27,7 @@
 file(GLOB SectionSources sections/*.c)
 file(GLOB EDKSources edk/*.c)
 add_library(CPERParseLibrary STATIC cper-parse.c cper-utils.c ${SectionSources} ${EDKSources})
-add_executable(CPERParseTest cper-test.c)
+add_executable(CPERParseTest testing/cper-test.c)
 
 # Link library.
 target_link_libraries(CPERParseLibrary json-c b64c)
diff --git a/sections/cper-section-cxl-protocol.c b/sections/cper-section-cxl-protocol.c
index 41b6ee5..b902cc7 100644
--- a/sections/cper-section-cxl-protocol.c
+++ b/sections/cper-section-cxl-protocol.c
@@ -6,6 +6,7 @@
  **/
 #include <stdio.h>
 #include "json.h"
+#include "b64.h"
 #include "../edk/Cper.h"
 #include "../cper-utils.h"
 #include "cper-section-cxl-protocol.h"
@@ -70,7 +71,13 @@
     if (cxl_protocol_error->CxlAgentType == CXL_PROTOCOL_ERROR_DEVICE_AGENT)
     {
         json_object_object_add(section_ir, "deviceSerial", json_object_new_uint64(cxl_protocol_error->DeviceSerial));
-        //todo: add generic parser for PCI capability structure (see Cper.h)
+
+        //The PCIe capability structure provided here could either be PCIe 1.1 Capability Structure 
+        //(36-byte, padded to 60 bytes) or PCIe 2.0 Capability Structure (60-byte). There does not seem
+        //to be a way to differentiate these, so this is left as a b64 dump.
+        char* encoded = b64_encode(cxl_protocol_error->CapabilityStructure.PcieCap, 60);
+        json_object_object_add(section_ir, "capabilityStructure", json_object_new_uint64(cxl_protocol_error->DeviceSerial));
+        free(encoded);
     }
 
     //CXL DVSEC & error log length.
@@ -78,11 +85,17 @@
     json_object_object_add(section_ir, "errorLogLength", json_object_new_int(cxl_protocol_error->CxlErrorLogLength));
 
     //CXL DVSEC
-    //todo: for CXL 1.1 devices, implement this as the "CXL DVSEC For Flex Bus Device" structure as in CXL 1.1 spec.
-    //todo: for CXL 1.1 host downstream port, implement this as "CXL DVSEC For Flex Bus Port" structure as in CXL 1.1 spec.
+    //For CXL 1.1 devices, this is the "CXL DVSEC For Flex Bus Device" structure as in CXL 1.1 spec.
+    unsigned char* cur_pos = (unsigned char*)(cxl_protocol_error + 1);
+    char* encoded = b64_encode(cur_pos, cxl_protocol_error->CxlDvsecLength);
+    json_object_object_add(section_ir, "capabilityStructure", json_object_new_uint64(cxl_protocol_error->DeviceSerial));
+    free(encoded);
+    cur_pos += cxl_protocol_error->CxlDvsecLength;
+
+    //For CXL 1.1 host downstream ports, this is the "CXL DVSEC For Flex Bus Port" structure as in CXL 1.1 spec.
 
     //CXL Error Log
-    //todo: implement this as the "CXL RAS Capability Structure" as in CXL 1.1 spec.
+    //This as the "CXL RAS Capability Structure" as in CXL 1.1 spec.
     
     return section_ir;
 }
\ No newline at end of file
diff --git a/cper-test.c b/testing/cper-test.c
similarity index 85%
rename from cper-test.c
rename to testing/cper-test.c
index 12bfc48..6f6534d 100644
--- a/cper-test.c
+++ b/testing/cper-test.c
@@ -1,5 +1,5 @@
 #include <stdio.h>
-#include "cper-parse.h"
+#include "../cper-parse.h"
 #include "json.h"
 
 int main(int argc, char* argv[]) {