Add AER registers to PCIe decoding
Break out AER registers so aerinfo doesn't require manual interpretation
Change-Id: I5e626155270636420a1f6e7c473a2b15bfa7ecf0
Signed-off-by: Andrew Adriance <aadriance@nvidia.com>
diff --git a/sections/cper-section-pcie.c b/sections/cper-section-pcie.c
index ecf6d52..41cebb3 100644
--- a/sections/cper-section-pcie.c
+++ b/sections/cper-section-pcie.c
@@ -12,6 +12,17 @@
#include <libcper/cper-utils.h>
#include <libcper/sections/cper-section-pcie.h>
+struct aer_info_registers {
+ UINT32 pcie_capability_header;
+ UINT32 uncorrectable_error_status;
+ UINT32 uncorrectable_error_mask;
+ UINT32 uncorrectable_error_severity;
+ UINT32 correctable_error_status;
+ UINT32 correctable_error_mask;
+ UINT32 aer_capabilites_control;
+ UINT32 tlp_header_log[4];
+};
+
//Converts a single PCIe CPER section into JSON IR.
json_object *cper_section_pcie_to_ir(void *section)
{
@@ -134,6 +145,43 @@
encoded_len));
free(encoded);
}
+
+ struct aer_info_registers *aer_decode;
+ aer_decode = (struct aer_info_registers *)&pcie_error->AerInfo.PcieAer;
+ json_object_object_add(
+ aer_capability_ir, "capability_header",
+ json_object_new_uint64(aer_decode->pcie_capability_header));
+ json_object_object_add(
+ aer_capability_ir, "uncorrectable_error_status",
+ json_object_new_uint64(aer_decode->uncorrectable_error_status));
+ json_object_object_add(
+ aer_capability_ir, "uncorrectable_error_mask",
+ json_object_new_uint64(aer_decode->uncorrectable_error_mask));
+ json_object_object_add(
+ aer_capability_ir, "uncorrectable_error_severity",
+ json_object_new_uint64(
+ aer_decode->uncorrectable_error_severity));
+ json_object_object_add(
+ aer_capability_ir, "correctable_error_status",
+ json_object_new_uint64(aer_decode->correctable_error_status));
+ json_object_object_add(
+ aer_capability_ir, "correctable_error_mask",
+ json_object_new_uint64(aer_decode->correctable_error_mask));
+ json_object_object_add(
+ aer_capability_ir, "capabilites_control",
+ json_object_new_uint64(aer_decode->aer_capabilites_control));
+ json_object_object_add(
+ aer_capability_ir, "tlp_header_0",
+ json_object_new_uint64(aer_decode->tlp_header_log[0]));
+ json_object_object_add(
+ aer_capability_ir, "tlp_header_1",
+ json_object_new_uint64(aer_decode->tlp_header_log[1]));
+ json_object_object_add(
+ aer_capability_ir, "tlp_header_2",
+ json_object_new_uint64(aer_decode->tlp_header_log[2]));
+ json_object_object_add(
+ aer_capability_ir, "tlp_header_3",
+ json_object_new_uint64(aer_decode->tlp_header_log[3]));
json_object_object_add(section_ir, "aerInfo", aer_capability_ir);
return section_ir;
diff --git a/specification/json/sections/cper-pcie.json b/specification/json/sections/cper-pcie.json
index 14581a3..9c3fd1f 100644
--- a/specification/json/sections/cper-pcie.json
+++ b/specification/json/sections/cper-pcie.json
@@ -154,6 +154,39 @@
"properties": {
"data": {
"type": "string"
+ },
+ "capability_header": {
+ "type": "integer"
+ },
+ "uncorrectable_error_status": {
+ "type": "integer"
+ },
+ "uncorrectable_error_mask": {
+ "type": "integer"
+ },
+ "uncorrectable_error_severity": {
+ "type": "integer"
+ },
+ "correctable_error_status": {
+ "type": "integer"
+ },
+ "correctable_error_mask": {
+ "type": "integer"
+ },
+ "capabilites_control": {
+ "type": "integer"
+ },
+ "tlp_header_0": {
+ "type": "integer"
+ },
+ "tlp_header_1": {
+ "type": "integer"
+ },
+ "tlp_header_2": {
+ "type": "integer"
+ },
+ "tlp_header_3": {
+ "type": "integer"
}
}
}