commit 3cebfc2879e7733b392faf8a53a82f35ce7447ee
author Andrew Adriance <aadriance@nvidia.com> Wed Nov 20 12:57:04 2024 -0800
committer Ed Tanous <ed@tanous.net> Thu Dec 05 23:42:14 2024 +0000
tree 5a57fdf29bee2d36565bdc1ba0883b63ddeb10bc
parent 17bc66a05a9cdc36f9d05c95dca0effdcfe606db

Add AER registers to PCIe decoding

Break out AER registers so aerinfo doesn't require manual interpretation

Change-Id: I5e626155270636420a1f6e7c473a2b15bfa7ecf0
Signed-off-by: Andrew Adriance <aadriance@nvidia.com>

specification/json/sections/cper-pcie.json

diff --git a/specification/json/sections/cper-pcie.json b/specification/json/sections/cper-pcie.json
index 14581a3..9c3fd1f 100644
--- a/specification/json/sections/cper-pcie.json
+++ b/specification/json/sections/cper-pcie.json
@@ -154,6 +154,39 @@
             "properties": {
                 "data": {
                     "type": "string"
+                },
+                "capability_header": {
+                    "type": "integer"
+                },
+                "uncorrectable_error_status": {
+                    "type": "integer"
+                },
+                "uncorrectable_error_mask": {
+                    "type": "integer"
+                },
+                "uncorrectable_error_severity": {
+                    "type": "integer"
+                },
+                "correctable_error_status": {
+                    "type": "integer"
+                },
+                "correctable_error_mask": {
+                    "type": "integer"
+                },
+                "capabilites_control": {
+                    "type": "integer"
+                },
+                "tlp_header_0": {
+                    "type": "integer"
+                },
+                "tlp_header_1": {
+                    "type": "integer"
+                },
+                "tlp_header_2": {
+                    "type": "integer"
+                },
+                "tlp_header_3": {
+                    "type": "integer"
                 }
             }
         }