diff --git a/include/libcper/BaseTypes.h b/include/libcper/BaseTypes.h
new file mode 100644
index 0000000..93320e4
--- /dev/null
+++ b/include/libcper/BaseTypes.h
@@ -0,0 +1,109 @@
+/** @file
+  Processor or Compiler specific defines for all supported processors.
+
+  This file is stand alone self consistent set of definitions.
+
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef CPER_BASETYPES_H
+#define CPER_BASETYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+///
+/// 8-byte unsigned value
+///
+typedef unsigned long long UINT64;
+///
+/// 8-byte signed value
+///
+typedef long long INT64;
+///
+/// 4-byte unsigned value
+///
+typedef unsigned int UINT32;
+///
+/// 4-byte signed value
+///
+typedef int INT32;
+///
+/// 2-byte unsigned value
+///
+typedef unsigned short UINT16;
+///
+/// 2-byte Character.  Unless otherwise specified all strings are stored in the
+/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
+///
+typedef unsigned short CHAR16;
+///
+/// 2-byte signed value
+///
+typedef short INT16;
+///
+/// Logical Boolean.  1-byte value containing 0 for FALSE or a 1 for TRUE.  Other
+/// values are undefined.
+///
+typedef unsigned char BOOLEAN;
+///
+/// 1-byte unsigned value
+///
+typedef unsigned char UINT8;
+///
+/// 1-byte Character
+///
+typedef char CHAR8;
+///
+/// 1-byte signed value
+///
+typedef signed char INT8;
+//
+// Basical data type definitions introduced in UEFI.
+//
+typedef struct {
+	UINT32 Data1;
+	UINT16 Data2;
+	UINT16 Data3;
+	UINT8 Data4[8];
+} EFI_GUID;
+
+/**
+  Returns a 16-bit signature built from 2 ASCII characters.
+
+  This macro returns a 16-bit value built from the two ASCII characters specified
+  by A and B.
+
+  @param  A    The first ASCII character.
+  @param  B    The second ASCII character.
+
+  @return A 16-bit value built from the two ASCII characters specified by A and B.
+
+**/
+#define SIGNATURE_16(A, B) ((A) | (B << 8))
+/**
+  Returns a 32-bit signature built from 4 ASCII characters.
+
+  This macro returns a 32-bit value built from the four ASCII characters specified
+  by A, B, C, and D.
+
+  @param  A    The first ASCII character.
+  @param  B    The second ASCII character.
+  @param  C    The third ASCII character.
+  @param  D    The fourth ASCII character.
+
+  @return A 32-bit value built from the two ASCII characters specified by A, B,
+          C and D.
+
+**/
+#define SIGNATURE_32(A, B, C, D)                                               \
+	(SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/Cper.h b/include/libcper/Cper.h
new file mode 100644
index 0000000..4a647cf
--- /dev/null
+++ b/include/libcper/Cper.h
@@ -0,0 +1,1442 @@
+/** @file
+  GUIDs and definitions used for Common Platform Error Record.
+
+  Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>
+  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  GUIDs defined in UEFI 2.7 Specification.
+
+**/
+
+#ifndef __CPER_GUID_H__
+#define __CPER_GUID_H__
+
+#include <libcper/BaseTypes.h>
+#include <libcper/common-utils.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#pragma pack(push, 1)
+
+#define EFI_ERROR_RECORD_SIGNATURE_START SIGNATURE_32('C', 'P', 'E', 'R')
+#define EFI_ERROR_RECORD_SIGNATURE_END	 0xFFFFFFFF
+
+#define EFI_ERROR_RECORD_REVISION 0x0101
+
+///
+/// Error Severity in Error Record Header and Error Section Descriptor
+///@{
+#define EFI_GENERIC_ERROR_RECOVERABLE 0x00000000
+#define EFI_GENERIC_ERROR_FATAL	      0x00000001
+#define EFI_GENERIC_ERROR_CORRECTED   0x00000002
+#define EFI_GENERIC_ERROR_INFO	      0x00000003
+///@}
+
+///
+/// The validation bit mask indicates the validity of the following fields
+/// in Error Record Header.
+///@{
+#define EFI_ERROR_RECORD_HEADER_PLATFORM_ID_VALID  BIT0
+#define EFI_ERROR_RECORD_HEADER_TIME_STAMP_VALID   BIT1
+#define EFI_ERROR_RECORD_HEADER_PARTITION_ID_VALID BIT2
+///@}
+
+///
+/// Timestamp is precise if this bit is set and correlates to the time of the
+/// error event.
+///
+#define EFI_ERROR_TIME_STAMP_PRECISE BIT0
+
+///
+/// The timestamp correlates to the time when the error information was collected
+/// by the system software and may not necessarily represent the time of the error
+/// event. The timestamp contains the local time in BCD format.
+///
+typedef struct {
+	UINT8 Seconds;
+	UINT8 Minutes;
+	UINT8 Hours;
+	UINT8 Flag;
+	UINT8 Day;
+	UINT8 Month;
+	UINT8 Year;
+	UINT8 Century;
+} EFI_ERROR_TIME_STAMP;
+
+///
+/// GUID value indicating the record association with an error event notification type.
+///@{
+#define EFI_EVENT_NOTIFICATION_TYEP_CMC_GUID                                   \
+	{                                                                      \
+		0x2DCE8BB1, 0xBDD7, 0x450e,                                    \
+		{                                                              \
+			0xB9, 0xAD, 0x9C, 0xF4, 0xEB, 0xD4, 0xF8, 0x90         \
+		}                                                              \
+	}
+#define EFI_EVENT_NOTIFICATION_TYEP_CPE_GUID                                   \
+	{                                                                      \
+		0x4E292F96, 0xD843, 0x4a55,                                    \
+		{                                                              \
+			0xA8, 0xC2, 0xD4, 0x81, 0xF2, 0x7E, 0xBE, 0xEE         \
+		}                                                              \
+	}
+#define EFI_EVENT_NOTIFICATION_TYEP_MCE_GUID                                   \
+	{                                                                      \
+		0xE8F56FFE, 0x919C, 0x4cc5,                                    \
+		{                                                              \
+			0xBA, 0x88, 0x65, 0xAB, 0xE1, 0x49, 0x13, 0xBB         \
+		}                                                              \
+	}
+#define EFI_EVENT_NOTIFICATION_TYEP_PCIE_GUID                                  \
+	{                                                                      \
+		0xCF93C01F, 0x1A16, 0x4dfc,                                    \
+		{                                                              \
+			0xB8, 0xBC, 0x9C, 0x4D, 0xAF, 0x67, 0xC1, 0x04         \
+		}                                                              \
+	}
+#define EFI_EVENT_NOTIFICATION_TYEP_INIT_GUID                                  \
+	{                                                                      \
+		0xCC5263E8, 0x9308, 0x454a,                                    \
+		{                                                              \
+			0x89, 0xD0, 0x34, 0x0B, 0xD3, 0x9B, 0xC9, 0x8E         \
+		}                                                              \
+	}
+#define EFI_EVENT_NOTIFICATION_TYEP_NMI_GUID                                   \
+	{                                                                      \
+		0x5BAD89FF, 0xB7E6, 0x42c9,                                    \
+		{                                                              \
+			0x81, 0x4A, 0xCF, 0x24, 0x85, 0xD6, 0xE9, 0x8A         \
+		}                                                              \
+	}
+#define EFI_EVENT_NOTIFICATION_TYEP_BOOT_GUID                                  \
+	{                                                                      \
+		0x3D61A466, 0xAB40, 0x409a,                                    \
+		{                                                              \
+			0xA6, 0x98, 0xF3, 0x62, 0xD4, 0x64, 0xB3, 0x8F         \
+		}                                                              \
+	}
+#define EFI_EVENT_NOTIFICATION_TYEP_DMAR_GUID                                  \
+	{                                                                      \
+		0x667DD791, 0xC6B3, 0x4c27,                                    \
+		{                                                              \
+			0x8A, 0x6B, 0x0F, 0x8E, 0x72, 0x2D, 0xEB, 0x41         \
+		}                                                              \
+	}
+#define EFI_EVENT_NOTIFICATION_TYPE_DMAR_SEA                                   \
+	{                                                                      \
+		0x9A78788A, 0xBBE8, 0x11E4,                                    \
+		{                                                              \
+			0x80, 0x9E, 0x67, 0x61, 0x1E, 0x5D, 0x46, 0xB0         \
+		}                                                              \
+	}
+#define EFI_EVENT_NOTIFICATION_TYPE_DMAR_SEI                                   \
+	{                                                                      \
+		0x5C284C81, 0xB0AE, 0x4E87,                                    \
+		{                                                              \
+			0xA3, 0x22, 0xB0, 0x4C, 0x85, 0x62, 0x43, 0x23         \
+		}                                                              \
+	}
+#define EFI_EVENT_NOTIFICATION_TYPE_DMAR_PEI                                   \
+	{                                                                      \
+		0x09A9D5AC, 0x5204, 0x4214,                                    \
+		{                                                              \
+			0x96, 0xE5, 0x94, 0x99, 0x2E, 0x75, 0x2B, 0xCD         \
+		}                                                              \
+	}
+///@}
+
+///
+/// Error Record Header Flags
+///@{
+#define EFI_HW_ERROR_FLAGS_RECOVERED 0x00000001
+#define EFI_HW_ERROR_FLAGS_PREVERR   0x00000002
+#define EFI_HW_ERROR_FLAGS_SIMULATED 0x00000004
+///@}
+
+///
+/// Common error record header
+///
+typedef struct {
+	UINT32 SignatureStart;
+	UINT16 Revision;
+	UINT32 SignatureEnd;
+	UINT16 SectionCount;
+	UINT32 ErrorSeverity;
+	UINT32 ValidationBits;
+	UINT32 RecordLength;
+	EFI_ERROR_TIME_STAMP TimeStamp;
+	EFI_GUID PlatformID;
+	EFI_GUID PartitionID;
+	EFI_GUID CreatorID;
+	EFI_GUID NotificationType;
+	UINT64 RecordID;
+	UINT32 Flags;
+	UINT64 PersistenceInfo;
+	UINT8 Resv1[12];
+	///
+	/// An array of SectionCount descriptors for the associated
+	/// sections. The number of valid sections is equivalent to the
+	/// SectionCount. The buffer size of the record may include
+	/// more space to dynamically add additional Section
+	/// Descriptors to the error record.
+	///
+} EFI_COMMON_ERROR_RECORD_HEADER;
+
+#define EFI_ERROR_SECTION_REVISION 0x0100
+
+///
+/// Validity Fields in Error Section Descriptor.
+///
+#define EFI_ERROR_SECTION_FRU_ID_VALID	   BIT0
+#define EFI_ERROR_SECTION_FRU_STRING_VALID BIT1
+
+///
+/// Flag field contains information that describes the error section
+/// in Error Section Descriptor.
+///
+#define EFI_ERROR_SECTION_FLAGS_PRIMARY			 BIT0
+#define EFI_ERROR_SECTION_FLAGS_CONTAINMENT_WARNING	 BIT1
+#define EFI_ERROR_SECTION_FLAGS_RESET			 BIT2
+#define EFI_ERROR_SECTION_FLAGS_ERROR_THRESHOLD_EXCEEDED BIT3
+#define EFI_ERROR_SECTION_FLAGS_RESOURCE_NOT_ACCESSIBLE	 BIT4
+#define EFI_ERROR_SECTION_FLAGS_LATENT_ERROR		 BIT5
+
+///
+/// Error Sectition Type GUIDs in Error Section Descriptor
+///@{
+#define EFI_ERROR_SECTION_PROCESSOR_GENERIC_GUID                               \
+	{                                                                      \
+		0x9876ccad, 0x47b4, 0x4bdb,                                    \
+		{                                                              \
+			0xb6, 0x5e, 0x16, 0xf1, 0x93, 0xc4, 0xf3, 0xdb         \
+		}                                                              \
+	}
+#define EFI_ERROR_SECTION_PROCESSOR_SPECIFIC_GUID                              \
+	{                                                                      \
+		0xdc3ea0b0, 0xa144, 0x4797,                                    \
+		{                                                              \
+			0xb9, 0x5b, 0x53, 0xfa, 0x24, 0x2b, 0x6e, 0x1d         \
+		}                                                              \
+	}
+#define EFI_ERROR_SECTION_PROCESSOR_SPECIFIC_IA32X64_GUID                      \
+	{                                                                      \
+		0xdc3ea0b0, 0xa144, 0x4797,                                    \
+		{                                                              \
+			0xb9, 0x5b, 0x53, 0xfa, 0x24, 0x2b, 0x6e, 0x1d         \
+		}                                                              \
+	}
+#define EFI_ERROR_SECTION_PROCESSOR_SPECIFIC_ARM_GUID                          \
+	{                                                                      \
+		0xe19e3d16, 0xbc11, 0x11e4,                                    \
+		{                                                              \
+			0x9c, 0xaa, 0xc2, 0x05, 0x1d, 0x5d, 0x46, 0xb0         \
+		}                                                              \
+	}
+#define EFI_ERROR_SECTION_PLATFORM_MEMORY_GUID                                 \
+	{                                                                      \
+		0xa5bc1114, 0x6f64, 0x4ede,                                    \
+		{                                                              \
+			0xb8, 0x63, 0x3e, 0x83, 0xed, 0x7c, 0x83, 0xb1         \
+		}                                                              \
+	}
+#define EFI_ERROR_SECTION_PLATFORM_MEMORY2_GUID                                \
+	{                                                                      \
+		0x61EC04FC, 0x48E6, 0xD813,                                    \
+		{                                                              \
+			0x25, 0xC9, 0x8D, 0xAA, 0x44, 0x75, 0x0B, 0x12         \
+		}                                                              \
+	}
+#define EFI_ERROR_SECTION_PCIE_GUID                                            \
+	{                                                                      \
+		0xd995e954, 0xbbc1, 0x430f,                                    \
+		{                                                              \
+			0xad, 0x91, 0xb4, 0x4d, 0xcb, 0x3c, 0x6f, 0x35         \
+		}                                                              \
+	}
+#define EFI_ERROR_SECTION_FW_ERROR_RECORD_GUID                                 \
+	{                                                                      \
+		0x81212a96, 0x09ed, 0x4996,                                    \
+		{                                                              \
+			0x94, 0x71, 0x8d, 0x72, 0x9c, 0x8e, 0x69, 0xed         \
+		}                                                              \
+	}
+#define EFI_ERROR_SECTION_PCI_PCIX_BUS_GUID                                    \
+	{                                                                      \
+		0xc5753963, 0x3b84, 0x4095,                                    \
+		{                                                              \
+			0xbf, 0x78, 0xed, 0xda, 0xd3, 0xf9, 0xc9, 0xdd         \
+		}                                                              \
+	}
+#define EFI_ERROR_SECTION_PCI_DEVICE_GUID                                      \
+	{                                                                      \
+		0xeb5e4685, 0xca66, 0x4769,                                    \
+		{                                                              \
+			0xb6, 0xa2, 0x26, 0x06, 0x8b, 0x00, 0x13, 0x26         \
+		}                                                              \
+	}
+#define EFI_ERROR_SECTION_DMAR_GENERIC_GUID                                    \
+	{                                                                      \
+		0x5b51fef7, 0xc79d, 0x4434,                                    \
+		{                                                              \
+			0x8f, 0x1b, 0xaa, 0x62, 0xde, 0x3e, 0x2c, 0x64         \
+		}                                                              \
+	}
+#define EFI_ERROR_SECTION_DIRECTED_IO_DMAR_GUID                                \
+	{                                                                      \
+		0x71761d37, 0x32b2, 0x45cd,                                    \
+		{                                                              \
+			0xa7, 0xd0, 0xb0, 0xfe, 0xdd, 0x93, 0xe8, 0xcf         \
+		}                                                              \
+	}
+#define EFI_ERROR_SECTION_IOMMU_DMAR_GUID                                      \
+	{                                                                      \
+		0x036f84e1, 0x7f37, 0x428c,                                    \
+		{                                                              \
+			0xa7, 0x9e, 0x57, 0x5f, 0xdf, 0xaa, 0x84, 0xec         \
+		}                                                              \
+	}
+#define EFI_ERROR_SECTION_AMPERE_SPECIFIC_GUID                                 \
+	{                                                                      \
+		0x2826cc9f, 0x448c, 0x4c2b,                                    \
+		{                                                              \
+			0x86, 0xb6, 0xa9, 0x53, 0x94, 0xb7, 0xef, 0x33         \
+		}                                                              \
+	}
+///@}
+
+///
+/// Error Section Descriptor
+///
+typedef struct {
+	UINT32 SectionOffset;
+	UINT32 SectionLength;
+	UINT16 Revision;
+	UINT8 SecValidMask;
+	UINT8 Resv1;
+	UINT32 SectionFlags;
+	EFI_GUID SectionType;
+	EFI_GUID FruId;
+	UINT32 Severity;
+	CHAR8 FruString[20];
+} EFI_ERROR_SECTION_DESCRIPTOR;
+
+///
+/// The validation bit mask indicates whether or not each of the following fields are
+/// valid in Proessor Generic Error section.
+///@{
+#define EFI_GENERIC_ERROR_PROC_TYPE_VALID	  BIT0
+#define EFI_GENERIC_ERROR_PROC_ISA_VALID	  BIT1
+#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_VALID	  BIT2
+#define EFI_GENERIC_ERROR_PROC_OPERATION_VALID	  BIT3
+#define EFI_GENERIC_ERROR_PROC_FLAGS_VALID	  BIT4
+#define EFI_GENERIC_ERROR_PROC_LEVEL_VALID	  BIT5
+#define EFI_GENERIC_ERROR_PROC_VERSION_VALID	  BIT6
+#define EFI_GENERIC_ERROR_PROC_BRAND_VALID	  BIT7
+#define EFI_GENERIC_ERROR_PROC_ID_VALID		  BIT8
+#define EFI_GENERIC_ERROR_PROC_TARGET_ADDR_VALID  BIT9
+#define EFI_GENERIC_ERROR_PROC_REQUESTER_ID_VALID BIT10
+#define EFI_GENERIC_ERROR_PROC_RESPONDER_ID_VALID BIT11
+#define EFI_GENERIC_ERROR_PROC_INST_IP_VALID	  BIT12
+///@}
+
+///
+/// The type of the processor architecture in Proessor Generic Error section.
+///@{
+#define EFI_GENERIC_ERROR_PROC_TYPE_IA32_X64 0x00
+#define EFI_GENERIC_ERROR_PROC_TYPE_IA64     0x01
+#define EFI_GENERIC_ERROR_PROC_TYPE_ARM	     0x02
+///@}
+
+///
+/// The type of the instruction set executing when the error occurred in Proessor
+/// Generic Error section.
+///@{
+#define EFI_GENERIC_ERROR_PROC_ISA_IA32	       0x00
+#define EFI_GENERIC_ERROR_PROC_ISA_IA64	       0x01
+#define EFI_GENERIC_ERROR_PROC_ISA_X64	       0x02
+#define EFI_GENERIC_ERROR_PROC_ISA_ARM_A32_T32 0x03
+#define EFI_GENERIC_ERROR_PROC_ISA_ARM_A64     0x04
+///@}
+
+///
+/// The type of error that occurred in Proessor Generic Error section.
+///@{
+#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_UNKNOWN    0x00
+#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_CACHE	     0x01
+#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_TLB	     0x02
+#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_BUS	     0x04
+#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_MICRO_ARCH 0x08
+///@}
+
+///
+/// The type of operation in Proessor Generic Error section.
+///@{
+#define EFI_GENERIC_ERROR_PROC_OPERATION_GENERIC	  0x00
+#define EFI_GENERIC_ERROR_PROC_OPERATION_DATA_READ	  0x01
+#define EFI_GENERIC_ERROR_PROC_OPERATION_DATA_WRITE	  0x02
+#define EFI_GENERIC_ERROR_PROC_OPERATION_INSTRUCTION_EXEC 0x03
+///@}
+
+///
+/// Flags bit mask indicates additional information about the error in Proessor Generic
+/// Error section
+///@{
+#define EFI_GENERIC_ERROR_PROC_FLAGS_RESTARTABLE BIT0
+#define EFI_GENERIC_ERROR_PROC_FLAGS_PRECISE_IP	 BIT1
+#define EFI_GENERIC_ERROR_PROC_FLAGS_OVERFLOW	 BIT2
+#define EFI_GENERIC_ERROR_PROC_FLAGS_CORRECTED	 BIT3
+///@}
+
+///
+/// Processor Generic Error Section
+/// describes processor reported hardware errors for logical processors in the system.
+///
+typedef struct {
+	UINT64 ValidFields;
+	UINT8 Type;
+	UINT8 Isa;
+	UINT8 ErrorType;
+	UINT8 Operation;
+	UINT8 Flags;
+	UINT8 Level;
+	UINT16 Resv1;
+	UINT64 VersionInfo;
+	CHAR8 BrandString[128];
+	UINT64 ApicId;
+	UINT64 TargetAddr;
+	UINT64 RequestorId;
+	UINT64 ResponderId;
+	UINT64 InstructionIP;
+} EFI_PROCESSOR_GENERIC_ERROR_DATA;
+
+///
+/// IA32 and x64 Specific definitions.
+///
+
+///
+/// GUID value indicating the type of Processor Error Information structure
+/// in IA32/X64 Processor Error Information Structure.
+///@{
+#define EFI_IA32_X64_ERROR_TYPE_CACHE_CHECK_GUID                               \
+	{                                                                      \
+		0xA55701F5, 0xE3EF, 0x43de,                                    \
+		{                                                              \
+			0xAC, 0x72, 0x24, 0x9B, 0x57, 0x3F, 0xAD, 0x2C         \
+		}                                                              \
+	}
+#define EFI_IA32_X64_ERROR_TYPE_TLB_CHECK_GUID                                 \
+	{                                                                      \
+		0xFC06B535, 0x5E1F, 0x4562,                                    \
+		{                                                              \
+			0x9F, 0x25, 0x0A, 0x3B, 0x9A, 0xDB, 0x63, 0xC3         \
+		}                                                              \
+	}
+#define EFI_IA32_X64_ERROR_TYPE_BUS_CHECK_GUID                                 \
+	{                                                                      \
+		0x1CF3F8B3, 0xC5B1, 0x49a2,                                    \
+		{                                                              \
+			0xAA, 0x59, 0x5E, 0xEF, 0x92, 0xFF, 0xA6, 0x3C         \
+		}                                                              \
+	}
+#define EFI_IA32_X64_ERROR_TYPE_MS_CHECK_GUID                                  \
+	{                                                                      \
+		0x48AB7F57, 0xDC34, 0x4f6c,                                    \
+		{                                                              \
+			0xA7, 0xD3, 0xB0, 0xB5, 0xB0, 0xA7, 0x43, 0x14         \
+		}                                                              \
+	}
+extern EFI_GUID gEfiIa32x64ErrorTypeCacheCheckGuid;
+extern EFI_GUID gEfiIa32x64ErrorTypeTlbCheckGuid;
+extern EFI_GUID gEfiIa32x64ErrorTypeBusCheckGuid;
+extern EFI_GUID gEfiIa32x64ErrorTypeMsCheckGuid;
+
+///@}
+
+///
+/// The validation bit mask indicates which fields in the IA32/X64 Processor
+/// Error Record structure are valid.
+///@{
+#define EFI_IA32_X64_PROCESSOR_ERROR_APIC_ID_VALID     BIT0
+#define EFI_IA32_X64_PROCESSOR_ERROR_CPU_ID_INFO_VALID BIT1
+///@}
+
+///
+/// IA32/X64 Processor Error Record
+///
+typedef struct {
+	UINT64 ValidFields;
+	UINT64 ApicId;
+	UINT8 CpuIdInfo[48];
+} EFI_IA32_X64_PROCESSOR_ERROR_RECORD;
+
+///
+/// The validation bit mask indicates which fields in the Cache Check structure
+/// are valid.
+///@{
+#define EFI_CACHE_CHECK_TRANSACTION_TYPE_VALID BIT0
+#define EFI_CACHE_CHECK_OPERATION_VALID	       BIT1
+#define EFI_CACHE_CHECK_LEVEL_VALID	       BIT2
+#define EFI_CACHE_CHECK_CONTEXT_CORRUPT_VALID  BIT3
+#define EFI_CACHE_CHECK_UNCORRECTED_VALID      BIT4
+#define EFI_CACHE_CHECK_PRECISE_IP_VALID       BIT5
+#define EFI_CACHE_CHECK_RESTARTABLE_VALID      BIT6
+#define EFI_CACHE_CHECK_OVERFLOW_VALID	       BIT7
+///@}
+
+///
+/// Type of cache error in the Cache Check structure
+///@{
+#define EFI_CACHE_CHECK_ERROR_TYPE_INSTRUCTION 0
+#define EFI_CACHE_CHECK_ERROR_TYPE_DATA_ACCESS 1
+#define EFI_CACHE_CHECK_ERROR_TYPE_GENERIC     2
+///@}
+
+///
+/// Type of cache operation that caused the error in the Cache
+/// Check structure
+///@{
+#define EFI_CACHE_CHECK_OPERATION_TYPE_GENERIC		 0
+#define EFI_CACHE_CHECK_OPERATION_TYPE_GENERIC_READ	 1
+#define EFI_CACHE_CHECK_OPERATION_TYPE_GENERIC_WRITE	 2
+#define EFI_CACHE_CHECK_OPERATION_TYPE_DATA_READ	 3
+#define EFI_CACHE_CHECK_OPERATION_TYPE_DATA_WRITE	 4
+#define EFI_CACHE_CHECK_OPERATION_TYPE_INSTRUCTION_FETCH 5
+#define EFI_CACHE_CHECK_OPERATION_TYPE_PREFETCH		 6
+#define EFI_CACHE_CHECK_OPERATION_TYPE_EVICTION		 7
+#define EFI_CACHE_CHECK_OPERATION_TYPE_SNOOP		 8
+///@}
+
+///
+/// IA32/X64 Cache Check Structure
+///
+typedef struct {
+	UINT64 ValidFields : 16;
+	UINT64 TransactionType : 2;
+	UINT64 Operation : 4;
+	UINT64 Level : 3;
+	UINT64 ContextCorrupt : 1;
+	UINT64 ErrorUncorrected : 1;
+	UINT64 PreciseIp : 1;
+	UINT64 RestartableIp : 1;
+	UINT64 Overflow : 1;
+	UINT64 Resv1 : 34;
+} EFI_IA32_X64_CACHE_CHECK_INFO;
+
+///
+/// The validation bit mask indicates which fields in the TLB Check structure
+/// are valid.
+///@{
+#define EFI_TLB_CHECK_TRANSACTION_TYPE_VALID BIT0
+#define EFI_TLB_CHECK_OPERATION_VALID	     BIT1
+#define EFI_TLB_CHECK_LEVEL_VALID	     BIT2
+#define EFI_TLB_CHECK_CONTEXT_CORRUPT_VALID  BIT3
+#define EFI_TLB_CHECK_UNCORRECTED_VALID	     BIT4
+#define EFI_TLB_CHECK_PRECISE_IP_VALID	     BIT5
+#define EFI_TLB_CHECK_RESTARTABLE_VALID	     BIT6
+#define EFI_TLB_CHECK_OVERFLOW_VALID	     BIT7
+///@}
+
+///
+/// Type of cache error in the TLB Check structure
+///@{
+#define EFI_TLB_CHECK_ERROR_TYPE_INSTRUCTION 0
+#define EFI_TLB_CHECK_ERROR_TYPE_DATA_ACCESS 1
+#define EFI_TLB_CHECK_ERROR_TYPE_GENERIC     2
+///@}
+
+///
+/// Type of cache operation that caused the error in the TLB
+/// Check structure
+///@{
+#define EFI_TLB_CHECK_OPERATION_TYPE_GENERIC	   0
+#define EFI_TLB_CHECK_OPERATION_TYPE_GENERIC_READ  1
+#define EFI_TLB_CHECK_OPERATION_TYPE_GENERIC_WRITE 2
+#define EFI_TLB_CHECK_OPERATION_TYPE_DATA_READ	   3
+#define EFI_TLB_CHECK_OPERATION_TYPE_DATA_WRITE	   4
+#define EFI_TLB_CHECK_OPERATION_TYPE_INST_FETCH	   5
+#define EFI_TLB_CHECK_OPERATION_TYPE_PREFETCH	   6
+///@}
+
+///
+/// IA32/X64 TLB Check Structure
+///
+typedef struct {
+	UINT64 ValidFields : 16;
+	UINT64 TransactionType : 2;
+	UINT64 Operation : 4;
+	UINT64 Level : 3;
+	UINT64 ContextCorrupt : 1;
+	UINT64 ErrorUncorrected : 1;
+	UINT64 PreciseIp : 1;
+	UINT64 RestartableIp : 1;
+	UINT64 Overflow : 1;
+	UINT64 Resv1 : 34;
+} EFI_IA32_X64_TLB_CHECK_INFO;
+
+///
+/// The validation bit mask indicates which fields in the MS Check structure
+/// are valid.
+///@{
+#define EFI_BUS_CHECK_TRANSACTION_TYPE_VALID   BIT0
+#define EFI_BUS_CHECK_OPERATION_VALID	       BIT1
+#define EFI_BUS_CHECK_LEVEL_VALID	       BIT2
+#define EFI_BUS_CHECK_CONTEXT_CORRUPT_VALID    BIT3
+#define EFI_BUS_CHECK_UNCORRECTED_VALID	       BIT4
+#define EFI_BUS_CHECK_PRECISE_IP_VALID	       BIT5
+#define EFI_BUS_CHECK_RESTARTABLE_VALID	       BIT6
+#define EFI_BUS_CHECK_OVERFLOW_VALID	       BIT7
+#define EFI_BUS_CHECK_PARTICIPATION_TYPE_VALID BIT8
+#define EFI_BUS_CHECK_TIME_OUT_VALID	       BIT9
+#define EFI_BUS_CHECK_ADDRESS_SPACE_VALID      BIT10
+///@}
+
+///
+/// Type of cache error in the Bus Check structure
+///@{
+#define EFI_BUS_CHECK_ERROR_TYPE_INSTRUCTION 0
+#define EFI_BUS_CHECK_ERROR_TYPE_DATA_ACCESS 1
+#define EFI_BUS_CHECK_ERROR_TYPE_GENERIC     2
+///@}
+
+///
+/// Type of cache operation that caused the error in the Bus
+/// Check structure
+///@{
+#define EFI_BUS_CHECK_OPERATION_TYPE_GENERIC	   0
+#define EFI_BUS_CHECK_OPERATION_TYPE_GENERIC_READ  1
+#define EFI_BUS_CHECK_OPERATION_TYPE_GENERIC_WRITE 2
+#define EFI_BUS_CHECK_OPERATION_TYPE_DATA_READ	   3
+#define EFI_BUS_CHECK_OPERATION_TYPE_DATA_WRITE	   4
+#define EFI_BUS_CHECK_OPERATION_TYPE_INST_FETCH	   5
+#define EFI_BUS_CHECK_OPERATION_TYPE_PREFETCH	   6
+///@}
+
+///
+/// Type of Participation
+///@{
+#define EFI_BUS_CHECK_PARTICIPATION_TYPE_REQUEST   0
+#define EFI_BUS_CHECK_PARTICIPATION_TYPE_RESPONDED 1
+#define EFI_BUS_CHECK_PARTICIPATION_TYPE_OBSERVED  2
+#define EFI_BUS_CHECK_PARTICIPATION_TYPE_GENERIC   3
+///@}
+
+///
+/// Type of Address Space
+///@{
+#define EFI_BUS_CHECK_ADDRESS_SPACE_TYPE_MEMORY	  0
+#define EFI_BUS_CHECK_ADDRESS_SPACE_TYPE_RESERVED 1
+#define EFI_BUS_CHECK_ADDRESS_SPACE_TYPE_IO	  2
+#define EFI_BUS_CHECK_ADDRESS_SPACE_TYPE_OTHER	  3
+///@}
+
+///
+/// IA32/X64 Bus Check Structure
+///
+typedef struct {
+	UINT64 ValidFields : 16;
+	UINT64 TransactionType : 2;
+	UINT64 Operation : 4;
+	UINT64 Level : 3;
+	UINT64 ContextCorrupt : 1;
+	UINT64 ErrorUncorrected : 1;
+	UINT64 PreciseIp : 1;
+	UINT64 RestartableIp : 1;
+	UINT64 Overflow : 1;
+	UINT64 ParticipationType : 2;
+	UINT64 TimeOut : 1;
+	UINT64 AddressSpace : 2;
+	UINT64 Resv1 : 29;
+} EFI_IA32_X64_BUS_CHECK_INFO;
+
+///
+/// The validation bit mask indicates which fields in the MS Check structure
+/// are valid.
+///@{
+#define EFI_MS_CHECK_ERROR_TYPE_VALID	   BIT0
+#define EFI_MS_CHECK_CONTEXT_CORRUPT_VALID BIT1
+#define EFI_MS_CHECK_UNCORRECTED_VALID	   BIT2
+#define EFI_MS_CHECK_PRECISE_IP_VALID	   BIT3
+#define EFI_MS_CHECK_RESTARTABLE_VALID	   BIT4
+#define EFI_MS_CHECK_OVERFLOW_VALID	   BIT5
+///@}
+
+///
+/// Error type identifies the operation that caused the error.
+///@{
+#define EFI_MS_CHECK_ERROR_TYPE_NO		      0
+#define EFI_MS_CHECK_ERROR_TYPE_UNCLASSIFIED	      1
+#define EFI_MS_CHECK_ERROR_TYPE_MICROCODE_PARITY      2
+#define EFI_MS_CHECK_ERROR_TYPE_EXTERNAL	      3
+#define EFI_MS_CHECK_ERROR_TYPE_FRC		      4
+#define EFI_MS_CHECK_ERROR_TYPE_INTERNAL_UNCLASSIFIED 5
+///@}
+
+///
+/// IA32/X64 MS Check Field Description
+///
+typedef struct {
+	UINT64 ValidFields : 16;
+	UINT64 ErrorType : 3;
+	UINT64 ContextCorrupt : 1;
+	UINT64 ErrorUncorrected : 1;
+	UINT64 PreciseIp : 1;
+	UINT64 RestartableIp : 1;
+	UINT64 Overflow : 1;
+	UINT64 Resv1 : 40;
+} EFI_IA32_X64_MS_CHECK_INFO;
+
+///
+/// IA32/X64 Check Information Item
+///
+typedef union {
+	EFI_IA32_X64_CACHE_CHECK_INFO CacheCheck;
+	EFI_IA32_X64_TLB_CHECK_INFO TlbCheck;
+	EFI_IA32_X64_BUS_CHECK_INFO BusCheck;
+	EFI_IA32_X64_MS_CHECK_INFO MsCheck;
+	UINT64 Data64;
+} EFI_IA32_X64_CHECK_INFO_ITEM;
+
+///
+/// The validation bit mask indicates which fields in the IA32/X64 Processor Error
+/// Information Structure are valid.
+///@{
+#define EFI_IA32_X64_ERROR_PROC_CHECK_INFO_VALID   BIT0
+#define EFI_IA32_X64_ERROR_PROC_TARGET_ADDR_VALID  BIT1
+#define EFI_IA32_X64_ERROR_PROC_REQUESTER_ID_VALID BIT2
+#define EFI_IA32_X64_ERROR_PROC_RESPONDER_ID_VALID BIT3
+#define EFI_IA32_X64_ERROR_PROC_INST_IP_VALID	   BIT4
+///@}
+
+///
+/// IA32/X64 Processor Error Information Structure
+///
+typedef struct {
+	EFI_GUID ErrorType;
+	UINT64 ValidFields;
+	EFI_IA32_X64_CHECK_INFO_ITEM CheckInfo;
+	UINT64 TargetId;
+	UINT64 RequestorId;
+	UINT64 ResponderId;
+	UINT64 InstructionIP;
+} EFI_IA32_X64_PROCESS_ERROR_INFO;
+
+///
+/// IA32/X64 Processor Context Information Structure
+///
+typedef struct {
+	UINT16 RegisterType;
+	UINT16 ArraySize;
+	UINT32 MsrAddress;
+	UINT64 MmRegisterAddress;
+	//
+	// This field will provide the contents of the actual registers or raw data.
+	// The number of Registers or size of the raw data reported is determined
+	// by (Array Size / 8) or otherwise specified by the context structure type
+	// definition.
+	//
+} EFI_IA32_X64_PROCESSOR_CONTEXT_INFO;
+
+///
+/// Register Context Type
+///@{
+#define EFI_REG_CONTEXT_TYPE_UNCLASSIFIED 0x0000
+#define EFI_REG_CONTEXT_TYPE_MSR	  0x0001
+#define EFI_REG_CONTEXT_TYPE_IA32	  0x0002
+#define EFI_REG_CONTEXT_TYPE_X64	  0x0003
+#define EFI_REG_CONTEXT_TYPE_FXSAVE	  0x0004
+#define EFI_REG_CONTEXT_TYPE_DR_IA32	  0x0005
+#define EFI_REG_CONTEXT_TYPE_DR_X64	  0x0006
+#define EFI_REG_CONTEXT_TYPE_MEM_MAP	  0x0007
+///@}
+
+///
+/// IA32 Register State
+///
+typedef struct {
+	UINT32 Eax;
+	UINT32 Ebx;
+	UINT32 Ecx;
+	UINT32 Edx;
+	UINT32 Esi;
+	UINT32 Edi;
+	UINT32 Ebp;
+	UINT32 Esp;
+	UINT16 Cs;
+	UINT16 Ds;
+	UINT16 Ss;
+	UINT16 Es;
+	UINT16 Fs;
+	UINT16 Gs;
+	UINT32 Eflags;
+	UINT32 Eip;
+	UINT32 Cr0;
+	UINT32 Cr1;
+	UINT32 Cr2;
+	UINT32 Cr3;
+	UINT32 Cr4;
+	UINT32 Gdtr[2];
+	UINT32 Idtr[2];
+	UINT16 Ldtr;
+	UINT16 Tr;
+} EFI_CONTEXT_IA32_REGISTER_STATE;
+
+///
+/// X64 Register State
+///
+typedef struct {
+	UINT64 Rax;
+	UINT64 Rbx;
+	UINT64 Rcx;
+	UINT64 Rdx;
+	UINT64 Rsi;
+	UINT64 Rdi;
+	UINT64 Rbp;
+	UINT64 Rsp;
+	UINT64 R8;
+	UINT64 R9;
+	UINT64 R10;
+	UINT64 R11;
+	UINT64 R12;
+	UINT64 R13;
+	UINT64 R14;
+	UINT64 R15;
+	UINT16 Cs;
+	UINT16 Ds;
+	UINT16 Ss;
+	UINT16 Es;
+	UINT16 Fs;
+	UINT16 Gs;
+	UINT32 Resv1;
+	UINT64 Rflags;
+	UINT64 Rip;
+	UINT64 Cr0;
+	UINT64 Cr1;
+	UINT64 Cr2;
+	UINT64 Cr3;
+	UINT64 Cr4;
+	UINT64 Cr8;
+	UINT64 Gdtr[2];
+	UINT64 Idtr[2];
+	UINT16 Ldtr;
+	UINT16 Tr;
+} EFI_CONTEXT_X64_REGISTER_STATE;
+
+///
+/// The validation bit mask indicates each of the following field is in IA32/X64
+/// Processor Error Section.
+///
+typedef struct {
+	UINT64 ApicIdValid : 1;
+	UINT64 CpuIdInforValid : 1;
+	UINT64 ErrorInfoNum : 6;
+	UINT64 ContextNum : 6;
+	UINT64 Resv1 : 50;
+} EFI_IA32_X64_VALID_BITS;
+
+///
+/// Error Status Fields
+///
+typedef struct {
+	UINT64 Resv1 : 8;
+	UINT64 Type : 8;
+	UINT64 AddressSignal : 1; ///< Error in Address signals or in Address portion of transaction
+	UINT64 ControlSignal : 1; ///< Error in Control signals or in Control portion of transaction
+	UINT64 DataSignal : 1; ///< Error in Data signals or in Data portion of transaction
+	UINT64 DetectedByResponder : 1; ///< Error detected by responder
+	UINT64 DetectedByRequester : 1; ///< Error detected by requestor
+	UINT64 FirstError : 1; ///< First Error in the sequence - option field
+	UINT64 OverflowNotLogged : 1; ///< Additional errors were not logged due to lack of resources
+	UINT64 Resv2 : 41;
+} EFI_GENERIC_ERROR_STATUS;
+
+///
+/// CPER Generic Error Codes
+///
+#define CPER_GENERIC_ERROR_TYPES_KEYS                                          \
+	(int[])                                                                \
+	{                                                                      \
+		1, 16, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25,   \
+			26                                                     \
+	}
+#define CPER_GENERIC_ERROR_TYPES_VALUES                                        \
+	(const char *[])                                                       \
+	{                                                                      \
+		"ERR_INTERNAL", "ERR_BUS", "ERR_MEM", "ERR_TLB", "ERR_CACHE",  \
+			"ERR_FUNCTION", "ERR_SELFTEST", "ERR_FLOW", "ERR_MAP", \
+			"ERR_IMPROPER", "ERR_UNIMPL", "ERR_LOL",               \
+			"ERR_RESPONSE", "ERR_PARITY", "ERR_PROTOCOL",          \
+			"ERR_ERROR", "ERR_TIMEOUT", "ERR_POISONED"             \
+	}
+#define CPER_GENERIC_ERROR_TYPES_DESCRIPTIONS                                               \
+	(const char *[])                                                                    \
+	{                                                                                   \
+		"Error detected internal to the component.",                                \
+			"Error detected in the bus.",                                       \
+			"Storage error in memory (DRAM).",                                  \
+			"Storage error in TLB.", "Storage error in cache.",                 \
+			"Error in one or more functional units.",                           \
+			"Component failed self test.",                                      \
+			"Overflow or underflow of internal queue.",                         \
+			"Virtual address not found on IO-TLB or IO-PDIR.",                  \
+			"Improper access error.",                                           \
+			"Access to a memory address which is not mapped to any component.", \
+			"Loss of Lockstep error.",                                          \
+			"Response not associated with a request.",                          \
+			"Bus parity error (must also set the A, C, or D bits).",            \
+			"Detection of a protocol error.",                                   \
+			"Detection of a PATH_ERROR.",                                       \
+			"Bus operation timeout.",                                           \
+			"A read was issued to data that has been poisoned."                 \
+	}
+
+///
+/// Error Type
+///
+typedef enum {
+	///
+	/// General Internal errors
+	///
+	ErrorInternal = 1,
+	ErrorBus = 16,
+	///
+	/// Component Internal errors
+	///
+	ErrorMemStorage = 4, // Error in memory device
+	ErrorTlbStorage = 5, // TLB error in cache
+	ErrorCacheStorage = 6,
+	ErrorFunctionalUnit = 7,
+	ErrorSelftest = 8,
+	ErrorOverflow = 9,
+	///
+	/// Bus internal errors
+	///
+	ErrorVirtualMap = 17,
+	ErrorAccessInvalid = 18,   // Improper access
+	ErrorUnimplAccess = 19,	   // Unimplemented memory access
+	ErrorLossOfLockstep = 20,
+	ErrorResponseInvalid = 21, // Response not associated with request
+	ErrorParity = 22,
+	ErrorProtocol = 23,
+	ErrorPath = 24,	   // Detected path error
+	ErrorTimeout = 25, // Bus timeout
+	ErrorPoisoned = 26 // Read data poisoned
+} EFI_GENERIC_ERROR_STATUS_ERROR_TYPE;
+
+///
+/// Validation bit mask indicates which fields in the memory error record are valid
+/// in Memory Error section
+///@{
+#define EFI_PLATFORM_MEMORY_ERROR_STATUS_VALID		       BIT0
+#define EFI_PLATFORM_MEMORY_PHY_ADDRESS_VALID		       BIT1
+#define EFI_PLATFORM_MEMORY_PHY_ADDRESS_MASK_VALID	       BIT2
+#define EFI_PLATFORM_MEMORY_NODE_VALID			       BIT3
+#define EFI_PLATFORM_MEMORY_CARD_VALID			       BIT4
+#define EFI_PLATFORM_MEMORY_MODULE_VALID		       BIT5
+#define EFI_PLATFORM_MEMORY_BANK_VALID			       BIT6
+#define EFI_PLATFORM_MEMORY_DEVICE_VALID		       BIT7
+#define EFI_PLATFORM_MEMORY_ROW_VALID			       BIT8
+#define EFI_PLATFORM_MEMORY_COLUMN_VALID		       BIT9
+#define EFI_PLATFORM_MEMORY_BIT_POS_VALID		       BIT10
+#define EFI_PLATFORM_MEMORY_REQUESTOR_ID_VALID		       BIT11
+#define EFI_PLATFORM_MEMORY_RESPONDER_ID_VALID		       BIT12
+#define EFI_PLATFORM_MEMORY_TARGET_ID_VALID		       BIT13
+#define EFI_PLATFORM_MEMORY_ERROR_TYPE_VALID		       BIT14
+#define EFI_PLATFORM_MEMORY_ERROR_RANK_NUM_VALID	       BIT15
+#define EFI_PLATFORM_MEMORY_ERROR_CARD_HANDLE_VALID	       BIT16
+#define EFI_PLATFORM_MEMORY_ERROR_MODULE_HANDLE_VALID	       BIT17
+#define EFI_PLATFORM_MEMORY_ERROR_EXTENDED_ROW_BIT_16_17_VALID BIT18
+#define EFI_PLATFORM_MEMORY_ERROR_BANK_GROUP_VALID	       BIT19
+#define EFI_PLATFORM_MEMORY_ERROR_BANK_ADDRESS_VALID	       BIT20
+#define EFI_PLATFORM_MEMORY_ERROR_CHIP_IDENTIFICATION_VALID    BIT21
+///@}
+
+///
+/// Memory Error Type identifies the type of error that occurred in Memory
+/// Error section
+///@{
+#define EFI_PLATFORM_MEMORY_ERROR_UNKNOWN		 0x00
+#define EFI_PLATFORM_MEMORY_ERROR_NONE			 0x01
+#define EFI_PLATFORM_MEMORY_ERROR_SINGLEBIT_ECC		 0x02
+#define EFI_PLATFORM_MEMORY_ERROR_MLTIBIT_ECC		 0x03
+#define EFI_PLATFORM_MEMORY_ERROR_SINGLESYMBOLS_CHIPKILL 0x04
+#define EFI_PLATFORM_MEMORY_ERROR_MULTISYMBOL_CHIPKILL	 0x05
+#define EFI_PLATFORM_MEMORY_ERROR_MATER_ABORT		 0x06
+#define EFI_PLATFORM_MEMORY_ERROR_TARGET_ABORT		 0x07
+#define EFI_PLATFORM_MEMORY_ERROR_PARITY		 0x08
+#define EFI_PLATFORM_MEMORY_ERROR_WDT			 0x09
+#define EFI_PLATFORM_MEMORY_ERROR_INVALID_ADDRESS	 0x0A
+#define EFI_PLATFORM_MEMORY_ERROR_MIRROR_FAILED		 0x0B
+#define EFI_PLATFORM_MEMORY_ERROR_SPARING		 0x0C
+#define EFI_PLATFORM_MEMORY_ERROR_SCRUB_CORRECTED	 0x0D
+#define EFI_PLATFORM_MEMORY_ERROR_SCRUB_UNCORRECTED	 0x0E
+#define EFI_PLATFORM_MEMORY_ERROR_MEMORY_MAP_EVENT	 0x0F
+///@}
+
+///
+/// Memory Error Section
+///
+typedef struct {
+	UINT64 ValidFields;
+	EFI_GENERIC_ERROR_STATUS ErrorStatus;
+	UINT64 PhysicalAddress;	    // Error physical address
+	UINT64 PhysicalAddressMask; // Grnaularity
+	UINT16 Node;		    // Node #
+	UINT16 Card;
+	UINT16 ModuleRank;	    // Module or Rank#
+	UINT16 Bank;
+	UINT16 Device;
+	UINT16 Row;
+	UINT16 Column;
+	UINT16 BitPosition;
+	UINT64 RequestorId;
+	UINT64 ResponderId;
+	UINT64 TargetId;
+	UINT8 ErrorType;
+	UINT8 Extended;
+	UINT16 RankNum;
+	UINT16 CardHandle;
+	UINT16 ModuleHandle;
+} EFI_PLATFORM_MEMORY_ERROR_DATA;
+
+///
+/// Validation bit mask indicates which fields in the memory error record 2 are valid
+/// in Memory Error section 2
+///@{
+#define EFI_PLATFORM_MEMORY2_ERROR_STATUS_VALID	     BIT0
+#define EFI_PLATFORM_MEMORY2_PHY_ADDRESS_VALID	     BIT1
+#define EFI_PLATFORM_MEMORY2_PHY_ADDRESS_MASK_VALID  BIT2
+#define EFI_PLATFORM_MEMORY2_NODE_VALID		     BIT3
+#define EFI_PLATFORM_MEMORY2_CARD_VALID		     BIT4
+#define EFI_PLATFORM_MEMORY2_MODULE_VALID	     BIT5
+#define EFI_PLATFORM_MEMORY2_BANK_VALID		     BIT6
+#define EFI_PLATFORM_MEMORY2_DEVICE_VALID	     BIT7
+#define EFI_PLATFORM_MEMORY2_ROW_VALID		     BIT8
+#define EFI_PLATFORM_MEMORY2_COLUMN_VALID	     BIT9
+#define EFI_PLATFORM_MEMORY2_RANK_VALID		     BIT10
+#define EFI_PLATFORM_MEMORY2_BIT_POS_VALID	     BIT11
+#define EFI_PLATFORM_MEMORY2_CHIP_ID_VALID	     BIT12
+#define EFI_PLATFORM_MEMORY2_MEMORY_ERROR_TYPE_VALID BIT13
+#define EFI_PLATFORM_MEMORY2_STATUS_VALID	     BIT14
+#define EFI_PLATFORM_MEMORY2_REQUESTOR_ID_VALID	     BIT15
+#define EFI_PLATFORM_MEMORY2_RESPONDER_ID_VALID	     BIT16
+#define EFI_PLATFORM_MEMORY2_TARGET_ID_VALID	     BIT17
+#define EFI_PLATFORM_MEMORY2_CARD_HANDLE_VALID	     BIT18
+#define EFI_PLATFORM_MEMORY2_MODULE_HANDLE_VALID     BIT19
+#define EFI_PLATFORM_MEMORY2_BANK_GROUP_VALID	     BIT20
+#define EFI_PLATFORM_MEMORY2_BANK_ADDRESS_VALID	     BIT21
+///@}
+
+///
+/// Memory Error Type identifies the type of error that occurred in Memory
+/// Error section 2
+///@{
+#define EFI_PLATFORM_MEMORY2_ERROR_UNKNOWN		 0x00
+#define EFI_PLATFORM_MEMORY2_ERROR_NONE			 0x01
+#define EFI_PLATFORM_MEMORY2_ERROR_SINGLEBIT_ECC	 0x02
+#define EFI_PLATFORM_MEMORY2_ERROR_MLTIBIT_ECC		 0x03
+#define EFI_PLATFORM_MEMORY2_ERROR_SINGLESYMBOL_CHIPKILL 0x04
+#define EFI_PLATFORM_MEMORY2_ERROR_MULTISYMBOL_CHIPKILL	 0x05
+#define EFI_PLATFORM_MEMORY2_ERROR_MASTER_ABORT		 0x06
+#define EFI_PLATFORM_MEMORY2_ERROR_TARGET_ABORT		 0x07
+#define EFI_PLATFORM_MEMORY2_ERROR_PARITY		 0x08
+#define EFI_PLATFORM_MEMORY2_ERROR_WDT			 0x09
+#define EFI_PLATFORM_MEMORY2_ERROR_INVALID_ADDRESS	 0x0A
+#define EFI_PLATFORM_MEMORY2_ERROR_MIRROR_BROKEN	 0x0B
+#define EFI_PLATFORM_MEMORY2_ERROR_MEMORY_SPARING	 0x0C
+#define EFI_PLATFORM_MEMORY2_ERROR_SCRUB_CORRECTED	 0x0D
+#define EFI_PLATFORM_MEMORY2_ERROR_SCRUB_UNCORRECTED	 0x0E
+#define EFI_PLATFORM_MEMORY2_ERROR_MEMORY_MAP_EVENT	 0x0F
+///@}
+
+///
+/// Memory Error Section 2
+///
+typedef struct {
+	UINT64 ValidFields;
+	EFI_GENERIC_ERROR_STATUS ErrorStatus;
+	UINT64 PhysicalAddress;	    // Error physical address
+	UINT64 PhysicalAddressMask; // Grnaularity
+	UINT16 Node;		    // Node #
+	UINT16 Card;
+	UINT16 Module;		    // Module or Rank#
+	UINT16 Bank;
+	UINT32 Device;
+	UINT32 Row;
+	UINT32 Column;
+	UINT32 Rank;
+	UINT32 BitPosition;
+	UINT8 ChipId;
+	UINT8 MemErrorType;
+	UINT8 Status;
+	UINT8 Reserved;
+	UINT64 RequestorId;
+	UINT64 ResponderId;
+	UINT64 TargetId;
+	UINT32 CardHandle;
+	UINT32 ModuleHandle;
+} EFI_PLATFORM_MEMORY2_ERROR_DATA;
+
+///
+/// Validation bits mask indicates which of the following fields is valid
+/// in PCI Express Error Record.
+///@{
+#define EFI_PCIE_ERROR_PORT_TYPE_VALID	     BIT0
+#define EFI_PCIE_ERROR_VERSION_VALID	     BIT1
+#define EFI_PCIE_ERROR_COMMAND_STATUS_VALID  BIT2
+#define EFI_PCIE_ERROR_DEVICE_ID_VALID	     BIT3
+#define EFI_PCIE_ERROR_SERIAL_NO_VALID	     BIT4
+#define EFI_PCIE_ERROR_BRIDGE_CRL_STS_VALID  BIT5
+#define EFI_PCIE_ERROR_CAPABILITY_INFO_VALID BIT6
+#define EFI_PCIE_ERROR_AER_INFO_VALID	     BIT7
+///@}
+
+///
+/// PCIe Device/Port Type as defined in the PCI Express capabilities register
+///@{
+#define EFI_PCIE_ERROR_PORT_PCIE_ENDPOINT	 0x00000000
+#define EFI_PCIE_ERROR_PORT_PCI_ENDPOINT	 0x00000001
+#define EFI_PCIE_ERROR_PORT_ROOT_PORT		 0x00000004
+#define EFI_PCIE_ERROR_PORT_UPSWITCH_PORT	 0x00000005
+#define EFI_PCIE_ERROR_PORT_DOWNSWITCH_PORT	 0x00000006
+#define EFI_PCIE_ERROR_PORT_PCIE_TO_PCI_BRIDGE	 0x00000007
+#define EFI_PCIE_ERROR_PORT_PCI_TO_PCIE_BRIDGE	 0x00000008
+#define EFI_PCIE_ERROR_PORT_ROOT_INT_ENDPOINT	 0x00000009
+#define EFI_PCIE_ERROR_PORT_ROOT_EVENT_COLLECTOR 0x0000000A
+///@}
+
+///
+/// PCI Slot number
+///
+typedef struct {
+	UINT16 Resv1 : 3;
+	UINT16 Number : 13;
+} EFI_GENERIC_ERROR_PCI_SLOT;
+
+///
+/// PCIe Root Port PCI/bridge PCI compatible device number and
+/// bus number information to uniquely identify the root port or
+/// bridge. Default values for both the bus numbers is zero.
+///
+typedef struct {
+	UINT16 VendorId;
+	UINT16 DeviceId;
+	UINT8 ClassCode[3];
+	UINT8 Function;
+	UINT8 Device;
+	UINT16 Segment;
+	UINT8 PrimaryOrDeviceBus;
+	UINT8 SecondaryBus;
+	EFI_GENERIC_ERROR_PCI_SLOT Slot;
+	UINT8 Resv1;
+} EFI_GENERIC_ERROR_PCIE_DEV_BRIDGE_ID;
+
+///
+/// PCIe Capability Structure
+///
+typedef struct {
+	UINT8 PcieCap[60];
+} EFI_PCIE_ERROR_DATA_CAPABILITY;
+
+///
+/// PCIe Advanced Error Reporting Extended Capability Structure.
+///
+typedef struct {
+	UINT8 PcieAer[96];
+} EFI_PCIE_ERROR_DATA_AER;
+
+///
+/// PCI Express Error Record
+///
+typedef struct {
+	UINT64 ValidFields;
+	UINT32 PortType;
+	UINT32 Version;
+	UINT32 CommandStatus;
+	UINT32 Resv2;
+	EFI_GENERIC_ERROR_PCIE_DEV_BRIDGE_ID DevBridge;
+	UINT64 SerialNo;
+	UINT32 BridgeControlStatus;
+	EFI_PCIE_ERROR_DATA_CAPABILITY Capability;
+	EFI_PCIE_ERROR_DATA_AER AerInfo;
+} EFI_PCIE_ERROR_DATA;
+
+///
+/// Validation bits Indicates which of the following fields is valid
+/// in PCI/PCI-X Bus Error Section.
+///@{
+#define EFI_PCI_PCIX_BUS_ERROR_STATUS_VALID	  BIT0
+#define EFI_PCI_PCIX_BUS_ERROR_TYPE_VALID	  BIT1
+#define EFI_PCI_PCIX_BUS_ERROR_BUS_ID_VALID	  BIT2
+#define EFI_PCI_PCIX_BUS_ERROR_BUS_ADDRESS_VALID  BIT3
+#define EFI_PCI_PCIX_BUS_ERROR_BUS_DATA_VALID	  BIT4
+#define EFI_PCI_PCIX_BUS_ERROR_COMMAND_VALID	  BIT5
+#define EFI_PCI_PCIX_BUS_ERROR_REQUESTOR_ID_VALID BIT6
+#define EFI_PCI_PCIX_BUS_ERROR_COMPLETER_ID_VALID BIT7
+#define EFI_PCI_PCIX_BUS_ERROR_TARGET_ID_VALID	  BIT8
+///@}
+
+///
+/// PCI Bus Error Type in PCI/PCI-X Bus Error Section
+///@{
+#define EFI_PCI_PCIX_BUS_ERROR_UNKNOWN		  0x0000
+#define EFI_PCI_PCIX_BUS_ERROR_DATA_PARITY	  0x0001
+#define EFI_PCI_PCIX_BUS_ERROR_SYSTEM		  0x0002
+#define EFI_PCI_PCIX_BUS_ERROR_MASTER_ABORT	  0x0003
+#define EFI_PCI_PCIX_BUS_ERROR_BUS_TIMEOUT	  0x0004
+#define EFI_PCI_PCIX_BUS_ERROR_MASTER_DATA_PARITY 0x0005
+#define EFI_PCI_PCIX_BUS_ERROR_ADDRESS_PARITY	  0x0006
+#define EFI_PCI_PCIX_BUS_ERROR_COMMAND_PARITY	  0x0007
+///@}
+
+///
+/// PCI/PCI-X Bus Error Section
+///
+typedef struct {
+	UINT64 ValidFields;
+	EFI_GENERIC_ERROR_STATUS ErrorStatus;
+	UINT16 Type;
+	UINT16 BusId;
+	UINT32 Resv2;
+	UINT64 BusAddress;
+	UINT64 BusData;
+	UINT64 BusCommand;
+	UINT64 RequestorId;
+	UINT64 ResponderId;
+	UINT64 TargetId;
+} EFI_PCI_PCIX_BUS_ERROR_DATA;
+
+///
+/// Validation bits Indicates which of the following fields is valid
+/// in PCI/PCI-X Component Error Section.
+///@{
+#define EFI_PCI_PCIX_DEVICE_ERROR_STATUS_VALID	      BIT0
+#define EFI_PCI_PCIX_DEVICE_ERROR_ID_INFO_VALID	      BIT1
+#define EFI_PCI_PCIX_DEVICE_ERROR_MEM_NUM_VALID	      BIT2
+#define EFI_PCI_PCIX_DEVICE_ERROR_IO_NUM_VALID	      BIT3
+#define EFI_PCI_PCIX_DEVICE_ERROR_REG_DATA_PAIR_VALID BIT4
+///@}
+
+///
+/// PCI/PCI-X Device Identification Information
+///
+typedef struct {
+	UINT16 VendorId;
+	UINT16 DeviceId;
+	UINT8 ClassCode[3];
+	UINT8 Function;
+	UINT8 Device;
+	UINT8 Bus;
+	UINT8 Segment;
+	UINT8 Resv1;
+	UINT32 Resv2;
+} EFI_GENERIC_ERROR_PCI_DEVICE_ID;
+
+///
+/// Identifies the type of firmware error record
+///@{
+#define EFI_FIRMWARE_ERROR_TYPE_IPF_SAL	  0x00
+#define EFI_FIRMWARE_ERROR_TYPE_SOC_TYPE1 0x01
+#define EFI_FIRMWARE_ERROR_TYPE_SOC_TYPE2 0x02
+///@}
+
+///
+/// Firmware Error Record Section
+///
+typedef struct {
+	UINT8 ErrorType;
+	UINT8 Revision;
+	UINT8 Resv1[6];
+	UINT64 RecordId;
+	EFI_GUID RecordIdGuid;
+} EFI_FIRMWARE_ERROR_DATA;
+
+///
+/// Fault Reason in DMAr Generic Error Section
+///@{
+#define EFI_DMA_FAULT_REASON_TABLE_ENTRY_NOT_PRESENT	       0x01
+#define EFI_DMA_FAULT_REASON_TABLE_ENTRY_INVALID	       0x02
+#define EFI_DMA_FAULT_REASON_ACCESS_MAPPING_TABLE_ERROR	       0x03
+#define EFI_DMA_FAULT_REASON_RESV_BIT_ERROR_IN_MAPPING_TABLE   0x04
+#define EFI_DMA_FAULT_REASON_ACCESS_ADDR_OUT_OF_SPACE	       0x05
+#define EFI_DMA_FAULT_REASON_INVALID_ACCESS		       0x06
+#define EFI_DMA_FAULT_REASON_INVALID_REQUEST		       0x07
+#define EFI_DMA_FAULT_REASON_ACCESS_TRANSLATE_TABLE_ERROR      0x08
+#define EFI_DMA_FAULT_REASON_RESV_BIT_ERROR_IN_TRANSLATE_TABLE 0x09
+#define EFI_DMA_FAULT_REASON_INVALID_COMMAOND		       0x0A
+#define EFI_DMA_FAULT_REASON_ACCESS_COMMAND_BUFFER_ERROR       0x0B
+///@}
+
+///
+/// DMA access type in DMAr Generic Error Section
+///@{
+#define EFI_DMA_ACCESS_TYPE_READ  0x00
+#define EFI_DMA_ACCESS_TYPE_WRITE 0x01
+///@}
+
+///
+/// DMA address type in DMAr Generic Error Section
+///@{
+#define EFI_DMA_ADDRESS_UNTRANSLATED 0x00
+#define EFI_DMA_ADDRESS_TRANSLATION  0x01
+///@}
+
+///
+/// Architecture type in DMAr Generic Error Section
+///@{
+#define EFI_DMA_ARCH_TYPE_VT	0x01
+#define EFI_DMA_ARCH_TYPE_IOMMU 0x02
+///@}
+
+///
+/// DMAr Generic Error Section
+///
+typedef struct {
+	UINT16 RequesterId;
+	UINT16 SegmentNumber;
+	UINT8 FaultReason;
+	UINT8 AccessType;
+	UINT8 AddressType;
+	UINT8 ArchType;
+	UINT64 DeviceAddr;
+	UINT8 Resv1[16];
+} EFI_DMAR_GENERIC_ERROR_DATA;
+
+///
+/// Intel VT for Directed I/O specific DMAr Errors
+///
+typedef struct {
+	UINT8 Version;
+	UINT8 Revision;
+	UINT8 OemId[6];
+	UINT64 Capability;
+	UINT64 CapabilityEx;
+	UINT32 GlobalCommand;
+	UINT32 GlobalStatus;
+	UINT32 FaultStatus;
+	UINT8 Resv1[12];
+	UINT64 FaultRecord[2];
+	UINT64 RootEntry[2];
+	UINT64 ContextEntry[2];
+	UINT64 PteL6;
+	UINT64 PteL5;
+	UINT64 PteL4;
+	UINT64 PteL3;
+	UINT64 PteL2;
+	UINT64 PteL1;
+} EFI_DIRECTED_IO_DMAR_ERROR_DATA;
+
+///
+/// IOMMU specific DMAr Errors
+///
+typedef struct {
+	UINT8 Revision;
+	UINT8 Resv1[7];
+	UINT64 Control;
+	UINT64 Status;
+	UINT8 Resv2[8];
+	UINT64 EventLogEntry[2];
+	UINT8 Resv3[16];
+	UINT64 DeviceTableEntry[4];
+	UINT64 PteL6;
+	UINT64 PteL5;
+	UINT64 PteL4;
+	UINT64 PteL3;
+	UINT64 PteL2;
+	UINT64 PteL1;
+} EFI_IOMMU_DMAR_ERROR_DATA;
+
+extern EFI_GUID gEfiEventNotificationTypeCmcGuid;
+extern EFI_GUID gEfiEventNotificationTypeCpeGuid;
+extern EFI_GUID gEfiEventNotificationTypeMceGuid;
+extern EFI_GUID gEfiEventNotificationTypePcieGuid;
+extern EFI_GUID gEfiEventNotificationTypeInitGuid;
+extern EFI_GUID gEfiEventNotificationTypeNmiGuid;
+extern EFI_GUID gEfiEventNotificationTypeBootGuid;
+extern EFI_GUID gEfiEventNotificationTypeDmarGuid;
+extern EFI_GUID gEfiEventNotificationTypeSeaGuid;
+extern EFI_GUID gEfiEventNotificationTypeSeiGuid;
+extern EFI_GUID gEfiEventNotificationTypePeiGuid;
+extern EFI_GUID gEfiEventNotificationTypeCxlGuid;
+extern EFI_GUID gEfiProcessorGenericErrorSectionGuid;
+extern EFI_GUID gEfiProcessorSpecificErrorSectionGuid;
+extern EFI_GUID gEfiIa32X64ProcessorErrorSectionGuid;
+extern EFI_GUID gEfiIpfProcessorErrorSectionGuid;
+extern EFI_GUID gEfiArmProcessorErrorSectionGuid;
+extern EFI_GUID gEfiPlatformMemoryErrorSectionGuid;
+extern EFI_GUID gEfiPlatformMemoryError2SectionGuid;
+extern EFI_GUID gEfiPcieErrorSectionGuid;
+extern EFI_GUID gEfiFirmwareErrorSectionGuid;
+extern EFI_GUID gEfiPciBusErrorSectionGuid;
+extern EFI_GUID gEfiPciDevErrorSectionGuid;
+extern EFI_GUID gEfiDMArGenericErrorSectionGuid;
+extern EFI_GUID gEfiDirectedIoDMArErrorSectionGuid;
+extern EFI_GUID gEfiIommuDMArErrorSectionGuid;
+extern EFI_GUID gEfiCcixPerLogErrorSectionGuid;
+extern EFI_GUID gEfiCxlProtocolErrorSectionGuid;
+extern EFI_GUID gEfiCxlGeneralMediaErrorSectionGuid;
+extern EFI_GUID gEfiCxlDramEventErrorSectionGuid;
+extern EFI_GUID gEfiCxlMemoryModuleErrorSectionGuid;
+extern EFI_GUID gEfiCxlPhysicalSwitchErrorSectionGuid;
+extern EFI_GUID gEfiCxlVirtualSwitchErrorSectionGuid;
+extern EFI_GUID gEfiCxlMldPortErrorSectionGuid;
+
+#if defined(MDE_CPU_IA32) || defined(MDE_CPU_X64)
+///
+/// IA32 and x64 Specific definitions.
+///
+
+extern EFI_GUID gEfiIa32X64ErrorTypeCacheCheckGuid;
+extern EFI_GUID gEfiIa32X64ErrorTypeTlbCheckGuid;
+extern EFI_GUID gEfiIa32X64ErrorTypeBusCheckGuid;
+extern EFI_GUID gEfiIa32X64ErrorTypeMsCheckGuid;
+
+#endif
+
+///
+/// NVIDIA Error Record Section
+///
+typedef struct {
+	UINT64 Address;
+	UINT64 Value;
+} EFI_NVIDIA_REGISTER_DATA;
+
+typedef struct {
+	CHAR8 Signature[16];
+	UINT16 ErrorType;
+	UINT16 ErrorInstance;
+	UINT8 Severity;
+	UINT8 Socket;
+	UINT8 NumberRegs;
+	UINT8 Reserved;
+	UINT64 InstanceBase;
+	// Keep this at the end of this struct
+	// and allocate based on NumberRegs
+#ifndef __cplusplus
+	EFI_NVIDIA_REGISTER_DATA Register[] LIBCPER_CC_COUNTED_BY(NumberRegs);
+#endif
+} EFI_NVIDIA_ERROR_DATA;
+
+extern EFI_GUID gEfiNvidiaErrorSectionGuid;
+
+///
+/// Ampere Error Record Section
+///
+typedef struct {
+	UINT16 TypeId;
+	UINT16 SubtypeId;
+	UINT32 InstanceId;
+} __attribute__((packed)) EFI_AMPERE_ERROR_DATA;
+
+extern EFI_GUID gEfiAmpereErrorSectionGuid;
+
+#pragma pack(pop)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/base64.h b/include/libcper/base64.h
new file mode 100644
index 0000000..78bf1c1
--- /dev/null
+++ b/include/libcper/base64.h
@@ -0,0 +1,26 @@
+#ifndef CPER_BASE64_H
+#define CPER_BASE64_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <libcper/BaseTypes.h>
+
+/**
+ * base64_decode
+ * Caller is responsible for freeing the returned buffer.
+ */
+UINT8 *base64_decode(const CHAR8 *src, INT32 len, INT32 *out_len);
+
+/**
+ * base64_encode
+ * Caller is responsible for freeing the returned buffer.
+ */
+CHAR8 *base64_encode(const UINT8 *src, INT32 len, INT32 *out_len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/common-utils.h b/include/libcper/common-utils.h
new file mode 100644
index 0000000..2528f59
--- /dev/null
+++ b/include/libcper/common-utils.h
@@ -0,0 +1,19 @@
+#ifndef CPER_LIB_COMMON_UTILS_H
+#define CPER_LIB_COMMON_UTILS_H
+
+#include <libcper/BaseTypes.h>
+
+int bcd_to_int(UINT8 bcd);
+UINT8 int_to_bcd(int value);
+
+#if defined __has_attribute
+#if __has_attribute(counted_by)
+#define LIBCPER_CC_COUNTED_BY(x) __attribute__((counted_by(x)))
+#endif
+#endif
+
+#ifndef LIBCPER_CC_COUNTED_BY
+#define LIBCPER_CC_COUNTED_BY(x)
+#endif
+
+#endif
diff --git a/include/libcper/cper-parse-str.h b/include/libcper/cper-parse-str.h
new file mode 100644
index 0000000..95db594
--- /dev/null
+++ b/include/libcper/cper-parse-str.h
@@ -0,0 +1,18 @@
+#ifndef CPER_PARSE_STR_H
+#define CPER_PARSE_STR_H
+
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+char *cperbuf_to_str_ir(const unsigned char *cper, size_t size);
+char *cperbuf_single_section_to_str_ir(const unsigned char *cper_section,
+				       size_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/cper-parse.h b/include/libcper/cper-parse.h
new file mode 100644
index 0000000..4b966f1
--- /dev/null
+++ b/include/libcper/cper-parse.h
@@ -0,0 +1,49 @@
+#ifndef CPER_PARSE_H
+#define CPER_PARSE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <json.h>
+#include <stdio.h>
+
+#define CPER_HEADER_VALID_BITFIELD_NAMES                                       \
+	(const char *[])                                                       \
+	{                                                                      \
+		"platformIDValid", "timestampValid", "partitionIDValid"        \
+	}
+#define CPER_SECTION_DESCRIPTOR_VALID_BITFIELD_NAMES                           \
+	(const char *[])                                                       \
+	{                                                                      \
+		"fruIDValid", "fruStringValid"                                 \
+	}
+#define CPER_SECTION_DESCRIPTOR_FLAGS_BITFIELD_NAMES                           \
+	(const char *[])                                                       \
+	{                                                                      \
+		"primary", "containmentWarning", "reset",                      \
+			"errorThresholdExceeded", "resourceNotAccessible",     \
+			"latentError", "propagated", "overflow"                \
+	}
+#define CPER_HEADER_FLAG_TYPES_KEYS                                            \
+	(int[])                                                                \
+	{                                                                      \
+		1, 2, 4                                                        \
+	}
+#define CPER_HEADER_FLAG_TYPES_VALUES                                          \
+	(const char *[])                                                       \
+	{                                                                      \
+		"HW_ERROR_FLAGS_RECOVERED", "HW_ERROR_FLAGS_PREVERR",          \
+			"HW_ERROR_FLAGS_SIMULATED"                             \
+	}
+
+json_object *cper_to_ir(FILE *cper_file);
+json_object *cper_single_section_to_ir(FILE *cper_section_file);
+void ir_to_cper(json_object *ir, FILE *out);
+void ir_single_section_to_cper(json_object *ir, FILE *out);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/cper-utils.h b/include/libcper/cper-utils.h
new file mode 100644
index 0000000..603a4d7
--- /dev/null
+++ b/include/libcper/cper-utils.h
@@ -0,0 +1,54 @@
+#ifndef CPER_UTILS_H
+#define CPER_UTILS_H
+
+#define GUID_STRING_LENGTH 48
+#define TIMESTAMP_LENGTH   24
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <libcper/common-utils.h>
+#include <libcper/Cper.h>
+#include <json.h>
+
+json_object *
+cper_generic_error_status_to_ir(EFI_GENERIC_ERROR_STATUS *error_status);
+void ir_generic_error_status_to_cper(
+	json_object *error_status, EFI_GENERIC_ERROR_STATUS *error_status_cper);
+json_object *uniform_struct_to_ir(UINT32 *start, int len, const char *names[]);
+json_object *uniform_struct64_to_ir(UINT64 *start, int len,
+				    const char *names[]);
+void ir_to_uniform_struct(json_object *ir, UINT32 *start, int len,
+			  const char *names[]);
+void ir_to_uniform_struct64(json_object *ir, UINT64 *start, int len,
+			    const char *names[]);
+json_object *integer_to_readable_pair(UINT64 value, int len, const int keys[],
+				      const char *values[],
+				      const char *default_value);
+json_object *integer_to_readable_pair_with_desc(int value, int len,
+						const int keys[],
+						const char *values[],
+						const char *descriptions[],
+						const char *default_value);
+UINT64 readable_pair_to_integer(json_object *pair);
+json_object *bitfield_to_ir(UINT64 bitfield, int num_fields,
+			    const char *names[]);
+UINT64 ir_to_bitfield(json_object *ir, int num_fields, const char *names[]);
+json_object *uint64_array_to_ir_array(UINT64 *array, int len);
+json_object *revision_to_ir(UINT16 revision);
+const char *severity_to_string(UINT32 severity);
+void timestamp_to_string(char *out, EFI_ERROR_TIME_STAMP *timestamp);
+void string_to_timestamp(EFI_ERROR_TIME_STAMP *out, const char *timestamp);
+void guid_to_string(char *out, EFI_GUID *guid);
+void string_to_guid(EFI_GUID *out, const char *guid);
+int guid_equal(EFI_GUID *a, EFI_GUID *b);
+
+//The available severity types for CPER.
+extern const char *CPER_SEVERITY_TYPES[4];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/generator/cper-generate.h b/include/libcper/generator/cper-generate.h
new file mode 100644
index 0000000..97f5ea6
--- /dev/null
+++ b/include/libcper/generator/cper-generate.h
@@ -0,0 +1,18 @@
+#ifndef CPER_GENERATE_H
+#define CPER_GENERATE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdio.h>
+#include <libcper/BaseTypes.h>
+
+void generate_cper_record(char **types, UINT16 num_sections, FILE *out);
+void generate_single_section_record(char *type, FILE *out);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/generator/gen-utils.h b/include/libcper/generator/gen-utils.h
new file mode 100644
index 0000000..8588cc1
--- /dev/null
+++ b/include/libcper/generator/gen-utils.h
@@ -0,0 +1,29 @@
+#ifndef CPER_GEN_UTILS_H
+#define CPER_GEN_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdlib.h>
+#include <libcper/BaseTypes.h>
+#include <libcper/common-utils.h>
+
+#define CPER_ERROR_TYPES_KEYS                                                  \
+	(int[])                                                                \
+	{                                                                      \
+		1, 16, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25,   \
+			26                                                     \
+	}
+
+size_t generate_random_section(void **location, size_t size);
+UINT8 *generate_random_bytes(size_t size);
+void init_random();
+void create_valid_error_section(UINT8 *start);
+UINT8 int_to_bcd(int value);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/generator/sections/gen-section.h b/include/libcper/generator/sections/gen-section.h
new file mode 100644
index 0000000..53c25c8
--- /dev/null
+++ b/include/libcper/generator/sections/gen-section.h
@@ -0,0 +1,44 @@
+#ifndef GEN_SECTIONS_H
+#define GEN_SECTIONS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdlib.h>
+#include <libcper/Cper.h>
+
+//Section generator function predefinitions.
+size_t generate_section_generic(void **location);
+size_t generate_section_ia32x64(void **location);
+size_t generate_section_arm(void **location);
+size_t generate_section_memory(void **location);
+size_t generate_section_memory2(void **location);
+size_t generate_section_pcie(void **location);
+size_t generate_section_pci_bus(void **location);
+size_t generate_section_pci_dev(void **location);
+size_t generate_section_firmware(void **location);
+size_t generate_section_dmar_generic(void **location);
+size_t generate_section_dmar_vtd(void **location);
+size_t generate_section_dmar_iommu(void **location);
+size_t generate_section_ccix_per(void **location);
+size_t generate_section_cxl_protocol(void **location);
+size_t generate_section_cxl_component(void **location);
+size_t generate_section_nvidia(void **location);
+size_t generate_section_ampere(void **location);
+
+//Definition structure for a single CPER section generator.
+typedef struct {
+	EFI_GUID *Guid;
+	const char *ShortName;
+	size_t (*Generate)(void **);
+} CPER_GENERATOR_DEFINITION;
+
+extern CPER_GENERATOR_DEFINITION generator_definitions[];
+extern const size_t generator_definitions_len;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/json-schema.h b/include/libcper/json-schema.h
new file mode 100644
index 0000000..7dbbe48
--- /dev/null
+++ b/include/libcper/json-schema.h
@@ -0,0 +1,24 @@
+#ifndef CPER_JSON_SCHEMA_H
+#define CPER_JSON_SCHEMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <json.h>
+
+#define JSON_SCHEMA_VERSION    "https://json-schema.org/draft/2020-12/schema"
+#define JSON_ERROR_MSG_MAX_LEN 512
+
+int validate_schema(json_object *schema, char *schema_directory,
+		    json_object *object, char *error_message);
+int validate_schema_from_file(const char *schema_file, json_object *object,
+			      char *error_message);
+void validate_schema_debug_enable();
+void validate_schema_debug_disable();
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/meson.build b/include/libcper/meson.build
new file mode 100644
index 0000000..44c42ba
--- /dev/null
+++ b/include/libcper/meson.build
@@ -0,0 +1,12 @@
+install_headers(
+    'BaseTypes.h',
+    'Cper.h',
+    'cper-parse.h',
+    'cper-parse-str.h',
+    'cper-utils.h',
+    'common-utils.h',
+    subdir: 'libcper',
+    preserve_path : true
+)
+
+install_headers('generator/cper-generate.h', subdir: 'libcper/generator')
\ No newline at end of file
diff --git a/include/libcper/sections/cper-section-ampere.h b/include/libcper/sections/cper-section-ampere.h
new file mode 100644
index 0000000..3d3f744
--- /dev/null
+++ b/include/libcper/sections/cper-section-ampere.h
@@ -0,0 +1,10 @@
+#ifndef CPER_SECTION_AMPERE_H
+#define CPER_SECTION_AMPERE_H
+
+#include <json.h>
+#include <libcper/Cper.h>
+
+json_object *cper_section_ampere_to_ir(void *section);
+void ir_section_ampere_to_cper(json_object *section, FILE *out);
+
+#endif
diff --git a/include/libcper/sections/cper-section-arm.h b/include/libcper/sections/cper-section-arm.h
new file mode 100644
index 0000000..0580801
--- /dev/null
+++ b/include/libcper/sections/cper-section-arm.h
@@ -0,0 +1,470 @@
+#ifndef CPER_SECTION_ARM_H
+#define CPER_SECTION_ARM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <json.h>
+#include <libcper/Cper.h>
+
+#define ARM_ERROR_VALID_BITFIELD_NAMES                                         \
+	(const char *[])                                                       \
+	{                                                                      \
+		"mpidrValid", "errorAffinityLevelValid", "runningStateValid",  \
+			"vendorSpecificInfoValid"                              \
+	}
+#define ARM_ERROR_INFO_ENTRY_VALID_BITFIELD_NAMES                              \
+	(const char *[])                                                       \
+	{                                                                      \
+		"multipleErrorValid", "flagsValid", "errorInformationValid",   \
+			"virtualFaultAddressValid",                            \
+			"physicalFaultAddressValid"                            \
+	}
+#define ARM_ERROR_INFO_ENTRY_FLAGS_NAMES                                       \
+	(const char *[])                                                       \
+	{                                                                      \
+		"firstErrorCaptured", "lastErrorCaptured", "propagated",       \
+			"overflow"                                             \
+	}
+#define ARM_CACHE_TLB_ERROR_VALID_BITFIELD_NAMES                               \
+	(const char *[])                                                       \
+	{                                                                      \
+		"transactionTypeValid", "operationValid", "levelValid",        \
+			"processorContextCorruptValid", "correctedValid",      \
+			"precisePCValid", "restartablePCValid"                 \
+	}
+#define ARM_BUS_ERROR_VALID_BITFIELD_NAMES                                     \
+	(const char *[])                                                       \
+	{                                                                      \
+		"transactionTypeValid", "operationValid", "levelValid",        \
+			"processorContextCorruptValid", "correctedValid",      \
+			"precisePCValid", "restartablePCValid",                \
+			"participationTypeValid", "timedOutValid",             \
+			"addressSpaceValid", "memoryAttributesValid",          \
+			"accessModeValid"                                      \
+	}
+#define ARM_ERROR_TRANSACTION_TYPES_KEYS                                       \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 2                                                        \
+	}
+#define ARM_ERROR_TRANSACTION_TYPES_VALUES                                     \
+	(const char *[])                                                       \
+	{                                                                      \
+		"Instruction", "Data Access", "Generic"                        \
+	}
+#define ARM_ERROR_INFO_ENTRY_INFO_TYPES_KEYS                                   \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 2, 3                                                     \
+	}
+#define ARM_ERROR_INFO_ENTRY_INFO_TYPES_VALUES                                 \
+	(const char *[])                                                       \
+	{                                                                      \
+		"Cache Error", "TLB Error", "Bus Error",                       \
+			"Micro-Architectural Error"                            \
+	}
+#define ARM_CACHE_BUS_OPERATION_TYPES_KEYS                                     \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10                               \
+	}
+#define ARM_CACHE_BUS_OPERATION_TYPES_VALUES                                   \
+	(const char *[])                                                       \
+	{                                                                      \
+		"Generic Error", "Generic Read", "Generic Write", "Data Read", \
+			"Data Write", "Instruction Fetch", "Prefetch",         \
+			"Eviction", "Snooping", "Snooped", "Management"        \
+	}
+#define ARM_TLB_OPERATION_TYPES_KEYS                                           \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 2, 3, 4, 5, 6, 7, 8                                      \
+	}
+#define ARM_TLB_OPERATION_TYPES_VALUES                                         \
+	(const char *[])                                                       \
+	{                                                                      \
+		"Generic Error", "Generic Read", "Generic Write", "Data Read", \
+			"Data Write", "Instruction Fetch", "Prefetch",         \
+			"Local Management Operation",                          \
+			"External Management Operation"                        \
+	}
+#define ARM_BUS_PARTICIPATION_TYPES_KEYS                                       \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 2, 3                                                     \
+	}
+#define ARM_BUS_PARTICIPATION_TYPES_VALUES                                     \
+	(const char *[])                                                       \
+	{                                                                      \
+		"Local Processor Originated Request",                          \
+			"Local Processor Responded to Request",                \
+			"Local Processor Observed", "Generic"                  \
+	}
+#define ARM_BUS_ADDRESS_SPACE_TYPES_KEYS                                       \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 3                                                        \
+	}
+#define ARM_BUS_ADDRESS_SPACE_TYPES_VALUES                                     \
+	(const char *[])                                                       \
+	{                                                                      \
+		"External Memory Access", "Internal Memory Access",            \
+			"Device Memory Access"                                 \
+	}
+#define ARM_PROCESSOR_INFO_REGISTER_CONTEXT_TYPES_KEYS                         \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 2, 3, 4, 5, 6, 7, 8                                      \
+	}
+#define ARM_PROCESSOR_INFO_REGISTER_CONTEXT_TYPES_VALUES                       \
+	(const char *[])                                                       \
+	{                                                                      \
+		"AArch32 General Purpose Registers",                           \
+			"AArch32 EL1 Context Registers",                       \
+			"AArch32 EL2 Context Registers",                       \
+			"AArch32 Secure Context Registers",                    \
+			"AArch64 General Purpose Registers",                   \
+			"AArch64 EL1 Context Registers",                       \
+			"AArch64 EL2 Context Registers",                       \
+			"AArch64 EL3 Context Registers",                       \
+			"Miscellaneous System Register Structure"              \
+	}
+#define ARM_AARCH32_GPR_NAMES                                                  \
+	(const char *[])                                                       \
+	{                                                                      \
+		"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",    \
+			"r10", "r11", "r12", "r13_sp", "r14_lr", "r15_pc"      \
+	}
+#define ARM_AARCH32_EL1_REGISTER_NAMES                                         \
+	(const char *[])                                                       \
+	{                                                                      \
+		"dfar", "dfsr", "ifar", "isr", "mair0", "mair1", "midr",       \
+			"mpidr", "nmrr", "prrr", "sctlr_ns", "spsr",           \
+			"spsr_abt", "spsr_fiq", "spsr_irq", "spsr_svc",        \
+			"spsr_und", "tpidrprw", "tpidruro", "tpidrurw",        \
+			"ttbcr", "ttbr0", "ttbr1", "dacr"                      \
+	}
+#define ARM_AARCH32_EL2_REGISTER_NAMES                                         \
+	(const char *[])                                                       \
+	{                                                                      \
+		"elr_hyp", "hamair0", "hamair1", "hcr", "hcr2", "hdfar",       \
+			"hifar", "hpfar", "hsr", "htcr", "htpidr", "httbr",    \
+			"spsr_hyp", "vtcr", "vttbr", "dacr32_el2"              \
+	}
+#define ARM_AARCH32_SECURE_REGISTER_NAMES                                      \
+	(const char *[])                                                       \
+	{                                                                      \
+		"sctlr_s", "spsr_mon"                                          \
+	}
+#define ARM_AARCH64_GPR_NAMES                                                  \
+	(const char *[])                                                       \
+	{                                                                      \
+		"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9",    \
+			"x10", "x11", "x12", "x13", "x14", "x15", "x16",       \
+			"x17", "x18", "x19", "x20", "x21", "x22", "x23",       \
+			"x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp"  \
+	}
+#define ARM_AARCH64_EL1_REGISTER_NAMES                                         \
+	(const char *[])                                                       \
+	{                                                                      \
+		"elr_el1", "esr_el1", "far_el1", "isr_el1", "mair_el1",        \
+			"midr_el1", "mpidr_el1", "sctlr_el1", "sp_el0",        \
+			"sp_el1", "spsr_el1", "tcr_el1", "tpidr_el0",          \
+			"tpidr_el1", "tpidrro_el0", "ttbr0_el1", "ttbr1_el1"   \
+	}
+#define ARM_AARCH64_EL2_REGISTER_NAMES                                         \
+	(const char *[])                                                       \
+	{                                                                      \
+		"elr_el2", "esr_el2", "far_el2", "hacr_el2", "hcr_el2",        \
+			"hpfar_el2", "mair_el2", "sctlr_el2", "sp_el2",        \
+			"spsr_el2", "tcr_el2", "tpidr_el2", "ttbr0_el2",       \
+			"vtcr_el2", "vttbr_el2"                                \
+	}
+#define ARM_AARCH64_EL3_REGISTER_NAMES                                         \
+	(const char *[])                                                       \
+	{                                                                      \
+		"elr_el3", "esr_el3", "far_el3", "mair_el3", "sctlr_el3",      \
+			"sp_el3", "spsr_el3", "tcr_el3", "tpidr_el3",          \
+			"ttbr0_el3"                                            \
+	}
+
+///
+/// ARM Processor Error Record
+///
+typedef struct {
+	UINT32 ValidFields;
+	UINT16 ErrInfoNum;
+	UINT16 ContextInfoNum;
+	UINT32 SectionLength;
+	UINT32 ErrorAffinityLevel;
+	UINT64 MPIDR_EL1;
+	UINT64 MIDR_EL1;
+	UINT32 RunningState;
+	UINT32 PsciState;
+} __attribute__((packed, aligned(1))) EFI_ARM_ERROR_RECORD;
+
+///
+/// ARM Processor Error Information Structure
+///
+#define ARM_ERROR_INFORMATION_TYPE_CACHE     0
+#define ARM_ERROR_INFORMATION_TYPE_TLB	     1
+#define ARM_ERROR_INFORMATION_TYPE_BUS	     2
+#define ARM_ERROR_INFORMATION_TYPE_MICROARCH 3
+
+typedef struct {
+	UINT64 ValidationBits : 16;
+	UINT64 TransactionType : 2;
+	UINT64 Operation : 4;
+	UINT64 Level : 3;
+	UINT64 ProcessorContextCorrupt : 1;
+	UINT64 Corrected : 1;
+	UINT64 PrecisePC : 1;
+	UINT64 RestartablePC : 1;
+	UINT64 Reserved : 34;
+} EFI_ARM_CACHE_ERROR_STRUCTURE;
+
+typedef struct {
+	UINT64 ValidationBits : 16;
+	UINT64 TransactionType : 2;
+	UINT64 Operation : 4;
+	UINT64 Level : 3;
+	UINT64 ProcessorContextCorrupt : 1;
+	UINT64 Corrected : 1;
+	UINT64 PrecisePC : 1;
+	UINT64 RestartablePC : 1;
+	UINT64 Reserved : 34;
+} EFI_ARM_TLB_ERROR_STRUCTURE;
+
+typedef struct {
+	UINT64 ValidationBits : 16;
+	UINT64 TransactionType : 2;
+	UINT64 Operation : 4;
+	UINT64 Level : 3;
+	UINT64 ProcessorContextCorrupt : 1;
+	UINT64 Corrected : 1;
+	UINT64 PrecisePC : 1;
+	UINT64 RestartablePC : 1;
+	UINT64 ParticipationType : 2;
+	UINT64 TimeOut : 1;
+	UINT64 AddressSpace : 2;
+	UINT64 MemoryAddressAttributes : 8;
+	UINT64 AccessMode : 1;
+	UINT64 Reserved : 19;
+} EFI_ARM_BUS_ERROR_STRUCTURE;
+
+typedef union {
+	UINT64 Value;
+	EFI_ARM_CACHE_ERROR_STRUCTURE CacheError;
+	EFI_ARM_TLB_ERROR_STRUCTURE TlbError;
+	EFI_ARM_BUS_ERROR_STRUCTURE BusError;
+} EFI_ARM_ERROR_INFORMATION_STRUCTURE;
+
+typedef struct {
+	UINT8 Version;
+	UINT8 Length;
+	UINT16 ValidationBits;
+	UINT8 Type;
+	UINT16 MultipleError;
+	UINT8 Flags;
+	EFI_ARM_ERROR_INFORMATION_STRUCTURE ErrorInformation;
+	UINT64 VirtualFaultAddress;
+	UINT64 PhysicalFaultAddress;
+} __attribute__((packed, aligned(1))) EFI_ARM_ERROR_INFORMATION_ENTRY;
+
+///
+/// ARM Processor Context Information Structure
+///
+typedef struct {
+	UINT16 Version;
+	UINT16 RegisterContextType;
+	UINT32 RegisterArraySize;
+} __attribute__((packed, aligned(1))) EFI_ARM_CONTEXT_INFORMATION_HEADER;
+
+///
+/// ARM Processor Context Register Types
+///
+#define EFI_ARM_CONTEXT_TYPE_AARCH32_GPR    0
+#define EFI_ARM_CONTEXT_TYPE_AARCH32_EL1    1
+#define EFI_ARM_CONTEXT_TYPE_AARCH32_EL2    2
+#define EFI_ARM_CONTEXT_TYPE_AARCH32_SECURE 3
+#define EFI_ARM_CONTEXT_TYPE_AARCH64_GPR    4
+#define EFI_ARM_CONTEXT_TYPE_AARCH64_EL1    5
+#define EFI_ARM_CONTEXT_TYPE_AARCH64_EL2    6
+#define EFI_ARM_CONTEXT_TYPE_AARCH64_EL3    7
+#define EFI_ARM_CONTEXT_TYPE_MISC	    8
+
+typedef struct {
+	UINT32 R0;
+	UINT32 R1;
+	UINT32 R2;
+	UINT32 R3;
+	UINT32 R4;
+	UINT32 R5;
+	UINT32 R6;
+	UINT32 R7;
+	UINT32 R8;
+	UINT32 R9;
+	UINT32 R10;
+	UINT32 R11;
+	UINT32 R12;
+	UINT32 R13_sp;
+	UINT32 R14_lr;
+	UINT32 R15_pc;
+} EFI_ARM_V8_AARCH32_GPR;
+
+typedef struct {
+	UINT32 Dfar;
+	UINT32 Dfsr;
+	UINT32 Ifar;
+	UINT32 Isr;
+	UINT32 Mair0;
+	UINT32 Mair1;
+	UINT32 Midr;
+	UINT32 Mpidr;
+	UINT32 Nmrr;
+	UINT32 Prrr;
+	UINT32 Sctlr_Ns;
+	UINT32 Spsr;
+	UINT32 Spsr_Abt;
+	UINT32 Spsr_Fiq;
+	UINT32 Spsr_Irq;
+	UINT32 Spsr_Svc;
+	UINT32 Spsr_Und;
+	UINT32 Tpidrprw;
+	UINT32 Tpidruro;
+	UINT32 Tpidrurw;
+	UINT32 Ttbcr;
+	UINT32 Ttbr0;
+	UINT32 Ttbr1;
+	UINT32 Dacr;
+} EFI_ARM_AARCH32_EL1_CONTEXT_REGISTERS;
+
+typedef struct {
+	UINT32 Elr_Hyp;
+	UINT32 Hamair0;
+	UINT32 Hamair1;
+	UINT32 Hcr;
+	UINT32 Hcr2;
+	UINT32 Hdfar;
+	UINT32 Hifar;
+	UINT32 Hpfar;
+	UINT32 Hsr;
+	UINT32 Htcr;
+	UINT32 Htpidr;
+	UINT32 Httbr;
+	UINT32 Spsr_Hyp;
+	UINT32 Vtcr;
+	UINT32 Vttbr;
+	UINT32 Dacr32_El2;
+} EFI_ARM_AARCH32_EL2_CONTEXT_REGISTERS;
+
+typedef struct {
+	UINT32 Sctlr_S;
+	UINT32 Spsr_Mon;
+} EFI_ARM_AARCH32_SECURE_CONTEXT_REGISTERS;
+
+typedef struct {
+	UINT64 X0;
+	UINT64 X1;
+	UINT64 X2;
+	UINT64 X3;
+	UINT64 X4;
+	UINT64 X5;
+	UINT64 X6;
+	UINT64 X7;
+	UINT64 X8;
+	UINT64 X9;
+	UINT64 X10;
+	UINT64 X11;
+	UINT64 X12;
+	UINT64 X13;
+	UINT64 X14;
+	UINT64 X15;
+	UINT64 X16;
+	UINT64 X17;
+	UINT64 X18;
+	UINT64 X19;
+	UINT64 X20;
+	UINT64 X21;
+	UINT64 X22;
+	UINT64 X23;
+	UINT64 X24;
+	UINT64 X25;
+	UINT64 X26;
+	UINT64 X27;
+	UINT64 X28;
+	UINT64 X29;
+	UINT64 X30;
+	UINT64 Sp;
+} EFI_ARM_V8_AARCH64_GPR;
+
+typedef struct {
+	UINT64 Elr_El1;
+	UINT64 Esr_El1;
+	UINT64 Far_El1;
+	UINT64 Isr_El1;
+	UINT64 Mair_El1;
+	UINT64 Midr_El1;
+	UINT64 Mpidr_El1;
+	UINT64 Sctlr_El1;
+	UINT64 Sp_El0;
+	UINT64 Sp_El1;
+	UINT64 Spsr_El1;
+	UINT64 Tcr_El1;
+	UINT64 Tpidr_El0;
+	UINT64 Tpidr_El1;
+	UINT64 Tpidrro_El0;
+	UINT64 Ttbr0_El1;
+	UINT64 Ttbr1_El1;
+} EFI_ARM_AARCH64_EL1_CONTEXT_REGISTERS;
+
+typedef struct {
+	UINT64 Elr_El2;
+	UINT64 Esr_El2;
+	UINT64 Far_El2;
+	UINT64 Hacr_El2;
+	UINT64 Hcr_El2;
+	UINT64 Hpfar_El2;
+	UINT64 Mair_El2;
+	UINT64 Sctlr_El2;
+	UINT64 Sp_El2;
+	UINT64 Spsr_El2;
+	UINT64 Tcr_El2;
+	UINT64 Tpidr_El2;
+	UINT64 Ttbr0_El2;
+	UINT64 Vtcr_El2;
+	UINT64 Vttbr_El2;
+} EFI_ARM_AARCH64_EL2_CONTEXT_REGISTERS;
+
+typedef struct {
+	UINT64 Elr_El3;
+	UINT64 Esr_El3;
+	UINT64 Far_El3;
+	UINT64 Mair_El3;
+	UINT64 Sctlr_El3;
+	UINT64 Sp_El3;
+	UINT64 Spsr_El3;
+	UINT64 Tcr_El3;
+	UINT64 Tpidr_El3;
+	UINT64 Ttbr0_El3;
+} EFI_ARM_AARCH64_EL3_CONTEXT_REGISTERS;
+
+typedef struct {
+	UINT64 MrsOp2 : 3;
+	UINT64 MrsCrm : 4;
+	UINT64 MrsCrn : 4;
+	UINT64 MrsOp1 : 3;
+	UINT64 MrsO0 : 1;
+	UINT64 Value : 64;
+} EFI_ARM_MISC_CONTEXT_REGISTER;
+
+json_object *cper_section_arm_to_ir(void *section);
+void ir_section_arm_to_cper(json_object *section, FILE *out);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/sections/cper-section-ccix-per.h b/include/libcper/sections/cper-section-ccix-per.h
new file mode 100644
index 0000000..80f7ae4
--- /dev/null
+++ b/include/libcper/sections/cper-section-ccix-per.h
@@ -0,0 +1,35 @@
+#ifndef CPER_SECTION_CCIX_PER_H
+#define CPER_SECTION_CCIX_PER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <json.h>
+#include <libcper/Cper.h>
+
+#define CCIX_PER_ERROR_VALID_BITFIELD_NAMES                                    \
+	(const char *[])                                                       \
+	{                                                                      \
+		"ccixSourceIDValid", "ccixPortIDValid", "ccixPERLogValid"      \
+	}
+
+///
+/// CCIX PER Log Error Section
+///
+typedef struct {
+	UINT32 Length;
+	UINT64 ValidBits;
+	UINT8 CcixSourceId;
+	UINT8 CcixPortId;
+	UINT16 Reserved;
+} __attribute__((packed, aligned(1))) EFI_CCIX_PER_LOG_DATA;
+
+json_object *cper_section_ccix_per_to_ir(void *section);
+void ir_section_ccix_per_to_cper(json_object *section, FILE *out);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/sections/cper-section-cxl-component.h b/include/libcper/sections/cper-section-cxl-component.h
new file mode 100644
index 0000000..2e60294
--- /dev/null
+++ b/include/libcper/sections/cper-section-cxl-component.h
@@ -0,0 +1,47 @@
+#ifndef CPER_SECTION_CXL_COMPONENT_H
+#define CPER_SECTION_CXL_COMPONENT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <json.h>
+#include <libcper/Cper.h>
+
+#define CXL_COMPONENT_ERROR_VALID_BITFIELD_NAMES                               \
+	(const char *[])                                                       \
+	{                                                                      \
+		"deviceIDValid", "deviceSerialValid",                          \
+			"cxlComponentEventLogValid"                            \
+	}
+
+///
+/// CXL Generic Component Error Section
+///
+typedef struct {
+	UINT64 VendorId : 16;
+	UINT64 DeviceId : 16;
+	UINT64 FunctionNumber : 8;
+	UINT64 DeviceNumber : 8;
+	UINT64 BusNumber : 8;
+	UINT64 SegmentNumber : 16;
+	UINT64 Resv1 : 3;
+	UINT64 SlotNumber : 13;
+	UINT64 Resv2 : 8;
+} __attribute__((packed, aligned(1))) EFI_CXL_DEVICE_ID_INFO;
+
+typedef struct {
+	UINT32 Length;
+	UINT64 ValidBits;
+	EFI_CXL_DEVICE_ID_INFO DeviceId;
+	UINT64 DeviceSerial;
+} __attribute__((packed, aligned(1))) EFI_CXL_COMPONENT_EVENT_HEADER;
+
+json_object *cper_section_cxl_component_to_ir(void *section);
+void ir_section_cxl_component_to_cper(json_object *section, FILE *out);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/sections/cper-section-cxl-protocol.h b/include/libcper/sections/cper-section-cxl-protocol.h
new file mode 100644
index 0000000..28e745b
--- /dev/null
+++ b/include/libcper/sections/cper-section-cxl-protocol.h
@@ -0,0 +1,78 @@
+#ifndef CPER_SECTION_CXL_PROTOCOL_H
+#define CPER_SECTION_CXL_PROTOCOL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <json.h>
+#include <libcper/Cper.h>
+
+#define CXL_PROTOCOL_ERROR_VALID_BITFIELD_NAMES                                \
+	(const char *[])                                                       \
+	{                                                                      \
+		"cxlAgentTypeValid", "cxlAgentAddressValid", "deviceIDValid",  \
+			"deviceSerialValid", "capabilityStructureValid",       \
+			"cxlDVSECValid", "cxlErrorLogValid"                    \
+	}
+#define CXL_PROTOCOL_ERROR_AGENT_TYPES_KEYS                                    \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1                                                           \
+	}
+#define CXL_PROTOCOL_ERROR_AGENT_TYPES_VALUES                                  \
+	(const char *[])                                                       \
+	{                                                                      \
+		"CXL 1.1 Device", "CXL 1.1 Host Downstream Port"               \
+	}
+#define CXL_PROTOCOL_ERROR_DEVICE_AGENT		      0
+#define CXL_PROTOCOL_ERROR_HOST_DOWNSTREAM_PORT_AGENT 1
+
+///
+/// CXL Protocol Error Section
+///
+typedef struct {
+	UINT64 VendorId : 16;
+	UINT64 DeviceId : 16;
+	UINT64 SubsystemVendorId : 16;
+	UINT64 SubsystemDeviceId : 16;
+	UINT64 ClassCode : 16;
+	UINT64 Reserved1 : 3;
+	UINT64 SlotNumber : 13;
+	UINT64 Reserved2 : 32;
+} EFI_CXL_DEVICE_ID;
+
+typedef struct {
+	UINT64 FunctionNumber : 8;
+	UINT64 DeviceNumber : 8;
+	UINT64 BusNumber : 8;
+	UINT64 SegmentNumber : 16;
+	UINT64 Reserved : 24;
+} EFI_CXL_DEVICE_AGENT_ADDRESS;
+
+typedef union {
+	EFI_CXL_DEVICE_AGENT_ADDRESS
+	DeviceAddress; //Active when the agent is a CXL1.1 device in CxlAgentType.
+	UINT64 PortRcrbBaseAddress; //Active when the agent is a CXL1.1 host downstream port in CxlAgentType.
+} EFI_CXL_AGENT_ADDRESS;
+
+typedef struct {
+	UINT64 ValidBits;
+	UINT64 CxlAgentType;
+	EFI_CXL_AGENT_ADDRESS CxlAgentAddress;
+	EFI_CXL_DEVICE_ID DeviceId;
+	UINT64 DeviceSerial;
+	EFI_PCIE_ERROR_DATA_CAPABILITY CapabilityStructure;
+	UINT16 CxlDvsecLength;
+	UINT16 CxlErrorLogLength;
+	UINT32 Reserved;
+} __attribute__((packed, aligned(1))) EFI_CXL_PROTOCOL_ERROR_DATA;
+
+json_object *cper_section_cxl_protocol_to_ir(void *section);
+void ir_section_cxl_protocol_to_cper(json_object *section, FILE *out);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/sections/cper-section-dmar-generic.h b/include/libcper/sections/cper-section-dmar-generic.h
new file mode 100644
index 0000000..5a6dd4f
--- /dev/null
+++ b/include/libcper/sections/cper-section-dmar-generic.h
@@ -0,0 +1,79 @@
+#ifndef CPER_SECTION_DMAR_GENERIC_H
+#define CPER_SECTION_DMAR_GENERIC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <json.h>
+#include <libcper/Cper.h>
+
+#define DMAR_GENERIC_ERROR_FAULT_REASON_TYPES_KEYS                             \
+	(int[])                                                                \
+	{                                                                      \
+		0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xA, 0xB          \
+	}
+#define DMAR_GENERIC_ERROR_FAULT_REASON_TYPES_VALUES                           \
+	(const char *[])                                                       \
+	{                                                                      \
+		"DMT Entry Missing", "DMT Entry Invalid", "DMT Access Error",  \
+			"DMT Reserved Bit Invalid",                            \
+			"DMA Address Out of Bounds", "Invalid Read/Write",     \
+			"Invalid Device Request", "ATT Access Error",          \
+			"ATT Reserved Bit Invalid", "Illegal Command",         \
+			"Command Buffer Access Error"                          \
+	}
+#define DMAR_GENERIC_ERROR_FAULT_REASON_TYPES_DESCRIPTIONS                                                   \
+	(const char *[])                                                                                     \
+	{                                                                                                    \
+		"Domain mapping table entry is not present.",                                                \
+			"Invalid domain mapping table entry.",                                               \
+			"DMAr unit's attempt to access the domain mapping table resulted in an error.",      \
+			"Reserved bit set to non-zero value in the domain mapping table.",                   \
+			"DMA request to access an address beyond the device address width.",                 \
+			"Invalid read or write access.",                                                     \
+			"Invalid device request.",                                                           \
+			"DMAr unit's attempt to access the address translation table resulted in an error.", \
+			"Reserved bit set to non-zero value in the address translation table.",              \
+			"Illegal command error.",                                                            \
+			"DMAr unit's attempt to access the command buffer resulted in an error."             \
+	}
+#define DMAR_GENERIC_ERROR_ACCESS_TYPES_KEYS                                   \
+	(int[])                                                                \
+	{                                                                      \
+		0x0, 0x1                                                       \
+	}
+#define DMAR_GENERIC_ERROR_ACCESS_TYPES_VALUES                                 \
+	(const char *[])                                                       \
+	{                                                                      \
+		"DMA Write", "DMA Read"                                        \
+	}
+#define DMAR_GENERIC_ERROR_ADDRESS_TYPES_KEYS                                  \
+	(int[])                                                                \
+	{                                                                      \
+		0x0, 0x1                                                       \
+	}
+#define DMAR_GENERIC_ERROR_ADDRESS_TYPES_VALUES                                \
+	(const char *[])                                                       \
+	{                                                                      \
+		"Untranslated Request", "Translation Request"                  \
+	}
+#define DMAR_GENERIC_ERROR_ARCH_TYPES_KEYS                                     \
+	(int[])                                                                \
+	{                                                                      \
+		0x0, 0x1                                                       \
+	}
+#define DMAR_GENERIC_ERROR_ARCH_TYPES_VALUES                                   \
+	(const char *[])                                                       \
+	{                                                                      \
+		"VT-d", "IOMMU"                                                \
+	}
+
+json_object *cper_section_dmar_generic_to_ir(void *section);
+void ir_section_dmar_generic_to_cper(json_object *section, FILE *out);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/sections/cper-section-dmar-iommu.h b/include/libcper/sections/cper-section-dmar-iommu.h
new file mode 100644
index 0000000..6b2aa6f
--- /dev/null
+++ b/include/libcper/sections/cper-section-dmar-iommu.h
@@ -0,0 +1,18 @@
+#ifndef CPER_SECTION_DMAR_IOMMU_H
+#define CPER_SECTION_DMAR_IOMMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <json.h>
+#include <libcper/Cper.h>
+
+json_object *cper_section_dmar_iommu_to_ir(void *section);
+void ir_section_dmar_iommu_to_cper(json_object *section, FILE *out);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/sections/cper-section-dmar-vtd.h b/include/libcper/sections/cper-section-dmar-vtd.h
new file mode 100644
index 0000000..5c3c876
--- /dev/null
+++ b/include/libcper/sections/cper-section-dmar-vtd.h
@@ -0,0 +1,44 @@
+#ifndef CPER_SECTION_DMAR_VTD_H
+#define CPER_SECTION_DMAR_VTD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <json.h>
+#include <libcper/Cper.h>
+
+#define VTD_FAULT_RECORD_TYPES_KEYS                                            \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1                                                           \
+	}
+#define VTD_FAULT_RECORD_TYPES_VALUES                                          \
+	(const char *[])                                                       \
+	{                                                                      \
+		"Write Request", "Read/AtomicOp Request"                       \
+	}
+
+typedef struct {
+	UINT64 Resv1 : 12;
+	UINT64 FaultInformation : 52;
+	UINT64 SourceIdentifier : 16;
+	UINT64 Resv2 : 13;
+	UINT64 PrivelegeModeRequested : 1;
+	UINT64 ExecutePermissionRequested : 1;
+	UINT64 PasidPresent : 1;
+	UINT64 FaultReason : 8;
+	UINT64 PasidValue : 20;
+	UINT64 AddressType : 2;
+	UINT64 Type : 1;
+	UINT64 Resv3 : 1;
+} EFI_VTD_FAULT_RECORD;
+
+json_object *cper_section_dmar_vtd_to_ir(void *section);
+void ir_section_dmar_vtd_to_cper(json_object *section, FILE *out);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/sections/cper-section-firmware.h b/include/libcper/sections/cper-section-firmware.h
new file mode 100644
index 0000000..ea1e19a
--- /dev/null
+++ b/include/libcper/sections/cper-section-firmware.h
@@ -0,0 +1,31 @@
+#ifndef CPER_SECTION_FIRMWARE_H
+#define CPER_SECTION_FIRMWARE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <json.h>
+#include <libcper/Cper.h>
+
+#define FIRMWARE_ERROR_RECORD_TYPES_KEYS                                       \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 2                                                        \
+	}
+#define FIRMWARE_ERROR_RECORD_TYPES_VALUES                                     \
+	(const char *[])                                                       \
+	{                                                                      \
+		"IPF SAL Error Record",                                        \
+			"SOC Firmware Error Record (Type1 Legacy)",            \
+			"SOC Firmware Error Record (Type2)"                    \
+	}
+
+json_object *cper_section_firmware_to_ir(void *section);
+void ir_section_firmware_to_cper(json_object *section, FILE *out);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/sections/cper-section-generic.h b/include/libcper/sections/cper-section-generic.h
new file mode 100644
index 0000000..6ec3ba4
--- /dev/null
+++ b/include/libcper/sections/cper-section-generic.h
@@ -0,0 +1,76 @@
+#ifndef CPER_SECTION_GENERIC_H
+#define CPER_SECTION_GENERIC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <json.h>
+#include <libcper/Cper.h>
+
+#define GENERIC_PROC_TYPES_KEYS                                                \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 2                                                        \
+	}
+#define GENERIC_PROC_TYPES_VALUES                                              \
+	(const char *[])                                                       \
+	{                                                                      \
+		"IA32/X64", "IA64", "ARM"                                      \
+	}
+#define GENERIC_ISA_TYPES_KEYS                                                 \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 2, 3, 4                                                  \
+	}
+#define GENERIC_ISA_TYPES_VALUES                                               \
+	(const char *[])                                                       \
+	{                                                                      \
+		"IA32", "IA64", "X64", "ARM A32/T32", "ARM A64"                \
+	}
+#define GENERIC_ERROR_TYPES_KEYS                                               \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 2, 4, 8                                                  \
+	}
+#define GENERIC_ERROR_TYPES_VALUES                                             \
+	(const char *[])                                                       \
+	{                                                                      \
+		"Unknown", "Cache Error", "TLB Error", "Bus Error",            \
+			"Micro-Architectural Error"                            \
+	}
+#define GENERIC_OPERATION_TYPES_KEYS                                           \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 2, 3                                                     \
+	}
+#define GENERIC_OPERATION_TYPES_VALUES                                         \
+	(const char *[])                                                       \
+	{                                                                      \
+		"Unknown or Generic", "Data Read", "Data Write",               \
+			"Instruction Execution"                                \
+	}
+#define GENERIC_VALIDATION_BITFIELD_NAMES                                      \
+	(const char *[])                                                       \
+	{                                                                      \
+		"processorTypeValid", "processorISAValid",                     \
+			"processorErrorTypeValid", "operationValid",           \
+			"flagsValid", "levelValid", "cpuVersionValid",         \
+			"cpuBrandInfoValid", "cpuIDValid",                     \
+			"targetAddressValid", "requestorIDValid",              \
+			"responderIDValid", "instructionIPValid"               \
+	}
+#define GENERIC_FLAGS_BITFIELD_NAMES                                           \
+	(const char *[])                                                       \
+	{                                                                      \
+		"restartable", "preciseIP", "overflow", "corrected"            \
+	}
+
+json_object *cper_section_generic_to_ir(void *section);
+void ir_section_generic_to_cper(json_object *section, FILE *out);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/sections/cper-section-ia32x64.h b/include/libcper/sections/cper-section-ia32x64.h
new file mode 100644
index 0000000..4da2517
--- /dev/null
+++ b/include/libcper/sections/cper-section-ia32x64.h
@@ -0,0 +1,119 @@
+#ifndef CPER_SECTION_IA32X64_H
+#define CPER_SECTION_IA32X64_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <json.h>
+#include <libcper/Cper.h>
+
+#define IA32X64_PROCESSOR_ERROR_VALID_BITFIELD_NAMES                           \
+	(const char *[])                                                       \
+	{                                                                      \
+		"checkInfoValid", "targetAddressIDValid", "requestorIDValid",  \
+			"responderIDValid", "instructionPointerValid"          \
+	}
+#define IA32X64_CHECK_INFO_VALID_BITFIELD_NAMES                                \
+	(const char *[])                                                       \
+	{                                                                      \
+		"transactionTypeValid", "operationValid", "levelValid",        \
+			"processorContextCorruptValid", "uncorrectedValid",    \
+			"preciseIPValid", "restartableIPValid",                \
+			"overflowValid", "participationTypeValid",             \
+			"timedOutValid", "addressSpaceValid"                   \
+	}
+#define IA32X64_CHECK_INFO_MS_CHECK_VALID_BITFIELD_NAMES                       \
+	(const char *[])                                                       \
+	{                                                                      \
+		"errorTypeValid", "processorContextCorruptValid",              \
+			"uncorrectedValid", "preciseIPValid",                  \
+			"restartableIPValid", "overflowValid"                  \
+	}
+#define IA32X64_CHECK_INFO_TRANSACTION_TYPES_KEYS                              \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 2                                                        \
+	}
+#define IA32X64_CHECK_INFO_TRANSACTION_TYPES_VALUES                            \
+	(const char *[])                                                       \
+	{                                                                      \
+		"Instruction", "Data Access", "Generic"                        \
+	}
+#define IA32X64_CHECK_INFO_OPERATION_TYPES_KEYS                                \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 2, 3, 4, 5, 6, 7, 8                                      \
+	}
+#define IA32X64_CHECK_INFO_OPERATION_TYPES_VALUES                              \
+	(const char *[])                                                       \
+	{                                                                      \
+		"Generic Error", "Generic Read", "Generic Write", "Data Read", \
+			"Data Write", "Instruction Fetch", "Prefetch",         \
+			"Eviction", "Snoop"                                    \
+	}
+#define IA32X64_BUS_CHECK_INFO_PARTICIPATION_TYPES_KEYS                        \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 2, 3                                                     \
+	}
+#define IA32X64_BUS_CHECK_INFO_PARTICIPATION_TYPES_VALUES                      \
+	(const char *[])                                                       \
+	{                                                                      \
+		"Local processor originated request",                          \
+			"Local processor responded to request",                \
+			"Local processor observed", "Generic"                  \
+	}
+#define IA32X64_BUS_CHECK_INFO_ADDRESS_SPACE_TYPES_KEYS                        \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 2, 3                                                     \
+	}
+#define IA32X64_BUS_CHECK_INFO_ADDRESS_SPACE_TYPES_VALUES                      \
+	(const char *[])                                                       \
+	{                                                                      \
+		"Memory Access", "Reserved", "I/O", "Other Transaction"        \
+	}
+#define IA32X64_MS_CHECK_INFO_ERROR_TYPES_KEYS                                 \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 2, 3, 4, 5                                               \
+	}
+#define IA32X64_MS_CHECK_INFO_ERROR_TYPES_VALUES                               \
+	(const char *[])                                                       \
+	{                                                                      \
+		"No Error", "Unclassified", "Microcode ROM Parity Error",      \
+			"External Error", "FRC Error", "Internal Unclassified" \
+	}
+#define IA32X64_REGISTER_CONTEXT_TYPES_KEYS                                    \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 2, 3, 4, 5, 6, 7                                         \
+	}
+#define IA32X64_REGISTER_CONTEXT_TYPES_VALUES                                  \
+	(const char *[])                                                       \
+	{                                                                      \
+		"Unclassified Data", "MSR Registers",                          \
+			"32-bit Mode Execution Context",                       \
+			"64-bit Mode Execution Context", "FXSave Context",     \
+			"32-bit Mode Debug Registers",                         \
+			"64-bit Mode Debug Registers",                         \
+			"Memory Mapper Registers"                              \
+	}
+
+typedef struct {
+	UINT64 Eax;
+	UINT64 Ebx;
+	UINT64 Ecx;
+	UINT64 Edx;
+	UINT64 Reserved[2];
+} EFI_IA32_X64_CPU_ID;
+
+json_object *cper_section_ia32x64_to_ir(void *section);
+void ir_section_ia32x64_to_cper(json_object *section, FILE *out);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/sections/cper-section-ipf.h b/include/libcper/sections/cper-section-ipf.h
new file mode 100644
index 0000000..95b3012
--- /dev/null
+++ b/include/libcper/sections/cper-section-ipf.h
@@ -0,0 +1,80 @@
+#ifndef CPER_SECTION_IPF_H
+#define CPER_SECTION_IPF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <json.h>
+#include <libcper/Cper.h>
+
+#define IPF_MOD_ERROR_VALID_BITFIELD_NAMES                                     \
+	(const char *[])                                                       \
+	{                                                                      \
+		"checkInfoValid", "requestorIdentifierValid",                  \
+			"responderIdentifierValid", "targetIdentifierValid",   \
+			"preciseIPValid"                                       \
+	}
+#define IPF_PSI_STATIC_INFO_VALID_BITFIELD_NAMES                               \
+	(const char *[])                                                       \
+	{                                                                      \
+		"minstateValid", "brValid", "crValid", "arValid", "rrValid",   \
+			"frValid"                                              \
+	}
+
+///
+/// IPF Error Record Section
+/// Defined as according to B.2.3 of the ItaniumTM Processor Family System Abstraction Layer (SAL) Specification.
+///
+typedef struct {
+	UINT64 ProcErrorMapValid : 1;
+	UINT64 ProcStateParameterValid : 1;
+	UINT64 ProcCrLidValid : 1;
+	UINT64 PsiStaticStructValid : 1;
+	UINT64 CacheCheckNum : 4;
+	UINT64 TlbCheckNum : 4;
+	UINT64 BusCheckNum : 4;
+	UINT64 RegFileCheckNum : 4;
+	UINT64 MsCheckNum : 4;
+	UINT64 CpuIdInfoValid : 1;
+	UINT64 Reserved : 39;
+} EPI_IPF_ERROR_VALID_BITS;
+
+typedef struct {
+	EPI_IPF_ERROR_VALID_BITS ValidBits;
+	UINT64 ProcErrorMap;
+	UINT64 ProcStateParameter;
+	UINT64 ProcCrLid;
+} EFI_IPF_ERROR_INFO_HEADER;
+
+typedef struct {
+	UINT64 ValidBits;
+	UINT64 ModCheckInfo;
+	UINT64 ModTargetId;
+	UINT64 ModRequestorId; //NOTE: The Intel Itanium specification contains a typo which makes the order
+	UINT64 ModResponderId; // of these two fields undefined. This is a best guess and could be wrong.
+	UINT64 ModPreciseIp;
+} EFI_IPF_MOD_ERROR_INFO;
+
+typedef struct {
+	UINT8 CpuIdInfo[40];
+	UINT8 Reserved1[8];
+} EFI_IPF_CPU_INFO;
+
+typedef struct {
+	UINT64 ValidBits;
+	UINT8 MinimalSaveStateInfo[1024];
+	UINT64 Brs[8];
+	UINT64 Crs[128];
+	UINT64 Ars[128];
+	UINT64 Rrs[8];
+	UINT64 Frs[256];
+} EFI_IPF_PSI_STATIC;
+
+json_object *cper_section_ipf_to_ir(void *section);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/sections/cper-section-memory.h b/include/libcper/sections/cper-section-memory.h
new file mode 100644
index 0000000..71991f2
--- /dev/null
+++ b/include/libcper/sections/cper-section-memory.h
@@ -0,0 +1,65 @@
+#ifndef CPER_SECTION_MEMORY_H
+#define CPER_SECTION_MEMORY_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <json.h>
+#include <libcper/Cper.h>
+
+#define MEMORY_ERROR_VALID_BITFIELD_NAMES                                      \
+	(const char *[])                                                       \
+	{                                                                      \
+		"errorStatusValid", "physicalAddressValid",                    \
+			"physicalAddressMaskValid", "nodeValid", "cardValid",  \
+			"moduleValid", "bankValid", "deviceValid", "rowValid", \
+			"columnValid", "bitPositionValid",                     \
+			"platformRequestorIDValid",                            \
+			"platformResponderIDValid",                            \
+			"memoryPlatformTargetValid", "memoryErrorTypeValid",   \
+			"rankNumberValid", "cardHandleValid",                  \
+			"moduleHandleValid", "extendedRowBitsValid",           \
+			"bankGroupValid", "bankAddressValid",                  \
+			"chipIdentificationValid"                              \
+	}
+#define MEMORY_ERROR_TYPES_KEYS                                                \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15           \
+	}
+#define MEMORY_ERROR_TYPES_VALUES                                              \
+	(const char *[])                                                       \
+	{                                                                      \
+		"Unknown", "No Error", "Single-bit ECC", "Multi-bit ECC",      \
+			"Single-symbol ChipKill ECC",                          \
+			"Multi-symbol ChipKill ECC", "Master Abort",           \
+			"Target Abort", "Parity Error", "Watchdog Timeout",    \
+			"Invalid Address", "Mirror Broken", "Memory Sparing",  \
+			"Scrub Corrected Error", "Scrub Uncorrected Error",    \
+			"Physical Memory Map-out Event"                        \
+	}
+#define MEMORY_ERROR_2_VALID_BITFIELD_NAMES                                    \
+	(const char *[])                                                       \
+	{                                                                      \
+		"errorStatusValid", "physicalAddressValid",                    \
+			"physicalAddressMaskValid", "nodeValid", "cardValid",  \
+			"moduleValid", "bankValid", "deviceValid", "rowValid", \
+			"columnValid", "rankValid", "bitPositionValid",        \
+			"chipIDValid", "memoryErrorTypeValid", "statusValid",  \
+			"requestorIDValid", "responderIDValid",                \
+			"targetIDValid", "cardHandleValid",                    \
+			"moduleHandleValid", "bankGroupValid",                 \
+			"bankAddressValid"                                     \
+	}
+
+json_object *cper_section_platform_memory_to_ir(void *section);
+json_object *cper_section_platform_memory2_to_ir(void *section);
+void ir_section_memory_to_cper(json_object *section, FILE *out);
+void ir_section_memory2_to_cper(json_object *section, FILE *out);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/sections/cper-section-nvidia.h b/include/libcper/sections/cper-section-nvidia.h
new file mode 100644
index 0000000..b5bb594
--- /dev/null
+++ b/include/libcper/sections/cper-section-nvidia.h
@@ -0,0 +1,18 @@
+#ifndef CPER_SECTION_NVIDIA_H
+#define CPER_SECTION_NVIDIA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <json.h>
+#include <libcper/Cper.h>
+
+json_object *cper_section_nvidia_to_ir(void *section);
+void ir_section_nvidia_to_cper(json_object *section, FILE *out);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/sections/cper-section-pci-bus.h b/include/libcper/sections/cper-section-pci-bus.h
new file mode 100644
index 0000000..34fd368
--- /dev/null
+++ b/include/libcper/sections/cper-section-pci-bus.h
@@ -0,0 +1,41 @@
+#ifndef CPER_SECTION_PCI_BUS_H
+#define CPER_SECTION_PCI_BUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <json.h>
+#include <libcper/Cper.h>
+
+#define PCI_BUS_ERROR_VALID_BITFIELD_NAMES                                     \
+	(const char *[])                                                       \
+	{                                                                      \
+		"errorStatusValid", "errorTypeValid", "busIDValid",            \
+			"busAddressValid", "busDataValid", "commandValid",     \
+			"requestorIDValid", "completerIDValid",                \
+			"targetIDValid"                                        \
+	}
+#define PCI_BUS_ERROR_TYPES_KEYS                                               \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 2, 3, 4, 5, 6, 7                                         \
+	}
+#define PCI_BUS_ERROR_TYPES_VALUES                                             \
+	(const char *[])                                                       \
+	{                                                                      \
+		"Unknown/OEM Specific Error", "Data Parity Error",             \
+			"System Error", "Master Abort",                        \
+			"Bus Timeout/No Device Present (No DEVSEL#)",          \
+			"Master Data Parity Error", "Address Parity Error",    \
+			"Command Parity Error"                                 \
+	}
+
+json_object *cper_section_pci_bus_to_ir(void *section);
+void ir_section_pci_bus_to_cper(json_object *section, FILE *out);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/sections/cper-section-pci-dev.h b/include/libcper/sections/cper-section-pci-dev.h
new file mode 100644
index 0000000..7396aa7
--- /dev/null
+++ b/include/libcper/sections/cper-section-pci-dev.h
@@ -0,0 +1,47 @@
+#ifndef CPER_SECTION_PCI_DEV_H
+#define CPER_SECTION_PCI_DEV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <json.h>
+#include <libcper/Cper.h>
+
+#define PCI_DEV_ERROR_VALID_BITFIELD_NAMES                                     \
+	(const char *[])                                                       \
+	{                                                                      \
+		"errorStatusValid", "idInfoValid", "memoryNumberValid",        \
+			"ioNumberValid", "registerDataPairsValid"              \
+	}
+
+///
+/// PCI/PCI-X Device Error Section
+///
+typedef struct {
+	UINT64 VendorId : 16;
+	UINT64 DeviceId : 16;
+	UINT64 ClassCode : 24;
+	UINT64 FunctionNumber : 8;
+	UINT64 DeviceNumber : 8;
+	UINT64 BusNumber : 8;
+	UINT64 SegmentNumber : 8;
+	UINT64 Reserved : 40;
+} EFI_PCI_PCIX_DEVICE_ID_INFO;
+
+typedef struct {
+	UINT64 ValidFields;
+	EFI_GENERIC_ERROR_STATUS ErrorStatus;
+	EFI_PCI_PCIX_DEVICE_ID_INFO IdInfo;
+	UINT32 MemoryNumber;
+	UINT32 IoNumber;
+} __attribute__((packed, aligned(1))) EFI_PCI_PCIX_DEVICE_ERROR_DATA;
+
+json_object *cper_section_pci_dev_to_ir(void *section);
+void ir_section_pci_dev_to_cper(json_object *section, FILE *out);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/sections/cper-section-pcie.h b/include/libcper/sections/cper-section-pcie.h
new file mode 100644
index 0000000..cc54ebd
--- /dev/null
+++ b/include/libcper/sections/cper-section-pcie.h
@@ -0,0 +1,43 @@
+#ifndef CPER_SECTION_PCIE_H
+#define CPER_SECTION_PCIE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <json.h>
+#include <libcper/Cper.h>
+
+#define PCIE_ERROR_VALID_BITFIELD_NAMES                                        \
+	(const char *[])                                                       \
+	{                                                                      \
+		"portTypeValid", "versionValid", "commandStatusValid",         \
+			"deviceIDValid", "deviceSerialNumberValid",            \
+			"bridgeControlStatusValid",                            \
+			"capabilityStructureStatusValid", "aerInfoValid"       \
+	}
+#define PCIE_ERROR_PORT_TYPES_KEYS                                             \
+	(int[])                                                                \
+	{                                                                      \
+		0, 1, 4, 5, 6, 7, 8, 9, 10                                     \
+	}
+#define PCIE_ERROR_PORT_TYPES_VALUES                                           \
+	(const char *[])                                                       \
+	{                                                                      \
+		"PCI Express End Point", "Legacy PCI End Point Device",        \
+			"Root Port", "Upstream Switch Port",                   \
+			"Downstream Switch Port",                              \
+			"PCI Express to PCI/PCI-X Bridge",                     \
+			"PCI/PCI-X Bridge to PCI Express Bridge",              \
+			"Root Complex Integrated Endpoint Device",             \
+			"Root Complex Event Collector"                         \
+	}
+
+json_object *cper_section_pcie_to_ir(void *section);
+void ir_section_pcie_to_cper(json_object *section, FILE *out);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/libcper/sections/cper-section.h b/include/libcper/sections/cper-section.h
new file mode 100644
index 0000000..f288f2a
--- /dev/null
+++ b/include/libcper/sections/cper-section.h
@@ -0,0 +1,29 @@
+#ifndef CPER_SECTION_H
+#define CPER_SECTION_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <json.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <libcper/Cper.h>
+
+//Definition structure for a single CPER section type.
+typedef struct {
+	EFI_GUID *Guid;
+	const char *ReadableName;
+	const char *ShortName;
+	json_object *(*ToIR)(void *);
+	void (*ToCPER)(json_object *, FILE *);
+} CPER_SECTION_DEFINITION;
+
+extern CPER_SECTION_DEFINITION section_definitions[];
+extern const size_t section_definitions_len;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/meson.build b/include/meson.build
new file mode 100644
index 0000000..4865b92
--- /dev/null
+++ b/include/meson.build
@@ -0,0 +1 @@
+subdir('libcper')