clang-format: copy latest and re-format
clang-format-16 has some backwards incompatible changes that require
additional settings for best compatibility and re-running the formatter.
Copy the latest .clang-format from the docs repository and reformat the
repository.
Change-Id: I677d72d4d8d7ff28d2708b51ded916e2287974ff
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
diff --git a/.clang-format b/.clang-format
index ae9ad39..d92a3f1 100644
--- a/.clang-format
+++ b/.clang-format
@@ -5,22 +5,24 @@
AlignAfterOpenBracket: Align
AlignConsecutiveAssignments: false
AlignConsecutiveDeclarations: false
-AlignEscapedNewlinesLeft: false
-AlignOperands: true
-AlignTrailingComments: true
+AlignEscapedNewlines: Right
+AlignOperands: Align
+AlignTrailingComments:
+ Kind: Always
+ OverEmptyLines: 1
AllowAllParametersOfDeclarationOnNextLine: true
-AllowShortBlocksOnASingleLine: false
+AllowShortBlocksOnASingleLine: Empty
AllowShortCaseLabelsOnASingleLine: false
-AllowShortFunctionsOnASingleLine: None
+AllowShortFunctionsOnASingleLine: Empty
AllowShortIfStatementsOnASingleLine: false
AllowShortLoopsOnASingleLine: false
-AlwaysBreakAfterDefinitionReturnType: None
AlwaysBreakAfterReturnType: None
AlwaysBreakBeforeMultilineStrings: false
-AlwaysBreakTemplateDeclarations: true
+AlwaysBreakTemplateDeclarations: Yes
BinPackArguments: true
BinPackParameters: true
BraceWrapping:
+ AfterCaseLabel: true
AfterClass: true
AfterControlStatement: true
AfterEnum: true
@@ -29,19 +31,28 @@
AfterObjCDeclaration: true
AfterStruct: true
AfterUnion: true
+ AfterExternBlock: true
BeforeCatch: true
BeforeElse: true
IndentBraces: false
+ SplitEmptyFunction: false
+ SplitEmptyRecord: false
+ SplitEmptyNamespace: false
+BreakAfterAttributes: Never
BreakBeforeBinaryOperators: None
BreakBeforeBraces: Custom
BreakBeforeTernaryOperators: true
BreakConstructorInitializers: AfterColon
+BreakInheritanceList: AfterColon
+BreakStringLiterals: false
ColumnLimit: 80
CommentPragmas: '^ IWYU pragma:'
+CompactNamespaces: false
ConstructorInitializerAllOnOneLineOrOnePerLine: false
ConstructorInitializerIndentWidth: 4
ContinuationIndentWidth: 4
Cpp11BracedListStyle: true
+DeriveLineEnding: false
DerivePointerAlignment: false
PointerAlignment: Left
DisableFormat: false
@@ -51,21 +62,29 @@
IncludeBlocks: Regroup
IncludeCategories:
- Regex: '^[<"](gtest|gmock)'
- Priority: 5
+ Priority: 7
- Regex: '^"config.h"'
Priority: -1
- - Regex: '^".*\.hpp"'
+ - Regex: '^".*\.h"'
Priority: 1
- - Regex: '^<.*\.h>'
+ - Regex: '^".*\.hpp"'
Priority: 2
- - Regex: '^<.*'
+ - Regex: '^<.*\.h>'
Priority: 3
- - Regex: '.*'
+ - Regex: '^<.*\.hpp>'
Priority: 4
+ - Regex: '^<.*'
+ Priority: 5
+ - Regex: '.*'
+ Priority: 6
IndentCaseLabels: true
+IndentRequiresClause: true
IndentWidth: 4
IndentWrappedFunctionNames: true
-KeepEmptyLinesAtTheStartOfBlocks: true
+InsertNewlineAtEOF: true
+KeepEmptyLinesAtTheStartOfBlocks: false
+LambdaBodyIndentation: OuterScope
+LineEnding: LF
MacroBlockBegin: ''
MacroBlockEnd: ''
MaxEmptyLinesToKeep: 1
@@ -73,18 +92,29 @@
ObjCBlockIndentWidth: 2
ObjCSpaceAfterProperty: false
ObjCSpaceBeforeProtocolList: true
+PenaltyBreakAssignment: 25
PenaltyBreakBeforeFirstCallParameter: 19
PenaltyBreakComment: 300
PenaltyBreakFirstLessLess: 120
PenaltyBreakString: 1000
PenaltyExcessCharacter: 1000000
PenaltyReturnTypeOnItsOwnLine: 60
+PenaltyIndentedWhitespace: 0
+QualifierAlignment: Left
+ReferenceAlignment: Left
ReflowComments: true
+RequiresClausePosition: OwnLine
+RequiresExpressionIndentation: Keyword
SortIncludes: true
SortUsingDeclarations: true
SpaceAfterCStyleCast: false
+SpaceAfterTemplateKeyword: true
SpaceBeforeAssignmentOperators: true
+SpaceBeforeCpp11BracedList: false
+SpaceBeforeCtorInitializerColon: true
+SpaceBeforeInheritanceColon: true
SpaceBeforeParens: ControlStatements
+SpaceBeforeRangeBasedForLoopColon: true
SpaceInEmptyParentheses: false
SpacesBeforeTrailingComments: 1
SpacesInAngles: false
@@ -92,7 +122,8 @@
SpacesInCStyleCastParentheses: false
SpacesInParentheses: false
SpacesInSquareBrackets: false
-Standard: Cpp11
+Standard: Latest
TabWidth: 4
UseTab: Never
...
+
diff --git a/dbus_raw_peci.cpp b/dbus_raw_peci.cpp
index cb47d20..adb0013 100644
--- a/dbus_raw_peci.cpp
+++ b/dbus_raw_peci.cpp
@@ -16,9 +16,10 @@
#include <peci.h>
#include <boost/asio/io_context.hpp>
-#include <iostream>
#include <sdbusplus/asio/object_server.hpp>
+#include <iostream>
+
int main()
{
boost::asio::io_context io;
diff --git a/peci.c b/peci.c
index 5b6346b..ab69234 100644
--- a/peci.c
+++ b/peci.c
@@ -377,8 +377,8 @@
cmd.addr = target;
- EPECIStatus ret =
- HW_peci_issue_cmd(PECI_IOC_GET_TEMP, (char*)&cmd, peci_fd);
+ EPECIStatus ret = HW_peci_issue_cmd(PECI_IOC_GET_TEMP, (char*)&cmd,
+ peci_fd);
if (ret == PECI_CC_SUCCESS)
{
@@ -807,9 +807,9 @@
{
return PECI_CC_DRIVER_ERR;
}
- ret =
- peci_RdPCIConfigLocal_seq_dom(target, domainId, u8Bus, u8Device, u8Fcn,
- u16Reg, u8ReadLen, pPCIReg, peci_fd, cc);
+ ret = peci_RdPCIConfigLocal_seq_dom(target, domainId, u8Bus, u8Device,
+ u8Fcn, u16Reg, u8ReadLen, pPCIReg,
+ peci_fd, cc);
peci_Close(peci_fd);
return ret;
@@ -1832,9 +1832,9 @@
return PECI_CC_CPU_NOT_PRESENT;
}
- ret =
- peci_RdPkgConfig(clientAddr, PECI_MBX_INDEX_CPU_ID, PECI_PKG_ID_CPU_ID,
- sizeof(uint32_t), (uint8_t*)&cpuid, cc);
+ ret = peci_RdPkgConfig(clientAddr, PECI_MBX_INDEX_CPU_ID,
+ PECI_PKG_ID_CPU_ID, sizeof(uint32_t),
+ (uint8_t*)&cpuid, cc);
// Separate out the model and stepping (bits 3:0) from the CPUID
*cpuModel = cpuid & 0xFFFFFFF0;
diff --git a/peci.h b/peci.h
index b3404a7..eef8533 100644
--- a/peci.h
+++ b/peci.h
@@ -15,7 +15,8 @@
*/
#pragma once
#ifdef __cplusplus
-extern "C" {
+extern "C"
+{
#endif
#include <inttypes.h>
#include <stdbool.h>
@@ -29,35 +30,35 @@
#define PECI_DEV_CC_SUCCESS 0x40
#define PECI_DEV_CC_FATAL_MCA_DETECTED 0x94
-typedef enum
-{
- skx = 0x00050650,
- icx = 0x000606A0,
- icxd = 0x000606C0,
- spr = 0x000806F0,
- emr = 0x000C06F0,
- gnr = 0x000A06D0,
- srf = 0x000A06F0,
-} CPUModel;
+ typedef enum
+ {
+ skx = 0x00050650,
+ icx = 0x000606A0,
+ icxd = 0x000606C0,
+ spr = 0x000806F0,
+ emr = 0x000C06F0,
+ gnr = 0x000A06D0,
+ srf = 0x000A06F0,
+ } CPUModel;
-// PECI Status Codes
-typedef enum
-{
- PECI_CC_SUCCESS = 0,
- PECI_CC_INVALID_REQ,
- PECI_CC_HW_ERR,
- PECI_CC_DRIVER_ERR,
- PECI_CC_CPU_NOT_PRESENT,
- PECI_CC_MEM_ERR,
- PECI_CC_TIMEOUT,
-} EPECIStatus;
+ // PECI Status Codes
+ typedef enum
+ {
+ PECI_CC_SUCCESS = 0,
+ PECI_CC_INVALID_REQ,
+ PECI_CC_HW_ERR,
+ PECI_CC_DRIVER_ERR,
+ PECI_CC_CPU_NOT_PRESENT,
+ PECI_CC_MEM_ERR,
+ PECI_CC_TIMEOUT,
+ } EPECIStatus;
-// PECI Timeout Options
-typedef enum
-{
- PECI_WAIT_FOREVER = -1,
- PECI_NO_WAIT = 0,
-} EPECITimeout;
+ // PECI Timeout Options
+ typedef enum
+ {
+ PECI_WAIT_FOREVER = -1,
+ PECI_NO_WAIT = 0,
+ } EPECITimeout;
#define PECI_TIMEOUT_RESOLUTION_MS 10 // 10 ms
#define PECI_TIMEOUT_MS 100 // 100 ms
@@ -70,368 +71,370 @@
#define VCU_ABORT_SEQ 0x0005
#define VCU_VERSION 0x0009
-typedef enum
-{
- VCU_READ_LOCAL_CSR_SEQ = 0x2,
- VCU_READ_LOCAL_MMIO_SEQ = 0x6,
- VCU_EN_SECURE_DATA_SEQ = 0x14,
- VCU_CORE_MCA_SEQ = 0x10000,
- VCU_UNCORE_MCA_SEQ = 0x10000,
- VCU_IOT_BRKPT_SEQ = 0x10010,
- VCU_MBP_CONFIG_SEQ = 0x10026,
- VCU_PWR_MGT_SEQ = 0x1002a,
- VCU_CRASHDUMP_SEQ = 0x10038,
- VCU_ARRAY_DUMP_SEQ = 0x20000,
- VCU_SCAN_DUMP_SEQ = 0x20008,
- VCU_TOR_DUMP_SEQ = 0x30002,
- VCU_SQ_DUMP_SEQ = 0x30004,
- VCU_UNCORE_CRASHDUMP_SEQ = 0x30006,
-} EPECISequence;
+ typedef enum
+ {
+ VCU_READ_LOCAL_CSR_SEQ = 0x2,
+ VCU_READ_LOCAL_MMIO_SEQ = 0x6,
+ VCU_EN_SECURE_DATA_SEQ = 0x14,
+ VCU_CORE_MCA_SEQ = 0x10000,
+ VCU_UNCORE_MCA_SEQ = 0x10000,
+ VCU_IOT_BRKPT_SEQ = 0x10010,
+ VCU_MBP_CONFIG_SEQ = 0x10026,
+ VCU_PWR_MGT_SEQ = 0x1002a,
+ VCU_CRASHDUMP_SEQ = 0x10038,
+ VCU_ARRAY_DUMP_SEQ = 0x20000,
+ VCU_SCAN_DUMP_SEQ = 0x20008,
+ VCU_TOR_DUMP_SEQ = 0x30002,
+ VCU_SQ_DUMP_SEQ = 0x30004,
+ VCU_UNCORE_CRASHDUMP_SEQ = 0x30006,
+ } EPECISequence;
#define MBX_INDEX_VCU 128 // VCU Index
-typedef enum
-{
- MMIO_DWORD_OFFSET = 0x05,
- MMIO_QWORD_OFFSET = 0x06,
-} EEndPtMmioAddrType;
+ typedef enum
+ {
+ MMIO_DWORD_OFFSET = 0x05,
+ MMIO_QWORD_OFFSET = 0x06,
+ } EEndPtMmioAddrType;
-// Find the specified PCI bus number value
-EPECIStatus FindBusNumber(uint8_t u8Bus, uint8_t u8Cpu, uint8_t* pu8BusValue);
+ // Find the specified PCI bus number value
+ EPECIStatus FindBusNumber(uint8_t u8Bus, uint8_t u8Cpu,
+ uint8_t* pu8BusValue);
-// Gets the temperature from the target
-// Expressed in signed fixed point value of 1/64 degrees celsius
-EPECIStatus peci_GetTemp(uint8_t target, int16_t* temperature);
+ // Gets the temperature from the target
+ // Expressed in signed fixed point value of 1/64 degrees celsius
+ EPECIStatus peci_GetTemp(uint8_t target, int16_t* temperature);
-// Provides read access to the package configuration space within the processor
-EPECIStatus peci_RdPkgConfig(uint8_t target, uint8_t u8Index, uint16_t u16Value,
- uint8_t u8ReadLen, uint8_t* pPkgConfig,
- uint8_t* cc);
-
-// Provides read access to the package configuration space within the processor
-// in the specified domain
-EPECIStatus peci_RdPkgConfig_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Index, uint16_t u16Value,
- uint8_t u8ReadLen, uint8_t* pPkgConfig,
- uint8_t* cc);
-
-// Allows sequential RdPkgConfig with the provided peci file descriptor
-EPECIStatus peci_RdPkgConfig_seq(uint8_t target, uint8_t u8Index,
+ // Provides read access to the package configuration space within the
+ // processor
+ EPECIStatus peci_RdPkgConfig(uint8_t target, uint8_t u8Index,
uint16_t u16Value, uint8_t u8ReadLen,
- uint8_t* pPkgConfig, int peci_fd, uint8_t* cc);
+ uint8_t* pPkgConfig, uint8_t* cc);
-// Allows sequential RdPkgConfig with the provided peci file descriptor in the
-// specified domain
-EPECIStatus peci_RdPkgConfig_seq_dom(uint8_t target, uint8_t domainId,
+ // Provides read access to the package configuration space within the
+ // processor in the specified domain
+ EPECIStatus peci_RdPkgConfig_dom(uint8_t target, uint8_t domainId,
uint8_t u8Index, uint16_t u16Value,
uint8_t u8ReadLen, uint8_t* pPkgConfig,
- int peci_fd, uint8_t* cc);
+ uint8_t* cc);
-// Provides write access to the package configuration space within the processor
-EPECIStatus peci_WrPkgConfig(uint8_t target, uint8_t u8Index, uint16_t u16Param,
- uint32_t u32Value, uint8_t u8WriteLen,
- uint8_t* cc);
+ // Allows sequential RdPkgConfig with the provided peci file descriptor
+ EPECIStatus peci_RdPkgConfig_seq(uint8_t target, uint8_t u8Index,
+ uint16_t u16Value, uint8_t u8ReadLen,
+ uint8_t* pPkgConfig, int peci_fd,
+ uint8_t* cc);
-// Provides write access to the package configuration space within the processor
-// in the specified domain
-EPECIStatus peci_WrPkgConfig_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Index, uint16_t u16Param,
- uint32_t u32Value, uint8_t u8WriteLen,
- uint8_t* cc);
+ // Allows sequential RdPkgConfig with the provided peci file descriptor in
+ // the specified domain
+ EPECIStatus peci_RdPkgConfig_seq_dom(uint8_t target, uint8_t domainId,
+ uint8_t u8Index, uint16_t u16Value,
+ uint8_t u8ReadLen, uint8_t* pPkgConfig,
+ int peci_fd, uint8_t* cc);
-// Allows sequential WrPkgConfig with the provided peci file descriptor
-EPECIStatus peci_WrPkgConfig_seq(uint8_t target, uint8_t u8Index,
+ // Provides write access to the package configuration space within the
+ // processor
+ EPECIStatus peci_WrPkgConfig(uint8_t target, uint8_t u8Index,
uint16_t u16Param, uint32_t u32Value,
- uint8_t u8WriteLen, int peci_fd, uint8_t* cc);
+ uint8_t u8WriteLen, uint8_t* cc);
-// Allows sequential WrPkgConfig with the provided peci file descriptor in the
-// specified domain
-EPECIStatus peci_WrPkgConfig_seq_dom(uint8_t target, uint8_t domainId,
+ // Provides write access to the package configuration space within the
+ // processor in the specified domain
+ EPECIStatus peci_WrPkgConfig_dom(uint8_t target, uint8_t domainId,
uint8_t u8Index, uint16_t u16Param,
uint32_t u32Value, uint8_t u8WriteLen,
- int peci_fd, uint8_t* cc);
+ uint8_t* cc);
-// Provides read access to Model Specific Registers
-EPECIStatus peci_RdIAMSR(uint8_t target, uint8_t threadID, uint16_t MSRAddress,
- uint64_t* u64MsrVal, uint8_t* cc);
+ // Allows sequential WrPkgConfig with the provided peci file descriptor
+ EPECIStatus peci_WrPkgConfig_seq(uint8_t target, uint8_t u8Index,
+ uint16_t u16Param, uint32_t u32Value,
+ uint8_t u8WriteLen, int peci_fd,
+ uint8_t* cc);
-// Provides read access to Model Specific Registers in the specified domain
-EPECIStatus peci_RdIAMSR_dom(uint8_t target, uint8_t domainId, uint8_t threadID,
+ // Allows sequential WrPkgConfig with the provided peci file descriptor in
+ // the specified domain
+ EPECIStatus peci_WrPkgConfig_seq_dom(uint8_t target, uint8_t domainId,
+ uint8_t u8Index, uint16_t u16Param,
+ uint32_t u32Value, uint8_t u8WriteLen,
+ int peci_fd, uint8_t* cc);
+
+ // Provides read access to Model Specific Registers
+ EPECIStatus peci_RdIAMSR(uint8_t target, uint8_t threadID,
uint16_t MSRAddress, uint64_t* u64MsrVal,
uint8_t* cc);
-// Provides read access to PCI Configuration space
-EPECIStatus peci_RdPCIConfig(uint8_t target, uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint16_t u16Reg, uint8_t* pPCIReg,
- uint8_t* cc);
+ // Provides read access to Model Specific Registers in the specified domain
+ EPECIStatus peci_RdIAMSR_dom(uint8_t target, uint8_t domainId,
+ uint8_t threadID, uint16_t MSRAddress,
+ uint64_t* u64MsrVal, uint8_t* cc);
-// Provides read access to PCI Configuration space in the specified domain
-EPECIStatus peci_RdPCIConfig_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Bus, uint8_t u8Device, uint8_t u8Fcn,
+ // Provides read access to PCI Configuration space
+ EPECIStatus peci_RdPCIConfig(uint8_t target, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn,
uint16_t u16Reg, uint8_t* pPCIReg,
uint8_t* cc);
-// Allows sequential RdPCIConfig with the provided peci file descriptor
-EPECIStatus peci_RdPCIConfig_seq(uint8_t target, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint16_t u16Reg, uint8_t* pPCIData,
- int peci_fd, uint8_t* cc);
-
-// Allows sequential RdPCIConfig with the provided peci file descriptor in the
-// specified domain
-EPECIStatus peci_RdPCIConfig_seq_dom(uint8_t target, uint8_t domainId,
+ // Provides read access to PCI Configuration space in the specified domain
+ EPECIStatus peci_RdPCIConfig_dom(uint8_t target, uint8_t domainId,
uint8_t u8Bus, uint8_t u8Device,
uint8_t u8Fcn, uint16_t u16Reg,
- uint8_t* pPCIData, int peci_fd,
- uint8_t* cc);
+ uint8_t* pPCIReg, uint8_t* cc);
-// Provides read access to the local PCI Configuration space
-EPECIStatus peci_RdPCIConfigLocal(uint8_t target, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint16_t u16Reg, uint8_t u8ReadLen,
- uint8_t* pPCIReg, uint8_t* cc);
+ // Allows sequential RdPCIConfig with the provided peci file descriptor
+ EPECIStatus peci_RdPCIConfig_seq(uint8_t target, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn,
+ uint16_t u16Reg, uint8_t* pPCIData,
+ int peci_fd, uint8_t* cc);
-// Provides read access to the local PCI Configuration space in the specified
-// domain
-EPECIStatus peci_RdPCIConfigLocal_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint16_t u16Reg,
- uint8_t u8ReadLen, uint8_t* pPCIReg,
- uint8_t* cc);
+ // Allows sequential RdPCIConfig with the provided peci file descriptor in
+ // the specified domain
+ EPECIStatus peci_RdPCIConfig_seq_dom(uint8_t target, uint8_t domainId,
+ uint8_t u8Bus, uint8_t u8Device,
+ uint8_t u8Fcn, uint16_t u16Reg,
+ uint8_t* pPCIData, int peci_fd,
+ uint8_t* cc);
-// Allows sequential RdPCIConfigLocal with the provided peci file descriptor
-EPECIStatus peci_RdPCIConfigLocal_seq(uint8_t target, uint8_t u8Bus,
+ // Provides read access to the local PCI Configuration space
+ EPECIStatus peci_RdPCIConfigLocal(uint8_t target, uint8_t u8Bus,
uint8_t u8Device, uint8_t u8Fcn,
uint16_t u16Reg, uint8_t u8ReadLen,
- uint8_t* pPCIReg, int peci_fd,
- uint8_t* cc);
+ uint8_t* pPCIReg, uint8_t* cc);
-// Allows sequential RdPCIConfigLocal with the provided peci file descriptor in
-// the specified domain
-EPECIStatus peci_RdPCIConfigLocal_seq_dom(uint8_t target, uint8_t domainId,
+ // Provides read access to the local PCI Configuration space in the
+ // specified domain
+ EPECIStatus peci_RdPCIConfigLocal_dom(uint8_t target, uint8_t domainId,
uint8_t u8Bus, uint8_t u8Device,
uint8_t u8Fcn, uint16_t u16Reg,
uint8_t u8ReadLen, uint8_t* pPCIReg,
- int peci_fd, uint8_t* cc);
-
-// Provides write access to the local PCI Configuration space
-EPECIStatus peci_WrPCIConfigLocal(uint8_t target, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint16_t u16Reg, uint8_t DataLen,
- uint32_t DataVal, uint8_t* cc);
-
-// Provides write access to the local PCI Configuration space in the specified
-// domain
-EPECIStatus peci_WrPCIConfigLocal_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint16_t u16Reg,
- uint8_t DataLen, uint32_t DataVal,
- uint8_t* cc);
-
-// Provides read access to PCI configuration space
-EPECIStatus peci_RdEndPointConfigPci(uint8_t target, uint8_t u8Seg,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint16_t u16Reg,
- uint8_t u8ReadLen, uint8_t* pPCIData,
- uint8_t* cc);
-
-// Provides read access to PCI configuration space in the specified domain
-EPECIStatus peci_RdEndPointConfigPci_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Seg, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint16_t u16Reg, uint8_t u8ReadLen,
- uint8_t* pPCIData, uint8_t* cc);
-
-// Allows sequential RdEndPointConfig to PCI Configuration space
-EPECIStatus peci_RdEndPointConfigPci_seq(uint8_t target, uint8_t u8Seg,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint16_t u16Reg,
- uint8_t u8ReadLen, uint8_t* pPCIData,
- int peci_fd, uint8_t* cc);
-
-// Allows sequential RdEndPointConfig to PCI Configuration space in the
-// specified domain
-EPECIStatus peci_RdEndPointConfigPci_seq_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Seg, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint16_t u16Reg, uint8_t u8ReadLen,
- uint8_t* pPCIData, int peci_fd,
- uint8_t* cc);
-
-// Provides read access to the local PCI configuration space
-EPECIStatus peci_RdEndPointConfigPciLocal(uint8_t target, uint8_t u8Seg,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint16_t u16Reg,
- uint8_t u8ReadLen, uint8_t* pPCIData,
uint8_t* cc);
-// Provides read access to the local PCI configuration space in the specified
-// domain
-EPECIStatus peci_RdEndPointConfigPciLocal_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Seg, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint16_t u16Reg,
- uint8_t u8ReadLen,
- uint8_t* pPCIData, uint8_t* cc);
+ // Allows sequential RdPCIConfigLocal with the provided peci file descriptor
+ EPECIStatus peci_RdPCIConfigLocal_seq(uint8_t target, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn,
+ uint16_t u16Reg, uint8_t u8ReadLen,
+ uint8_t* pPCIReg, int peci_fd,
+ uint8_t* cc);
-// Allows sequential RdEndPointConfig to the local PCI Configuration space
-EPECIStatus peci_RdEndPointConfigPciLocal_seq(uint8_t target, uint8_t u8Seg,
+ // Allows sequential RdPCIConfigLocal with the provided peci file descriptor
+ // in the specified domain
+ EPECIStatus peci_RdPCIConfigLocal_seq_dom(uint8_t target, uint8_t domainId,
uint8_t u8Bus, uint8_t u8Device,
uint8_t u8Fcn, uint16_t u16Reg,
uint8_t u8ReadLen,
- uint8_t* pPCIData, int peci_fd,
+ uint8_t* pPCIReg, int peci_fd,
uint8_t* cc);
-// Allows sequential RdEndPointConfig to the local PCI Configuration space in
-// the specified domain
-EPECIStatus peci_RdEndPointConfigPciLocal_seq_dom(
- uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg, uint8_t u8ReadLen,
- uint8_t* pPCIData, int peci_fd, uint8_t* cc);
+ // Provides write access to the local PCI Configuration space
+ EPECIStatus peci_WrPCIConfigLocal(uint8_t target, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn,
+ uint16_t u16Reg, uint8_t DataLen,
+ uint32_t DataVal, uint8_t* cc);
-// Provides read access to PCI MMIO space
-EPECIStatus peci_RdEndPointConfigMmio(uint8_t target, uint8_t u8Seg,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint8_t u8Bar,
- uint8_t u8AddrType, uint64_t u64Offset,
- uint8_t u8ReadLen, uint8_t* pMmioData,
- uint8_t* cc);
-
-// Provides read access to PCI MMIO space in the specified domain
-EPECIStatus peci_RdEndPointConfigMmio_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Seg, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint8_t u8Bar, uint8_t u8AddrType,
- uint64_t u64Offset, uint8_t u8ReadLen,
- uint8_t* pMmioData, uint8_t* cc);
-
-// Allows sequential RdEndPointConfig to PCI MMIO space
-EPECIStatus peci_RdEndPointConfigMmio_seq(
- uint8_t target, uint8_t u8Seg, uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType, uint64_t u64Offset,
- uint8_t u8ReadLen, uint8_t* pMmioData, int peci_fd, uint8_t* cc);
-
-// Allows sequential RdEndPointConfig to PCI MMIO space in the specified domain
-EPECIStatus peci_RdEndPointConfigMmio_seq_dom(
- uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType,
- uint64_t u64Offset, uint8_t u8ReadLen, uint8_t* pMmioData, int peci_fd,
- uint8_t* cc);
-
-// Provides write access to the EP local PCI Configuration space
-EPECIStatus peci_WrEndPointPCIConfigLocal(uint8_t target, uint8_t u8Seg,
+ // Provides write access to the local PCI Configuration space in the
+ // specified domain
+ EPECIStatus peci_WrPCIConfigLocal_dom(uint8_t target, uint8_t domainId,
uint8_t u8Bus, uint8_t u8Device,
uint8_t u8Fcn, uint16_t u16Reg,
uint8_t DataLen, uint32_t DataVal,
uint8_t* cc);
-// Provides write access to the EP local PCI Configuration space in the
-// specified domain
-EPECIStatus peci_WrEndPointPCIConfigLocal_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Seg, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint16_t u16Reg, uint8_t DataLen,
- uint32_t DataVal, uint8_t* cc);
+ // Provides read access to PCI configuration space
+ EPECIStatus peci_RdEndPointConfigPci(uint8_t target, uint8_t u8Seg,
+ uint8_t u8Bus, uint8_t u8Device,
+ uint8_t u8Fcn, uint16_t u16Reg,
+ uint8_t u8ReadLen, uint8_t* pPCIData,
+ uint8_t* cc);
-// Provides write access to the EP PCI Configuration space
-EPECIStatus peci_WrEndPointPCIConfig(uint8_t target, uint8_t u8Seg,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint16_t u16Reg,
- uint8_t DataLen, uint32_t DataVal,
- uint8_t* cc);
+ // Provides read access to PCI configuration space in the specified domain
+ EPECIStatus peci_RdEndPointConfigPci_dom(uint8_t target, uint8_t domainId,
+ uint8_t u8Seg, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn,
+ uint16_t u16Reg, uint8_t u8ReadLen,
+ uint8_t* pPCIData, uint8_t* cc);
-// Provides write access to the EP PCI Configuration space in the specified
-// domain
-EPECIStatus peci_WrEndPointPCIConfig_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Seg, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint16_t u16Reg, uint8_t DataLen,
- uint32_t DataVal, uint8_t* cc);
+ // Allows sequential RdEndPointConfig to PCI Configuration space
+ EPECIStatus peci_RdEndPointConfigPci_seq(uint8_t target, uint8_t u8Seg,
+ uint8_t u8Bus, uint8_t u8Device,
+ uint8_t u8Fcn, uint16_t u16Reg,
+ uint8_t u8ReadLen,
+ uint8_t* pPCIData, int peci_fd,
+ uint8_t* cc);
-// Allows sequential write access to the EP PCI Configuration space
-EPECIStatus peci_WrEndPointConfig_seq(uint8_t target, uint8_t u8MsgType,
- uint8_t u8Seg, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint16_t u16Reg, uint8_t DataLen,
- uint32_t DataVal, int peci_fd,
- uint8_t* cc);
+ // Allows sequential RdEndPointConfig to PCI Configuration space in the
+ // specified domain
+ EPECIStatus peci_RdEndPointConfigPci_seq_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg, uint8_t u8ReadLen,
+ uint8_t* pPCIData, int peci_fd, uint8_t* cc);
-// Allows sequential write access to the EP PCI Configuration space in the
-// specified domain
-EPECIStatus peci_WrEndPointConfig_seq_dom(uint8_t target, uint8_t domainId,
- uint8_t u8MsgType, uint8_t u8Seg,
+ // Provides read access to the local PCI configuration space
+ EPECIStatus peci_RdEndPointConfigPciLocal(uint8_t target, uint8_t u8Seg,
+ uint8_t u8Bus, uint8_t u8Device,
+ uint8_t u8Fcn, uint16_t u16Reg,
+ uint8_t u8ReadLen,
+ uint8_t* pPCIData, uint8_t* cc);
+
+ // Provides read access to the local PCI configuration space in the
+ // specified domain
+ EPECIStatus peci_RdEndPointConfigPciLocal_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg, uint8_t u8ReadLen,
+ uint8_t* pPCIData, uint8_t* cc);
+
+ // Allows sequential RdEndPointConfig to the local PCI Configuration space
+ EPECIStatus peci_RdEndPointConfigPciLocal_seq(
+ uint8_t target, uint8_t u8Seg, uint8_t u8Bus, uint8_t u8Device,
+ uint8_t u8Fcn, uint16_t u16Reg, uint8_t u8ReadLen, uint8_t* pPCIData,
+ int peci_fd, uint8_t* cc);
+
+ // Allows sequential RdEndPointConfig to the local PCI Configuration space
+ // in the specified domain
+ EPECIStatus peci_RdEndPointConfigPciLocal_seq_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg, uint8_t u8ReadLen,
+ uint8_t* pPCIData, int peci_fd, uint8_t* cc);
+
+ // Provides read access to PCI MMIO space
+ EPECIStatus peci_RdEndPointConfigMmio(uint8_t target, uint8_t u8Seg,
uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint16_t u16Reg,
- uint8_t DataLen, uint32_t DataVal,
- int peci_fd, uint8_t* cc);
+ uint8_t u8Fcn, uint8_t u8Bar,
+ uint8_t u8AddrType,
+ uint64_t u64Offset, uint8_t u8ReadLen,
+ uint8_t* pMmioData, uint8_t* cc);
-// Provides write access to the EP PCI MMIO space
-EPECIStatus peci_WrEndPointConfigMmio(uint8_t target, uint8_t u8Seg,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint8_t u8Bar,
- uint8_t u8AddrType, uint64_t u64Offset,
- uint8_t u8DataLen, uint64_t u64DataVal,
- uint8_t* cc);
+ // Provides read access to PCI MMIO space in the specified domain
+ EPECIStatus peci_RdEndPointConfigMmio_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType,
+ uint64_t u64Offset, uint8_t u8ReadLen, uint8_t* pMmioData, uint8_t* cc);
-// Provides write access to the EP PCI MMIO space in the specified domain
-EPECIStatus peci_WrEndPointConfigMmio_dom(uint8_t target, uint8_t domainId,
+ // Allows sequential RdEndPointConfig to PCI MMIO space
+ EPECIStatus peci_RdEndPointConfigMmio_seq(
+ uint8_t target, uint8_t u8Seg, uint8_t u8Bus, uint8_t u8Device,
+ uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType, uint64_t u64Offset,
+ uint8_t u8ReadLen, uint8_t* pMmioData, int peci_fd, uint8_t* cc);
+
+ // Allows sequential RdEndPointConfig to PCI MMIO space in the specified
+ // domain
+ EPECIStatus peci_RdEndPointConfigMmio_seq_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType,
+ uint64_t u64Offset, uint8_t u8ReadLen, uint8_t* pMmioData, int peci_fd,
+ uint8_t* cc);
+
+ // Provides write access to the EP local PCI Configuration space
+ EPECIStatus peci_WrEndPointPCIConfigLocal(uint8_t target, uint8_t u8Seg,
+ uint8_t u8Bus, uint8_t u8Device,
+ uint8_t u8Fcn, uint16_t u16Reg,
+ uint8_t DataLen, uint32_t DataVal,
+ uint8_t* cc);
+
+ // Provides write access to the EP local PCI Configuration space in the
+ // specified domain
+ EPECIStatus peci_WrEndPointPCIConfigLocal_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg, uint8_t DataLen,
+ uint32_t DataVal, uint8_t* cc);
+
+ // Provides write access to the EP PCI Configuration space
+ EPECIStatus peci_WrEndPointPCIConfig(uint8_t target, uint8_t u8Seg,
+ uint8_t u8Bus, uint8_t u8Device,
+ uint8_t u8Fcn, uint16_t u16Reg,
+ uint8_t DataLen, uint32_t DataVal,
+ uint8_t* cc);
+
+ // Provides write access to the EP PCI Configuration space in the specified
+ // domain
+ EPECIStatus peci_WrEndPointPCIConfig_dom(uint8_t target, uint8_t domainId,
+ uint8_t u8Seg, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn,
+ uint16_t u16Reg, uint8_t DataLen,
+ uint32_t DataVal, uint8_t* cc);
+
+ // Allows sequential write access to the EP PCI Configuration space
+ EPECIStatus peci_WrEndPointConfig_seq(uint8_t target, uint8_t u8MsgType,
uint8_t u8Seg, uint8_t u8Bus,
uint8_t u8Device, uint8_t u8Fcn,
- uint8_t u8Bar, uint8_t u8AddrType,
+ uint16_t u16Reg, uint8_t DataLen,
+ uint32_t DataVal, int peci_fd,
+ uint8_t* cc);
+
+ // Allows sequential write access to the EP PCI Configuration space in the
+ // specified domain
+ EPECIStatus peci_WrEndPointConfig_seq_dom(uint8_t target, uint8_t domainId,
+ uint8_t u8MsgType, uint8_t u8Seg,
+ uint8_t u8Bus, uint8_t u8Device,
+ uint8_t u8Fcn, uint16_t u16Reg,
+ uint8_t DataLen, uint32_t DataVal,
+ int peci_fd, uint8_t* cc);
+
+ // Provides write access to the EP PCI MMIO space
+ EPECIStatus peci_WrEndPointConfigMmio(uint8_t target, uint8_t u8Seg,
+ uint8_t u8Bus, uint8_t u8Device,
+ uint8_t u8Fcn, uint8_t u8Bar,
+ uint8_t u8AddrType,
uint64_t u64Offset, uint8_t u8DataLen,
uint64_t u64DataVal, uint8_t* cc);
-// Allows sequential write access to the EP PCI MMIO space
-EPECIStatus peci_WrEndPointConfigMmio_seq(
- uint8_t target, uint8_t u8Seg, uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType, uint64_t u64Offset,
- uint8_t u8DataLen, uint64_t u64DataVal, int peci_fd, uint8_t* cc);
+ // Provides write access to the EP PCI MMIO space in the specified domain
+ EPECIStatus peci_WrEndPointConfigMmio_dom(uint8_t target, uint8_t domainId,
+ uint8_t u8Seg, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn,
+ uint8_t u8Bar, uint8_t u8AddrType,
+ uint64_t u64Offset,
+ uint8_t u8DataLen,
+ uint64_t u64DataVal, uint8_t* cc);
-// Allows sequential write access to the EP PCI MMIO space in the specified
-// domain
-EPECIStatus peci_WrEndPointConfigMmio_seq_dom(
- uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType,
- uint64_t u64Offset, uint8_t u8DataLen, uint64_t u64DataVal, int peci_fd,
- uint8_t* cc);
+ // Allows sequential write access to the EP PCI MMIO space
+ EPECIStatus peci_WrEndPointConfigMmio_seq(
+ uint8_t target, uint8_t u8Seg, uint8_t u8Bus, uint8_t u8Device,
+ uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType, uint64_t u64Offset,
+ uint8_t u8DataLen, uint64_t u64DataVal, int peci_fd, uint8_t* cc);
-// Provides access to the Crashdump Discovery API
-EPECIStatus peci_CrashDump_Discovery(uint8_t target, uint8_t subopcode,
- uint8_t param0, uint16_t param1,
- uint8_t param2, uint8_t u8ReadLen,
- uint8_t* pData, uint8_t* cc);
+ // Allows sequential write access to the EP PCI MMIO space in the specified
+ // domain
+ EPECIStatus peci_WrEndPointConfigMmio_seq_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType,
+ uint64_t u64Offset, uint8_t u8DataLen, uint64_t u64DataVal, int peci_fd,
+ uint8_t* cc);
-// Provides access to the Crashdump Discovery API in the specified domain
-EPECIStatus peci_CrashDump_Discovery_dom(uint8_t target, uint8_t domainId,
- uint8_t subopcode, uint8_t param0,
- uint16_t param1, uint8_t param2,
- uint8_t u8ReadLen, uint8_t* pData,
- uint8_t* cc);
+ // Provides access to the Crashdump Discovery API
+ EPECIStatus peci_CrashDump_Discovery(uint8_t target, uint8_t subopcode,
+ uint8_t param0, uint16_t param1,
+ uint8_t param2, uint8_t u8ReadLen,
+ uint8_t* pData, uint8_t* cc);
-// Provides access to the Crashdump GetFrame API
-EPECIStatus peci_CrashDump_GetFrame(uint8_t target, uint16_t param0,
- uint16_t param1, uint16_t param2,
- uint8_t u8ReadLen, uint8_t* pData,
- uint8_t* cc);
+ // Provides access to the Crashdump Discovery API in the specified domain
+ EPECIStatus peci_CrashDump_Discovery_dom(uint8_t target, uint8_t domainId,
+ uint8_t subopcode, uint8_t param0,
+ uint16_t param1, uint8_t param2,
+ uint8_t u8ReadLen, uint8_t* pData,
+ uint8_t* cc);
-// Provides access to the Crashdump GetFrame API in the specified domain
-EPECIStatus peci_CrashDump_GetFrame_dom(uint8_t target, uint8_t domainId,
- uint16_t param0, uint16_t param1,
- uint16_t param2, uint8_t u8ReadLen,
- uint8_t* pData, uint8_t* cc);
+ // Provides access to the Crashdump GetFrame API
+ EPECIStatus peci_CrashDump_GetFrame(uint8_t target, uint16_t param0,
+ uint16_t param1, uint16_t param2,
+ uint8_t u8ReadLen, uint8_t* pData,
+ uint8_t* cc);
-// Provides raw PECI command access
-EPECIStatus peci_raw(uint8_t target, uint8_t u8ReadLen, const uint8_t* pRawCmd,
- const uint32_t cmdSize, uint8_t* pRawResp,
- uint32_t respSize);
+ // Provides access to the Crashdump GetFrame API in the specified domain
+ EPECIStatus peci_CrashDump_GetFrame_dom(uint8_t target, uint8_t domainId,
+ uint16_t param0, uint16_t param1,
+ uint16_t param2, uint8_t u8ReadLen,
+ uint8_t* pData, uint8_t* cc);
-EPECIStatus peci_Lock(int* peci_fd, int timeout_ms);
-void peci_Unlock(int peci_fd);
-EPECIStatus peci_Ping(uint8_t target);
-EPECIStatus peci_Ping_seq(uint8_t target, int peci_fd);
-EPECIStatus peci_GetCPUID(const uint8_t clientAddr, CPUModel* cpuModel,
- uint8_t* stepping, uint8_t* cc);
-void peci_SetDevName(char* peci_dev);
+ // Provides raw PECI command access
+ EPECIStatus peci_raw(uint8_t target, uint8_t u8ReadLen,
+ const uint8_t* pRawCmd, const uint32_t cmdSize,
+ uint8_t* pRawResp, uint32_t respSize);
+
+ EPECIStatus peci_Lock(int* peci_fd, int timeout_ms);
+ void peci_Unlock(int peci_fd);
+ EPECIStatus peci_Ping(uint8_t target);
+ EPECIStatus peci_Ping_seq(uint8_t target, int peci_fd);
+ EPECIStatus peci_GetCPUID(const uint8_t clientAddr, CPUModel* cpuModel,
+ uint8_t* stepping, uint8_t* cc);
+ void peci_SetDevName(char* peci_dev);
#ifdef __cplusplus
}
diff --git a/peci_cmds.c b/peci_cmds.c
index ca4f469..a900cf8 100644
--- a/peci_cmds.c
+++ b/peci_cmds.c
@@ -388,9 +388,9 @@
while (loops--)
{
clock_gettime(CLOCK_REALTIME, &begin);
- ret =
- peci_RdPkgConfig_dom(address, domainId, u8PkgIndex, u16PkgParam,
- u8Size, (uint8_t*)&u32PkgValue, &cc);
+ ret = peci_RdPkgConfig_dom(address, domainId, u8PkgIndex,
+ u16PkgParam, u8Size,
+ (uint8_t*)&u32PkgValue, &cc);
timeSpent = getTimeDifference(begin);
if (verbose && measureTime)
{