diff --git a/peci.h b/peci.h
index aa482db..fb46010 100644
--- a/peci.h
+++ b/peci.h
@@ -105,42 +105,97 @@
                              uint8_t u8ReadLen, uint8_t* pPkgConfig,
                              uint8_t* cc);
 
+// Provides read access to the package configuration space within the processor
+// in the specified domain
+EPECIStatus peci_RdPkgConfig_dom(uint8_t target, uint8_t domainId,
+                                 uint8_t u8Index, uint16_t u16Value,
+                                 uint8_t u8ReadLen, uint8_t* pPkgConfig,
+                                 uint8_t* cc);
+
 // Allows sequential RdPkgConfig with the provided peci file descriptor
 EPECIStatus peci_RdPkgConfig_seq(uint8_t target, uint8_t u8Index,
                                  uint16_t u16Value, uint8_t u8ReadLen,
                                  uint8_t* pPkgConfig, int peci_fd, uint8_t* cc);
 
+// Allows sequential RdPkgConfig with the provided peci file descriptor in the
+// specified domain
+EPECIStatus peci_RdPkgConfig_seq_dom(uint8_t target, uint8_t domainId,
+                                     uint8_t u8Index, uint16_t u16Value,
+                                     uint8_t u8ReadLen, uint8_t* pPkgConfig,
+                                     int peci_fd, uint8_t* cc);
+
 // Provides write access to the package configuration space within the processor
 EPECIStatus peci_WrPkgConfig(uint8_t target, uint8_t u8Index, uint16_t u16Param,
                              uint32_t u32Value, uint8_t u8WriteLen,
                              uint8_t* cc);
 
+// Provides write access to the package configuration space within the processor
+// in the specified domain
+EPECIStatus peci_WrPkgConfig_dom(uint8_t target, uint8_t domainId,
+                                 uint8_t u8Index, uint16_t u16Param,
+                                 uint32_t u32Value, uint8_t u8WriteLen,
+                                 uint8_t* cc);
+
 // Allows sequential WrPkgConfig with the provided peci file descriptor
 EPECIStatus peci_WrPkgConfig_seq(uint8_t target, uint8_t u8Index,
                                  uint16_t u16Param, uint32_t u32Value,
                                  uint8_t u8WriteLen, int peci_fd, uint8_t* cc);
 
+// Allows sequential WrPkgConfig with the provided peci file descriptor in the
+// specified domain
+EPECIStatus peci_WrPkgConfig_seq_dom(uint8_t target, uint8_t domainId,
+                                     uint8_t u8Index, uint16_t u16Param,
+                                     uint32_t u32Value, uint8_t u8WriteLen,
+                                     int peci_fd, uint8_t* cc);
+
 // Provides read access to Model Specific Registers
 EPECIStatus peci_RdIAMSR(uint8_t target, uint8_t threadID, uint16_t MSRAddress,
                          uint64_t* u64MsrVal, uint8_t* cc);
 
+// Provides read access to Model Specific Registers in the specified domain
+EPECIStatus peci_RdIAMSR_dom(uint8_t target, uint8_t domainId, uint8_t threadID,
+                             uint16_t MSRAddress, uint64_t* u64MsrVal,
+                             uint8_t* cc);
+
 // Provides read access to PCI Configuration space
 EPECIStatus peci_RdPCIConfig(uint8_t target, uint8_t u8Bus, uint8_t u8Device,
                              uint8_t u8Fcn, uint16_t u16Reg, uint8_t* pPCIReg,
                              uint8_t* cc);
 
+// Provides read access to PCI Configuration space in the specified domain
+EPECIStatus peci_RdPCIConfig_dom(uint8_t target, uint8_t domainId,
+                                 uint8_t u8Bus, uint8_t u8Device, uint8_t u8Fcn,
+                                 uint16_t u16Reg, uint8_t* pPCIReg,
+                                 uint8_t* cc);
+
 // Allows sequential RdPCIConfig with the provided peci file descriptor
 EPECIStatus peci_RdPCIConfig_seq(uint8_t target, uint8_t u8Bus,
                                  uint8_t u8Device, uint8_t u8Fcn,
                                  uint16_t u16Reg, uint8_t* pPCIData,
                                  int peci_fd, uint8_t* cc);
 
+// Allows sequential RdPCIConfig with the provided peci file descriptor in the
+// specified domain
+EPECIStatus peci_RdPCIConfig_seq_dom(uint8_t target, uint8_t domainId,
+                                     uint8_t u8Bus, uint8_t u8Device,
+                                     uint8_t u8Fcn, uint16_t u16Reg,
+                                     uint8_t* pPCIData, int peci_fd,
+                                     uint8_t* cc);
+
 // Provides read access to the local PCI Configuration space
 EPECIStatus peci_RdPCIConfigLocal(uint8_t target, uint8_t u8Bus,
                                   uint8_t u8Device, uint8_t u8Fcn,
                                   uint16_t u16Reg, uint8_t u8ReadLen,
                                   uint8_t* pPCIReg, uint8_t* cc);
 
+// Provides read access to the local PCI Configuration space in the specified
+// domain
+EPECIStatus peci_RdPCIConfigLocal_dom(uint8_t target, uint8_t domainId,
+                                      uint8_t u8Bus, uint8_t u8Device,
+                                      uint8_t u8Fcn, uint16_t u16Reg,
+                                      uint8_t u8ReadLen, uint8_t* pPCIReg,
+                                      uint8_t* cc);
+
 // Allows sequential RdPCIConfigLocal with the provided peci file descriptor
 EPECIStatus peci_RdPCIConfigLocal_seq(uint8_t target, uint8_t u8Bus,
                                       uint8_t u8Device, uint8_t u8Fcn,
@@ -148,12 +203,28 @@
                                       uint8_t* pPCIReg, int peci_fd,
                                       uint8_t* cc);
 
+// Allows sequential RdPCIConfigLocal with the provided peci file descriptor in
+// the specified domain
+EPECIStatus peci_RdPCIConfigLocal_seq_dom(uint8_t target, uint8_t domainId,
+                                          uint8_t u8Bus, uint8_t u8Device,
+                                          uint8_t u8Fcn, uint16_t u16Reg,
+                                          uint8_t u8ReadLen, uint8_t* pPCIReg,
+                                          int peci_fd, uint8_t* cc);
+
 // Provides write access to the local PCI Configuration space
 EPECIStatus peci_WrPCIConfigLocal(uint8_t target, uint8_t u8Bus,
                                   uint8_t u8Device, uint8_t u8Fcn,
                                   uint16_t u16Reg, uint8_t DataLen,
                                   uint32_t DataVal, uint8_t* cc);
 
+// Provides write access to the local PCI Configuration space in the specified
+// domain
+EPECIStatus peci_WrPCIConfigLocal_dom(uint8_t target, uint8_t domainId,
+                                      uint8_t u8Bus, uint8_t u8Device,
+                                      uint8_t u8Fcn, uint16_t u16Reg,
+                                      uint8_t DataLen, uint32_t DataVal,
+                                      uint8_t* cc);
+
 // Provides read access to PCI configuration space
 EPECIStatus peci_RdEndPointConfigPci(uint8_t target, uint8_t u8Seg,
                                      uint8_t u8Bus, uint8_t u8Device,
@@ -161,6 +232,13 @@
                                      uint8_t u8ReadLen, uint8_t* pPCIData,
                                      uint8_t* cc);
 
+// Provides read access to PCI configuration space in the specified domain
+EPECIStatus peci_RdEndPointConfigPci_dom(uint8_t target, uint8_t domainId,
+                                         uint8_t u8Seg, uint8_t u8Bus,
+                                         uint8_t u8Device, uint8_t u8Fcn,
+                                         uint16_t u16Reg, uint8_t u8ReadLen,
+                                         uint8_t* pPCIData, uint8_t* cc);
+
 // Allows sequential RdEndPointConfig to PCI Configuration space
 EPECIStatus peci_RdEndPointConfigPci_seq(uint8_t target, uint8_t u8Seg,
                                          uint8_t u8Bus, uint8_t u8Device,
@@ -168,6 +246,15 @@
                                          uint8_t u8ReadLen, uint8_t* pPCIData,
                                          int peci_fd, uint8_t* cc);
 
+// Allows sequential RdEndPointConfig to PCI Configuration space in the
+// specified domain
+EPECIStatus peci_RdEndPointConfigPci_seq_dom(uint8_t target, uint8_t domainId,
+                                             uint8_t u8Seg, uint8_t u8Bus,
+                                             uint8_t u8Device, uint8_t u8Fcn,
+                                             uint16_t u16Reg, uint8_t u8ReadLen,
+                                             uint8_t* pPCIData, int peci_fd,
+                                             uint8_t* cc);
+
 // Provides read access to the local PCI configuration space
 EPECIStatus peci_RdEndPointConfigPciLocal(uint8_t target, uint8_t u8Seg,
                                           uint8_t u8Bus, uint8_t u8Device,
@@ -175,6 +262,15 @@
                                           uint8_t u8ReadLen, uint8_t* pPCIData,
                                           uint8_t* cc);
 
+// Provides read access to the local PCI configuration space in the specified
+// domain
+EPECIStatus peci_RdEndPointConfigPciLocal_dom(uint8_t target, uint8_t domainId,
+                                              uint8_t u8Seg, uint8_t u8Bus,
+                                              uint8_t u8Device, uint8_t u8Fcn,
+                                              uint16_t u16Reg,
+                                              uint8_t u8ReadLen,
+                                              uint8_t* pPCIData, uint8_t* cc);
+
 // Allows sequential RdEndPointConfig to the local PCI Configuration space
 EPECIStatus peci_RdEndPointConfigPciLocal_seq(uint8_t target, uint8_t u8Seg,
                                               uint8_t u8Bus, uint8_t u8Device,
@@ -183,6 +279,13 @@
                                               uint8_t* pPCIData, int peci_fd,
                                               uint8_t* cc);
 
+// Allows sequential RdEndPointConfig to the local PCI Configuration space in
+// the specified domain
+EPECIStatus peci_RdEndPointConfigPciLocal_seq_dom(
+    uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+    uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg, uint8_t u8ReadLen,
+    uint8_t* pPCIData, int peci_fd, uint8_t* cc);
+
 // Provides read access to PCI MMIO space
 EPECIStatus peci_RdEndPointConfigMmio(uint8_t target, uint8_t u8Seg,
                                       uint8_t u8Bus, uint8_t u8Device,
@@ -191,12 +294,27 @@
                                       uint8_t u8ReadLen, uint8_t* pMmioData,
                                       uint8_t* cc);
 
+// Provides read access to PCI MMIO space in the specified domain
+EPECIStatus peci_RdEndPointConfigMmio_dom(uint8_t target, uint8_t domainId,
+                                          uint8_t u8Seg, uint8_t u8Bus,
+                                          uint8_t u8Device, uint8_t u8Fcn,
+                                          uint8_t u8Bar, uint8_t u8AddrType,
+                                          uint64_t u64Offset, uint8_t u8ReadLen,
+                                          uint8_t* pMmioData, uint8_t* cc);
+
 // Allows sequential RdEndPointConfig to PCI MMIO space
 EPECIStatus peci_RdEndPointConfigMmio_seq(
     uint8_t target, uint8_t u8Seg, uint8_t u8Bus, uint8_t u8Device,
     uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType, uint64_t u64Offset,
     uint8_t u8ReadLen, uint8_t* pMmioData, int peci_fd, uint8_t* cc);
 
+// Allows sequential RdEndPointConfig to PCI MMIO space in the specified domain
+EPECIStatus peci_RdEndPointConfigMmio_seq_dom(
+    uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+    uint8_t u8Device, uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType,
+    uint64_t u64Offset, uint8_t u8ReadLen, uint8_t* pMmioData, int peci_fd,
+    uint8_t* cc);
+
 // Provides write access to the EP local PCI Configuration space
 EPECIStatus peci_WrEndPointPCIConfigLocal(uint8_t target, uint8_t u8Seg,
                                           uint8_t u8Bus, uint8_t u8Device,
@@ -204,6 +322,14 @@
                                           uint8_t DataLen, uint32_t DataVal,
                                           uint8_t* cc);
 
+// Provides write access to the EP local PCI Configuration space in the
+// specified domain
+EPECIStatus peci_WrEndPointPCIConfigLocal_dom(uint8_t target, uint8_t domainId,
+                                              uint8_t u8Seg, uint8_t u8Bus,
+                                              uint8_t u8Device, uint8_t u8Fcn,
+                                              uint16_t u16Reg, uint8_t DataLen,
+                                              uint32_t DataVal, uint8_t* cc);
+
 // Provides write access to the EP PCI Configuration space
 EPECIStatus peci_WrEndPointPCIConfig(uint8_t target, uint8_t u8Seg,
                                      uint8_t u8Bus, uint8_t u8Device,
@@ -211,6 +337,14 @@
                                      uint8_t DataLen, uint32_t DataVal,
                                      uint8_t* cc);
 
+// Provides write access to the EP PCI Configuration space in the specified
+// domain
+EPECIStatus peci_WrEndPointPCIConfig_dom(uint8_t target, uint8_t domainId,
+                                         uint8_t u8Seg, uint8_t u8Bus,
+                                         uint8_t u8Device, uint8_t u8Fcn,
+                                         uint16_t u16Reg, uint8_t DataLen,
+                                         uint32_t DataVal, uint8_t* cc);
+
 // Allows sequential write access to the EP PCI Configuration space
 EPECIStatus peci_WrEndPointConfig_seq(uint8_t target, uint8_t u8MsgType,
                                       uint8_t u8Seg, uint8_t u8Bus,
@@ -219,6 +353,15 @@
                                       uint32_t DataVal, int peci_fd,
                                       uint8_t* cc);
 
+// Allows sequential write access to the EP PCI Configuration space in the
+// specified domain
+EPECIStatus peci_WrEndPointConfig_seq_dom(uint8_t target, uint8_t domainId,
+                                          uint8_t u8MsgType, uint8_t u8Seg,
+                                          uint8_t u8Bus, uint8_t u8Device,
+                                          uint8_t u8Fcn, uint16_t u16Reg,
+                                          uint8_t DataLen, uint32_t DataVal,
+                                          int peci_fd, uint8_t* cc);
+
 // Provides write access to the EP PCI MMIO space
 EPECIStatus peci_WrEndPointConfigMmio(uint8_t target, uint8_t u8Seg,
                                       uint8_t u8Bus, uint8_t u8Device,
@@ -227,24 +370,53 @@
                                       uint8_t u8DataLen, uint64_t u64DataVal,
                                       uint8_t* cc);
 
+// Provides write access to the EP PCI MMIO space in the specified domain
+EPECIStatus peci_WrEndPointConfigMmio_dom(uint8_t target, uint8_t domainId,
+                                          uint8_t u8Seg, uint8_t u8Bus,
+                                          uint8_t u8Device, uint8_t u8Fcn,
+                                          uint8_t u8Bar, uint8_t u8AddrType,
+                                          uint64_t u64Offset, uint8_t u8DataLen,
+                                          uint64_t u64DataVal, uint8_t* cc);
+
 // Allows sequential write access to the EP PCI MMIO space
 EPECIStatus peci_WrEndPointConfigMmio_seq(
     uint8_t target, uint8_t u8Seg, uint8_t u8Bus, uint8_t u8Device,
     uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType, uint64_t u64Offset,
     uint8_t u8DataLen, uint64_t u64DataVal, int peci_fd, uint8_t* cc);
 
+// Allows sequential write access to the EP PCI MMIO space in the specified
+// domain
+EPECIStatus peci_WrEndPointConfigMmio_seq_dom(
+    uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+    uint8_t u8Device, uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType,
+    uint64_t u64Offset, uint8_t u8DataLen, uint64_t u64DataVal, int peci_fd,
+    uint8_t* cc);
+
 // Provides access to the Crashdump Discovery API
 EPECIStatus peci_CrashDump_Discovery(uint8_t target, uint8_t subopcode,
                                      uint8_t param0, uint16_t param1,
                                      uint8_t param2, uint8_t u8ReadLen,
                                      uint8_t* pData, uint8_t* cc);
 
+// Provides access to the Crashdump Discovery API in the specified domain
+EPECIStatus peci_CrashDump_Discovery_dom(uint8_t target, uint8_t domainId,
+                                         uint8_t subopcode, uint8_t param0,
+                                         uint16_t param1, uint8_t param2,
+                                         uint8_t u8ReadLen, uint8_t* pData,
+                                         uint8_t* cc);
+
 // Provides access to the Crashdump GetFrame API
 EPECIStatus peci_CrashDump_GetFrame(uint8_t target, uint16_t param0,
                                     uint16_t param1, uint16_t param2,
                                     uint8_t u8ReadLen, uint8_t* pData,
                                     uint8_t* cc);
 
+// Provides access to the Crashdump GetFrame API in the specified domain
+EPECIStatus peci_CrashDump_GetFrame_dom(uint8_t target, uint8_t domainId,
+                                        uint16_t param0, uint16_t param1,
+                                        uint16_t param2, uint8_t u8ReadLen,
+                                        uint8_t* pData, uint8_t* cc);
+
 // Provides raw PECI command access
 EPECIStatus peci_raw(uint8_t target, uint8_t u8ReadLen, const uint8_t* pRawCmd,
                      const uint32_t cmdSize, uint8_t* pRawResp,