diff --git a/linux/peci-ioctl.h b/linux/peci-ioctl.h
index ab7c023..9b1dc53 100644
--- a/linux/peci-ioctl.h
+++ b/linux/peci-ioctl.h
@@ -161,6 +161,7 @@
  * @rx_len: number of data to be read in bytes
  * @cc: completion code
  * @pkg_config: package config data to be read
+ * @domain_id: domain ID of the client
  *
  * The RdPkgConfig() command provides read access to the Package Configuration
  * Space (PCS) within the processor, including various power and thermal
@@ -240,6 +241,8 @@
 	__u8	cc;
 	__u8	padding[2];
 	__u8	pkg_config[4];
+	__u8	domain_id;
+	__u8	padding1[3];
 } __attribute__((__packed__));
 
 /**
@@ -250,6 +253,7 @@
  * @tx_len: number of data to be written in bytes
  * @cc: completion code
  * @value: package config data to be written
+ * @domain_id: domain ID of the client
  *
  * The WrPkgConfig() command provides write access to the Package Configuration
  * Space (PCS) within the processor, including various power and thermal
@@ -272,6 +276,8 @@
 	__u8	cc;
 	__u8	padding[2];
 	__u32	value;
+	__u8	domain_id;
+	__u8	padding1[3];
 } __attribute__((__packed__));
 
 /**
@@ -281,6 +287,7 @@
  * @address: address of MSR to read from
  * @cc: completion code
  * @value: data to be read
+ * @domain_id: domain ID of the client
  *
  * The RdIAMSR() PECI command provides read access to Model Specific Registers
  * (MSRs) defined in the processor's Intel Architecture (IA).
@@ -296,6 +303,8 @@
 	__u8	cc;
 	__u8	padding[3];
 	__u64	value;
+	__u8	domain_id;
+	__u8	padding1[3];
 } __attribute__((__packed__));
 
 /**
@@ -306,6 +315,7 @@
  * @tx_len: number of data to be written in bytes
  * @cc: completion code
  * @value: data to be written
+ * @domain_id: domain ID of the client
  *
  * The WrIAMSR() PECI command provides write access to Model Specific Registers
  * (MSRs) defined in the processor's Intel Architecture (IA).
@@ -320,6 +330,8 @@
 	__u8	cc;
 	__u8	padding[2];
 	__u64	value;
+	__u8	domain_id;
+	__u8	padding1[3];
 } __attribute__((__packed__));
 
 /**
@@ -329,6 +341,7 @@
  * @address: address of MSR to read from
  * @cc: completion code
  * @value: data to be read
+ * @domain_id: domain ID of the client
  *
  * The RdIAMSREX() PECI command provides read access to Model Specific
  * Registers (MSRs) defined in the processor's Intel Architecture (IA).
@@ -348,6 +361,8 @@
 	__u8	cc;
 	__u8	padding1;
 	__u64	value;
+	__u8	domain_id;
+	__u8	padding2[3];
 } __attribute__((__packed__));
 
 /**
@@ -359,6 +374,7 @@
  * @reg: specific register to read from
  * @cc: completion code
  * @pci_config: config data to be read
+ * @domain_id: domain ID of the client
  *
  * The RdPCIConfig() command provides sideband read access to the PCI
  * configuration space maintained in downstream devices external to the
@@ -387,6 +403,8 @@
 	__u8	cc;
 	__u8	padding[1];
 	__u8	pci_config[4];
+	__u8	domain_id;
+	__u8	padding1[3];
 } __attribute__((__packed__));
 
 /**
@@ -399,6 +417,7 @@
  * @tx_len: number of data to be written in bytes
  * @cc: completion code
  * @pci_config: config data to be written
+ * @domain_id: domain ID of the client
  *
  * The RdPCIConfig() command provides sideband write access to the PCI
  * configuration space maintained in downstream devices external to the
@@ -415,6 +434,8 @@
 	__u8	tx_len;
 	__u8	cc;
 	__u8	pci_config[4];
+	__u8	domain_id;
+	__u8	padding[3];
 } __attribute__((__packed__));
 
 /**
@@ -427,6 +448,7 @@
  * @rx_len: number of data to be read in bytes
  * @cc: completion code
  * @pci_config: config data to be read
+ * @domain_id: domain ID of the client
  *
  * The RdPCIConfigLocal() command provides sideband read access to the PCI
  * configuration space that resides within the processor. This includes all
@@ -445,6 +467,8 @@
 	__u8	rx_len;
 	__u8	cc;
 	__u8	pci_config[4];
+	__u8	domain_id;
+	__u8	padding[3];
 } __attribute__((__packed__));
 
 /**
@@ -457,6 +481,7 @@
  * @tx_len: number of data to be written in bytes
  * @cc: completion code
  * @value: config data to be written
+ * @domain_id: domain ID of the client
  *
  * The WrPCIConfigLocal() command provides sideband write access to the PCI
  * configuration space that resides within the processor. PECI originators can
@@ -475,6 +500,8 @@
 	__u8	tx_len;
 	__u8	cc;
 	__u32	value;
+	__u8	domain_id;
+	__u8	padding[3];
 } __attribute__((__packed__));
 
 struct peci_rd_end_pt_cfg_msg {
@@ -516,6 +543,8 @@
 	__u8	cc;
 	__u8	padding[2];
 	__u8	data[8];
+	__u8	domain_id;
+	__u8	padding1[3];
 } __attribute__((__packed__));
 
 struct peci_wr_end_pt_cfg_msg {
@@ -553,6 +582,8 @@
 	__u8	cc;
 	__u8	padding[2];
 	__u64	value;
+	__u8	domain_id;
+	__u8	padding1[3];
 } __attribute__((__packed__));
 
 /* Crashdump Agent */
@@ -579,6 +610,8 @@
 	__u8	param2;
 	__u8	rx_len;
 	__u8	data[8];
+	__u8	domain_id;
+	__u8	padding[3];
 } __attribute__((__packed__));
 
 struct peci_crashdump_get_frame_msg {
@@ -601,6 +634,8 @@
 	__u8	cc;
 	__u8	padding1[2];
 	__u8	data[16];
+	__u8	domain_id;
+	__u8	padding2[3];
 } __attribute__((__packed__));
 
 #define PECI_IOC_BASE	0xb8
diff --git a/peci.c b/peci.c
index 35f74f5..0d6a47a 100644
--- a/peci.c
+++ b/peci.c
@@ -397,6 +397,20 @@
                              uint8_t u8ReadLen, uint8_t* pPkgConfig,
                              uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_RdPkgConfig_dom(target, 0, u8Index, u16Value, u8ReadLen,
+                                pPkgConfig, cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function provides read access to the package configuration
+ * space within the processor in the specified domain.
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_RdPkgConfig_dom(uint8_t target, uint8_t domainId,
+                                 uint8_t u8Index, uint16_t u16Value,
+                                 uint8_t u8ReadLen, uint8_t* pPkgConfig,
+                                 uint8_t* cc)
+{
     int peci_fd = -1;
     EPECIStatus ret = PECI_CC_SUCCESS;
 
@@ -415,8 +429,8 @@
     {
         return PECI_CC_DRIVER_ERR;
     }
-    ret = peci_RdPkgConfig_seq(target, u8Index, u16Value, u8ReadLen, pPkgConfig,
-                               peci_fd, cc);
+    ret = peci_RdPkgConfig_seq_dom(target, domainId, u8Index, u16Value,
+                                   u8ReadLen, pPkgConfig, peci_fd, cc);
 
     peci_Close(peci_fd);
     return ret;
@@ -430,6 +444,20 @@
                                  uint16_t u16Value, uint8_t u8ReadLen,
                                  uint8_t* pPkgConfig, int peci_fd, uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_RdPkgConfig_seq_dom(target, 0, u8Index, u16Value, u8ReadLen,
+                                    pPkgConfig, peci_fd, cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function allows sequential RdPkgConfig with the provided
+ * peci file descriptor in the specified domain.
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_RdPkgConfig_seq_dom(uint8_t target, uint8_t domainId,
+                                     uint8_t u8Index, uint16_t u16Value,
+                                     uint8_t u8ReadLen, uint8_t* pPkgConfig,
+                                     int peci_fd, uint8_t* cc)
+{
     struct peci_rd_pkg_cfg_msg cmd = {0};
     EPECIStatus ret = PECI_CC_SUCCESS;
 
@@ -460,6 +488,7 @@
     cmd.index = u8Index;  // RdPkgConfig index
     cmd.param = u16Value; // Config parameter value
     cmd.rx_len = u8ReadLen;
+    cmd.domain_id = domainId;
 
     ret = HW_peci_issue_cmd(PECI_IOC_RD_PKG_CFG, (char*)&cmd, peci_fd);
     *cc = cmd.cc;
@@ -478,6 +507,20 @@
 EPECIStatus peci_WrPkgConfig(uint8_t target, uint8_t u8Index, uint16_t u16Param,
                              uint32_t u32Value, uint8_t u8WriteLen, uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_WrPkgConfig_dom(target, 0, u8Index, u16Param, u32Value,
+                                u8WriteLen, cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function provides write access to the package configuration
+ * space within the processor in the specified domain
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_WrPkgConfig_dom(uint8_t target, uint8_t domainId,
+                                 uint8_t u8Index, uint16_t u16Param,
+                                 uint32_t u32Value, uint8_t u8WriteLen,
+                                 uint8_t* cc)
+{
     int peci_fd = -1;
     EPECIStatus ret = PECI_CC_SUCCESS;
 
@@ -496,8 +539,8 @@
     {
         return PECI_CC_DRIVER_ERR;
     }
-    ret = peci_WrPkgConfig_seq(target, u8Index, u16Param, u32Value, u8WriteLen,
-                               peci_fd, cc);
+    ret = peci_WrPkgConfig_seq_dom(target, domainId, u8Index, u16Param,
+                                   u32Value, u8WriteLen, peci_fd, cc);
 
     peci_Close(peci_fd);
     return ret;
@@ -511,6 +554,20 @@
                                  uint16_t u16Param, uint32_t u32Value,
                                  uint8_t u8WriteLen, int peci_fd, uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_WrPkgConfig_seq_dom(target, 0, u8Index, u16Param, u32Value,
+                                    u8WriteLen, peci_fd, cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function allows sequential WrPkgConfig with the provided
+ * peci file descriptor in the specified domain.
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_WrPkgConfig_seq_dom(uint8_t target, uint8_t domainId,
+                                     uint8_t u8Index, uint16_t u16Param,
+                                     uint32_t u32Value, uint8_t u8WriteLen,
+                                     int peci_fd, uint8_t* cc)
+{
     struct peci_wr_pkg_cfg_msg cmd = {0};
     EPECIStatus ret = PECI_CC_SUCCESS;
 
@@ -536,6 +593,7 @@
     cmd.param = u16Param; // parameter value
     cmd.tx_len = u8WriteLen;
     cmd.value = u32Value;
+    cmd.domain_id = domainId;
 
     ret = HW_peci_issue_cmd(PECI_IOC_WR_PKG_CFG, (char*)&cmd, peci_fd);
     *cc = cmd.cc;
@@ -550,6 +608,18 @@
 EPECIStatus peci_RdIAMSR(uint8_t target, uint8_t threadID, uint16_t MSRAddress,
                          uint64_t* u64MsrVal, uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_RdIAMSR_dom(target, 0, threadID, MSRAddress, u64MsrVal, cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function provides read access to Model Specific Registers
+ * defined in the processor doc in the specified domain.
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_RdIAMSR_dom(uint8_t target, uint8_t domainId, uint8_t threadID,
+                             uint16_t MSRAddress, uint64_t* u64MsrVal,
+                             uint8_t* cc)
+{
     int peci_fd = -1;
     struct peci_rd_ia_msr_msg cmd = {0};
     EPECIStatus ret = PECI_CC_SUCCESS;
@@ -573,6 +643,7 @@
     cmd.addr = target;
     cmd.thread_id = threadID; // request byte for thread ID
     cmd.address = MSRAddress; // MSR Address
+    cmd.domain_id = domainId;
 
     ret = HW_peci_issue_cmd(PECI_IOC_RD_IA_MSR, (char*)&cmd, peci_fd);
     *cc = cmd.cc;
@@ -593,6 +664,20 @@
                              uint8_t u8Fcn, uint16_t u16Reg, uint8_t* pPCIData,
                              uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_RdPCIConfig_dom(target, 0, u8Bus, u8Device, u8Fcn, u16Reg,
+                                pPCIData, cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function provides read access to the PCI configuration space at
+ * the requested PCI configuration address in the specified domain.
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_RdPCIConfig_dom(uint8_t target, uint8_t domainId,
+                                 uint8_t u8Bus, uint8_t u8Device, uint8_t u8Fcn,
+                                 uint16_t u16Reg, uint8_t* pPCIData,
+                                 uint8_t* cc)
+{
     int peci_fd = -1;
     EPECIStatus ret = PECI_CC_SUCCESS;
 
@@ -611,8 +696,8 @@
     {
         return PECI_CC_DRIVER_ERR;
     }
-    ret = peci_RdPCIConfig_seq(target, u8Bus, u8Device, u8Fcn, u16Reg, pPCIData,
-                               peci_fd, cc);
+    ret = peci_RdPCIConfig_seq_dom(target, domainId, u8Bus, u8Device, u8Fcn,
+                                   u16Reg, pPCIData, peci_fd, cc);
 
     peci_Close(peci_fd);
     return ret;
@@ -627,6 +712,21 @@
                                  uint16_t u16Reg, uint8_t* pPCIData,
                                  int peci_fd, uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_RdPCIConfig_seq_dom(target, 0, u8Bus, u8Device, u8Fcn, u16Reg,
+                                    pPCIData, peci_fd, cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function allows sequential RdPCIConfig with the provided
+ * peci file descriptor in the specified domain.
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_RdPCIConfig_seq_dom(uint8_t target, uint8_t domainId,
+                                     uint8_t u8Bus, uint8_t u8Device,
+                                     uint8_t u8Fcn, uint16_t u16Reg,
+                                     uint8_t* pPCIData, int peci_fd,
+                                     uint8_t* cc)
+{
     struct peci_rd_pci_cfg_msg cmd = {0};
     EPECIStatus ret = PECI_CC_SUCCESS;
 
@@ -652,6 +752,7 @@
     cmd.device = u8Device;
     cmd.function = u8Fcn;
     cmd.reg = u16Reg;
+    cmd.domain_id = domainId;
 
     ret = HW_peci_issue_cmd(PECI_IOC_RD_PCI_CFG, (char*)&cmd, peci_fd);
     *cc = cmd.cc;
@@ -665,13 +766,28 @@
 }
 
 /*-------------------------------------------------------------------------
- *  This function provides read access to the local PCI configuration space
+ * This function provides read access to the local PCI configuration space
  *------------------------------------------------------------------------*/
 EPECIStatus peci_RdPCIConfigLocal(uint8_t target, uint8_t u8Bus,
                                   uint8_t u8Device, uint8_t u8Fcn,
                                   uint16_t u16Reg, uint8_t u8ReadLen,
                                   uint8_t* pPCIReg, uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_RdPCIConfigLocal_dom(target, 0, u8Bus, u8Device, u8Fcn, u16Reg,
+                                     u8ReadLen, pPCIReg, cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function provides read access to the local PCI configuration space in
+ * the specified domain
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_RdPCIConfigLocal_dom(uint8_t target, uint8_t domainId,
+                                      uint8_t u8Bus, uint8_t u8Device,
+                                      uint8_t u8Fcn, uint16_t u16Reg,
+                                      uint8_t u8ReadLen, uint8_t* pPCIReg,
+                                      uint8_t* cc)
+{
     int peci_fd = -1;
     EPECIStatus ret = PECI_CC_SUCCESS;
 
@@ -690,8 +806,9 @@
     {
         return PECI_CC_DRIVER_ERR;
     }
-    ret = peci_RdPCIConfigLocal_seq(target, u8Bus, u8Device, u8Fcn, u16Reg,
-                                    u8ReadLen, pPCIReg, peci_fd, cc);
+    ret =
+        peci_RdPCIConfigLocal_seq_dom(target, domainId, u8Bus, u8Device, u8Fcn,
+                                      u16Reg, u8ReadLen, pPCIReg, peci_fd, cc);
 
     peci_Close(peci_fd);
     return ret;
@@ -707,6 +824,22 @@
                                       uint8_t* pPCIReg, int peci_fd,
                                       uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_RdPCIConfigLocal_seq_dom(target, 0, u8Bus, u8Device, u8Fcn,
+                                         u16Reg, u8ReadLen, pPCIReg, peci_fd,
+                                         cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function allows sequential RdPCIConfigLocal with the provided
+ * peci file descriptor in the specified domain.
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_RdPCIConfigLocal_seq_dom(uint8_t target, uint8_t domainId,
+                                          uint8_t u8Bus, uint8_t u8Device,
+                                          uint8_t u8Fcn, uint16_t u16Reg,
+                                          uint8_t u8ReadLen, uint8_t* pPCIReg,
+                                          int peci_fd, uint8_t* cc)
+{
     struct peci_rd_pci_cfg_local_msg cmd = {0};
     EPECIStatus ret = PECI_CC_SUCCESS;
 
@@ -739,6 +872,7 @@
     cmd.function = u8Fcn;
     cmd.reg = u16Reg;
     cmd.rx_len = u8ReadLen;
+    cmd.domain_id = domainId;
 
     ret = HW_peci_issue_cmd(PECI_IOC_RD_PCI_CFG_LOCAL, (char*)&cmd, peci_fd);
     *cc = cmd.cc;
@@ -752,13 +886,28 @@
 }
 
 /*-------------------------------------------------------------------------
- *  This function provides write access to the local PCI configuration space
+ * This function provides write access to the local PCI configuration space
  *------------------------------------------------------------------------*/
 EPECIStatus peci_WrPCIConfigLocal(uint8_t target, uint8_t u8Bus,
                                   uint8_t u8Device, uint8_t u8Fcn,
                                   uint16_t u16Reg, uint8_t DataLen,
                                   uint32_t DataVal, uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_WrPCIConfigLocal_dom(target, 0, u8Bus, u8Device, u8Fcn, u16Reg,
+                                     DataLen, DataVal, cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function provides write access to the local PCI configuration space in
+ * the specified domain
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_WrPCIConfigLocal_dom(uint8_t target, uint8_t domainId,
+                                      uint8_t u8Bus, uint8_t u8Device,
+                                      uint8_t u8Fcn, uint16_t u16Reg,
+                                      uint8_t DataLen, uint32_t DataVal,
+                                      uint8_t* cc)
+{
     int peci_fd = -1;
     struct peci_wr_pci_cfg_local_msg cmd = {0};
     EPECIStatus ret = PECI_CC_SUCCESS;
@@ -793,6 +942,7 @@
     cmd.reg = u16Reg;
     cmd.tx_len = DataLen;
     cmd.value = DataVal;
+    cmd.domain_id = domainId;
 
     ret = HW_peci_issue_cmd(PECI_IOC_WR_PCI_CFG_LOCAL, (char*)&cmd, peci_fd);
     *cc = cmd.cc;
@@ -802,12 +952,13 @@
 }
 
 /*-------------------------------------------------------------------------
- * This internal function is the common interface for RdEndPointConfig to PCI
+ * This internal function is the common interface for RdEndPointConfig to PCI in
+ * the specified domain
  *------------------------------------------------------------------------*/
-static EPECIStatus peci_RdEndPointConfigPciCommon(
-    uint8_t target, uint8_t u8MsgType, uint8_t u8Seg, uint8_t u8Bus,
-    uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg, uint8_t u8ReadLen,
-    uint8_t* pPCIData, int peci_fd, uint8_t* cc)
+static EPECIStatus peci_RdEndPointConfigPciCommon_dom(
+    uint8_t target, uint8_t domainId, uint8_t u8MsgType, uint8_t u8Seg,
+    uint8_t u8Bus, uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg,
+    uint8_t u8ReadLen, uint8_t* pPCIData, int peci_fd, uint8_t* cc)
 {
     struct peci_rd_end_pt_cfg_msg cmd = {0};
     EPECIStatus ret = PECI_CC_SUCCESS;
@@ -837,6 +988,7 @@
     cmd.params.pci_cfg.function = u8Fcn;
     cmd.params.pci_cfg.reg = u16Reg;
     cmd.rx_len = u8ReadLen;
+    cmd.domain_id = domainId;
 
     ret = HW_peci_issue_cmd(PECI_IOC_RD_END_PT_CFG, (char*)&cmd, peci_fd);
     *cc = cmd.cc;
@@ -863,6 +1015,21 @@
                                      uint8_t u8ReadLen, uint8_t* pPCIData,
                                      uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_RdEndPointConfigPci_dom(target, 0, u8Seg, u8Bus, u8Device,
+                                        u8Fcn, u16Reg, u8ReadLen, pPCIData, cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function provides read access to the PCI configuration space at
+ * the requested PCI configuration address in the specified domain.
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_RdEndPointConfigPci_dom(uint8_t target, uint8_t domainId,
+                                         uint8_t u8Seg, uint8_t u8Bus,
+                                         uint8_t u8Device, uint8_t u8Fcn,
+                                         uint16_t u16Reg, uint8_t u8ReadLen,
+                                         uint8_t* pPCIData, uint8_t* cc)
+{
     int peci_fd = -1;
     EPECIStatus ret = PECI_CC_SUCCESS;
 
@@ -881,9 +1048,9 @@
     {
         return PECI_CC_DRIVER_ERR;
     }
-    ret =
-        peci_RdEndPointConfigPci_seq(target, u8Seg, u8Bus, u8Device, u8Fcn,
-                                     u16Reg, u8ReadLen, pPCIData, peci_fd, cc);
+    ret = peci_RdEndPointConfigPci_seq_dom(target, domainId, u8Seg, u8Bus,
+                                           u8Device, u8Fcn, u16Reg, u8ReadLen,
+                                           pPCIData, peci_fd, cc);
     peci_Close(peci_fd);
     return ret;
 }
@@ -898,6 +1065,23 @@
                                          uint8_t u8ReadLen, uint8_t* pPCIData,
                                          int peci_fd, uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_RdEndPointConfigPci_seq_dom(target, 0, u8Seg, u8Bus, u8Device,
+                                            u8Fcn, u16Reg, u8ReadLen, pPCIData,
+                                            peci_fd, cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function allows sequential RdEndPointConfig to PCI with the provided
+ * peci file descriptor in the specified domain.
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_RdEndPointConfigPci_seq_dom(uint8_t target, uint8_t domainId,
+                                             uint8_t u8Seg, uint8_t u8Bus,
+                                             uint8_t u8Device, uint8_t u8Fcn,
+                                             uint16_t u16Reg, uint8_t u8ReadLen,
+                                             uint8_t* pPCIData, int peci_fd,
+                                             uint8_t* cc)
+{
     if (pPCIData == NULL || cc == NULL)
     {
         return PECI_CC_INVALID_REQ;
@@ -915,9 +1099,9 @@
         return PECI_CC_INVALID_REQ;
     }
 
-    return peci_RdEndPointConfigPciCommon(target, PECI_ENDPTCFG_TYPE_PCI, u8Seg,
-                                          u8Bus, u8Device, u8Fcn, u16Reg,
-                                          u8ReadLen, pPCIData, peci_fd, cc);
+    return peci_RdEndPointConfigPciCommon_dom(
+        target, domainId, PECI_ENDPTCFG_TYPE_PCI, u8Seg, u8Bus, u8Device, u8Fcn,
+        u16Reg, u8ReadLen, pPCIData, peci_fd, cc);
 }
 
 /*-------------------------------------------------------------------------
@@ -930,6 +1114,23 @@
                                           uint8_t u8ReadLen, uint8_t* pPCIData,
                                           uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_RdEndPointConfigPciLocal_dom(target, 0, u8Seg, u8Bus, u8Device,
+                                             u8Fcn, u16Reg, u8ReadLen, pPCIData,
+                                             cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function provides read access to the Local PCI configuration space at
+ * the requested PCI configuration address in the specified domain.
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_RdEndPointConfigPciLocal_dom(uint8_t target, uint8_t domainId,
+                                              uint8_t u8Seg, uint8_t u8Bus,
+                                              uint8_t u8Device, uint8_t u8Fcn,
+                                              uint16_t u16Reg,
+                                              uint8_t u8ReadLen,
+                                              uint8_t* pPCIData, uint8_t* cc)
+{
     int peci_fd = -1;
     EPECIStatus ret = PECI_CC_SUCCESS;
 
@@ -948,16 +1149,16 @@
     {
         return PECI_CC_DRIVER_ERR;
     }
-    ret = peci_RdEndPointConfigPciLocal_seq(target, u8Seg, u8Bus, u8Device,
-                                            u8Fcn, u16Reg, u8ReadLen, pPCIData,
-                                            peci_fd, cc);
+    ret = peci_RdEndPointConfigPciLocal_seq_dom(
+        target, domainId, u8Seg, u8Bus, u8Device, u8Fcn, u16Reg, u8ReadLen,
+        pPCIData, peci_fd, cc);
     peci_Close(peci_fd);
     return ret;
 }
 
 /*-------------------------------------------------------------------------
  * This function allows sequential RdEndPointConfig to PCI Local with the
- *provided peci file descriptor.
+ * provided peci file descriptor.
  *------------------------------------------------------------------------*/
 EPECIStatus peci_RdEndPointConfigPciLocal_seq(uint8_t target, uint8_t u8Seg,
                                               uint8_t u8Bus, uint8_t u8Device,
@@ -966,6 +1167,21 @@
                                               uint8_t* pPCIData, int peci_fd,
                                               uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_RdEndPointConfigPciLocal_seq_dom(
+        target, 0, u8Seg, u8Bus, u8Device, u8Fcn, u16Reg, u8ReadLen, pPCIData,
+        peci_fd, cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function allows sequential RdEndPointConfig to PCI Local with the
+ * provided peci file descriptor in the specified domain.
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_RdEndPointConfigPciLocal_seq_dom(
+    uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+    uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg, uint8_t u8ReadLen,
+    uint8_t* pPCIData, int peci_fd, uint8_t* cc)
+{
     if (pPCIData == NULL || cc == NULL)
     {
         return PECI_CC_INVALID_REQ;
@@ -983,9 +1199,9 @@
         return PECI_CC_INVALID_REQ;
     }
 
-    return peci_RdEndPointConfigPciCommon(target, PECI_ENDPTCFG_TYPE_LOCAL_PCI,
-                                          u8Seg, u8Bus, u8Device, u8Fcn, u16Reg,
-                                          u8ReadLen, pPCIData, peci_fd, cc);
+    return peci_RdEndPointConfigPciCommon_dom(
+        target, domainId, PECI_ENDPTCFG_TYPE_LOCAL_PCI, u8Seg, u8Bus, u8Device,
+        u8Fcn, u16Reg, u8ReadLen, pPCIData, peci_fd, cc);
 }
 
 /*-------------------------------------------------------------------------
@@ -999,6 +1215,23 @@
                                       uint8_t u8ReadLen, uint8_t* pMmioData,
                                       uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_RdEndPointConfigMmio_dom(target, 0, u8Seg, u8Bus, u8Device,
+                                         u8Fcn, u8Bar, u8AddrType, u64Offset,
+                                         u8ReadLen, pMmioData, cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function provides read access to PCI MMIO space at
+ * the requested PCI configuration address in the specified domain.
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_RdEndPointConfigMmio_dom(uint8_t target, uint8_t domainId,
+                                          uint8_t u8Seg, uint8_t u8Bus,
+                                          uint8_t u8Device, uint8_t u8Fcn,
+                                          uint8_t u8Bar, uint8_t u8AddrType,
+                                          uint64_t u64Offset, uint8_t u8ReadLen,
+                                          uint8_t* pMmioData, uint8_t* cc)
+{
     int peci_fd = -1;
     EPECIStatus ret = PECI_CC_SUCCESS;
 
@@ -1017,22 +1250,38 @@
     {
         return PECI_CC_DRIVER_ERR;
     }
-    ret = peci_RdEndPointConfigMmio_seq(target, u8Seg, u8Bus, u8Device, u8Fcn,
-                                        u8Bar, u8AddrType, u64Offset, u8ReadLen,
-                                        pMmioData, peci_fd, cc);
+    ret = peci_RdEndPointConfigMmio_seq_dom(
+        target, domainId, u8Seg, u8Bus, u8Device, u8Fcn, u8Bar, u8AddrType,
+        u64Offset, u8ReadLen, pMmioData, peci_fd, cc);
     peci_Close(peci_fd);
     return ret;
 }
 
 /*-------------------------------------------------------------------------
  * This function allows sequential RdEndPointConfig to PCI MMIO with the
- *provided peci file descriptor.
+ * provided peci file descriptor.
  *------------------------------------------------------------------------*/
 EPECIStatus peci_RdEndPointConfigMmio_seq(
     uint8_t target, uint8_t u8Seg, uint8_t u8Bus, uint8_t u8Device,
     uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType, uint64_t u64Offset,
     uint8_t u8ReadLen, uint8_t* pMmioData, int peci_fd, uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_RdEndPointConfigMmio_seq_dom(
+        target, 0, u8Seg, u8Bus, u8Device, u8Fcn, u8Bar, u8AddrType, u64Offset,
+        u8ReadLen, pMmioData, peci_fd, cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function allows sequential RdEndPointConfig to PCI MMIO with the
+ * provided peci file descriptor in the specified domain.
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_RdEndPointConfigMmio_seq_dom(
+    uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+    uint8_t u8Device, uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType,
+    uint64_t u64Offset, uint8_t u8ReadLen, uint8_t* pMmioData, int peci_fd,
+    uint8_t* cc)
+{
     struct peci_rd_end_pt_cfg_msg cmd = {0};
     EPECIStatus ret = PECI_CC_SUCCESS;
 
@@ -1069,6 +1318,7 @@
     cmd.params.mmio.addr_type = u8AddrType;
     cmd.params.mmio.offset = u64Offset;
     cmd.rx_len = u8ReadLen;
+    cmd.domain_id = domainId;
 
     ret = HW_peci_issue_cmd(PECI_IOC_RD_END_PT_CFG, (char*)&cmd, peci_fd);
     *cc = cmd.cc;
@@ -1087,7 +1337,7 @@
 
 /*-------------------------------------------------------------------------
  * This function allows sequential peci_WrEndPointConfig to PCI EndPoint with
- *the provided peci file descriptor.
+ * the provided peci file descriptor.
  *------------------------------------------------------------------------*/
 EPECIStatus peci_WrEndPointConfig_seq(uint8_t target, uint8_t u8MsgType,
                                       uint8_t u8Seg, uint8_t u8Bus,
@@ -1096,6 +1346,23 @@
                                       uint32_t DataVal, int peci_fd,
                                       uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_WrEndPointConfig_seq_dom(target, 0, u8MsgType, u8Seg, u8Bus,
+                                         u8Device, u8Fcn, u16Reg, DataLen,
+                                         DataVal, peci_fd, cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function allows sequential peci_WrEndPointConfig to PCI EndPoint with
+ * the provided peci file descriptor in the specified domain.
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_WrEndPointConfig_seq_dom(uint8_t target, uint8_t domainId,
+                                          uint8_t u8MsgType, uint8_t u8Seg,
+                                          uint8_t u8Bus, uint8_t u8Device,
+                                          uint8_t u8Fcn, uint16_t u16Reg,
+                                          uint8_t DataLen, uint32_t DataVal,
+                                          int peci_fd, uint8_t* cc)
+{
     struct peci_wr_end_pt_cfg_msg cmd = {0};
     EPECIStatus ret = PECI_CC_SUCCESS;
 
@@ -1125,6 +1392,7 @@
     cmd.params.pci_cfg.reg = u16Reg;
     cmd.tx_len = DataLen;
     cmd.value = DataVal;
+    cmd.domain_id = domainId;
 
     ret = HW_peci_issue_cmd(PECI_IOC_WR_END_PT_CFG, (char*)&cmd, peci_fd);
     *cc = cmd.cc;
@@ -1133,7 +1401,7 @@
 }
 
 /*-------------------------------------------------------------------------
- *  This function provides write access to the EP local PCI configuration space
+ * This function provides write access to the EP local PCI configuration space
  *------------------------------------------------------------------------*/
 EPECIStatus peci_WrEndPointPCIConfigLocal(uint8_t target, uint8_t u8Seg,
                                           uint8_t u8Bus, uint8_t u8Device,
@@ -1141,29 +1409,20 @@
                                           uint8_t DataLen, uint32_t DataVal,
                                           uint8_t* cc)
 {
-    int peci_fd = -1;
-    EPECIStatus ret = PECI_CC_SUCCESS;
-
-    if (peci_Open(&peci_fd) != PECI_CC_SUCCESS)
-    {
-        return PECI_CC_DRIVER_ERR;
-    }
-
-    ret = peci_WrEndPointConfig_seq(target, PECI_ENDPTCFG_TYPE_LOCAL_PCI, u8Seg,
-                                    u8Bus, u8Device, u8Fcn, u16Reg, DataLen,
-                                    DataVal, peci_fd, cc);
-    peci_Close(peci_fd);
-    return ret;
+    //  Default to domain ID 0
+    return peci_WrEndPointPCIConfigLocal_dom(
+        target, 0, u8Seg, u8Bus, u8Device, u8Fcn, u16Reg, DataLen, DataVal, cc);
 }
 
 /*-------------------------------------------------------------------------
- *  This function provides write access to the EP local PCI configuration space
+ * This function provides write access to the EP local PCI configuration space
+ * in the specified domain
  *------------------------------------------------------------------------*/
-EPECIStatus peci_WrEndPointPCIConfig(uint8_t target, uint8_t u8Seg,
-                                     uint8_t u8Bus, uint8_t u8Device,
-                                     uint8_t u8Fcn, uint16_t u16Reg,
-                                     uint8_t DataLen, uint32_t DataVal,
-                                     uint8_t* cc)
+EPECIStatus peci_WrEndPointPCIConfigLocal_dom(uint8_t target, uint8_t domainId,
+                                              uint8_t u8Seg, uint8_t u8Bus,
+                                              uint8_t u8Device, uint8_t u8Fcn,
+                                              uint16_t u16Reg, uint8_t DataLen,
+                                              uint32_t DataVal, uint8_t* cc)
 {
     int peci_fd = -1;
     EPECIStatus ret = PECI_CC_SUCCESS;
@@ -1172,9 +1431,48 @@
     {
         return PECI_CC_DRIVER_ERR;
     }
-    ret = peci_WrEndPointConfig_seq(target, PECI_ENDPTCFG_TYPE_PCI, u8Seg,
-                                    u8Bus, u8Device, u8Fcn, u16Reg, DataLen,
-                                    DataVal, peci_fd, cc);
+
+    ret = peci_WrEndPointConfig_seq_dom(
+        target, domainId, PECI_ENDPTCFG_TYPE_LOCAL_PCI, u8Seg, u8Bus, u8Device,
+        u8Fcn, u16Reg, DataLen, DataVal, peci_fd, cc);
+    peci_Close(peci_fd);
+    return ret;
+}
+
+/*-------------------------------------------------------------------------
+ * This function provides write access to the EP local PCI configuration space
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_WrEndPointPCIConfig(uint8_t target, uint8_t u8Seg,
+                                     uint8_t u8Bus, uint8_t u8Device,
+                                     uint8_t u8Fcn, uint16_t u16Reg,
+                                     uint8_t DataLen, uint32_t DataVal,
+                                     uint8_t* cc)
+{
+    //  Default to domain ID 0
+    return peci_WrEndPointPCIConfig_dom(target, 0, u8Seg, u8Bus, u8Device,
+                                        u8Fcn, u16Reg, DataLen, DataVal, cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function provides write access to the EP local PCI configuration space
+ * in the specified domain
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_WrEndPointPCIConfig_dom(uint8_t target, uint8_t domainId,
+                                         uint8_t u8Seg, uint8_t u8Bus,
+                                         uint8_t u8Device, uint8_t u8Fcn,
+                                         uint16_t u16Reg, uint8_t DataLen,
+                                         uint32_t DataVal, uint8_t* cc)
+{
+    int peci_fd = -1;
+    EPECIStatus ret = PECI_CC_SUCCESS;
+
+    if (peci_Open(&peci_fd) != PECI_CC_SUCCESS)
+    {
+        return PECI_CC_DRIVER_ERR;
+    }
+    ret = peci_WrEndPointConfig_seq_dom(
+        target, domainId, PECI_ENDPTCFG_TYPE_PCI, u8Seg, u8Bus, u8Device, u8Fcn,
+        u16Reg, DataLen, DataVal, peci_fd, cc);
     peci_Close(peci_fd);
     return ret;
 }
@@ -1190,6 +1488,23 @@
                                       uint8_t u8DataLen, uint64_t u64DataVal,
                                       uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_WrEndPointConfigMmio_dom(target, 0, u8Seg, u8Bus, u8Device,
+                                         u8Fcn, u8Bar, u8AddrType, u64Offset,
+                                         u8DataLen, u64DataVal, cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function provides write access to PCI MMIO space at
+ * the requested PCI configuration address in the specified domain.
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_WrEndPointConfigMmio_dom(uint8_t target, uint8_t domainId,
+                                          uint8_t u8Seg, uint8_t u8Bus,
+                                          uint8_t u8Device, uint8_t u8Fcn,
+                                          uint8_t u8Bar, uint8_t u8AddrType,
+                                          uint64_t u64Offset, uint8_t u8DataLen,
+                                          uint64_t u64DataVal, uint8_t* cc)
+{
     int peci_fd = -1;
     EPECIStatus ret = PECI_CC_SUCCESS;
 
@@ -1208,9 +1523,9 @@
     {
         return PECI_CC_DRIVER_ERR;
     }
-    ret = peci_WrEndPointConfigMmio_seq(target, u8Seg, u8Bus, u8Device, u8Fcn,
-                                        u8Bar, u8AddrType, u64Offset, u8DataLen,
-                                        u64DataVal, peci_fd, cc);
+    ret = peci_WrEndPointConfigMmio_seq_dom(
+        target, domainId, u8Seg, u8Bus, u8Device, u8Fcn, u8Bar, u8AddrType,
+        u64Offset, u8DataLen, u64DataVal, peci_fd, cc);
     peci_Close(peci_fd);
     return ret;
 }
@@ -1224,6 +1539,22 @@
     uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType, uint64_t u64Offset,
     uint8_t u8DataLen, uint64_t u64DataVal, int peci_fd, uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_WrEndPointConfigMmio_seq_dom(
+        target, 0, u8Seg, u8Bus, u8Device, u8Fcn, u8Bar, u8AddrType, u64Offset,
+        u8DataLen, u64DataVal, peci_fd, cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function allows sequential WrEndPointConfig to PCI MMIO with the
+ * provided peci file descriptor in the specified domain.
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_WrEndPointConfigMmio_seq_dom(
+    uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+    uint8_t u8Device, uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType,
+    uint64_t u64Offset, uint8_t u8DataLen, uint64_t u64DataVal, int peci_fd,
+    uint8_t* cc)
+{
     struct peci_wr_end_pt_cfg_msg cmd = {0};
     EPECIStatus ret = PECI_CC_SUCCESS;
 
@@ -1255,6 +1586,7 @@
     cmd.params.mmio.offset = u64Offset;
     cmd.tx_len = u8DataLen;
     cmd.value = u64DataVal;
+    cmd.domain_id = domainId;
 
     ret = HW_peci_issue_cmd(PECI_IOC_WR_END_PT_CFG, (char*)&cmd, peci_fd);
     *cc = cmd.cc;
@@ -1263,13 +1595,28 @@
 }
 
 /*-------------------------------------------------------------------------
- *  This function provides crashdump discovery data over PECI
+ * This function provides crashdump discovery data over PECI
  *------------------------------------------------------------------------*/
 EPECIStatus peci_CrashDump_Discovery(uint8_t target, uint8_t subopcode,
                                      uint8_t param0, uint16_t param1,
                                      uint8_t param2, uint8_t u8ReadLen,
                                      uint8_t* pData, uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_CrashDump_Discovery_dom(target, 0, subopcode, param0, param1,
+                                        param2, u8ReadLen, pData, cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function provides crashdump discovery data over PECI in the specified
+ * domain
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_CrashDump_Discovery_dom(uint8_t target, uint8_t domainId,
+                                         uint8_t subopcode, uint8_t param0,
+                                         uint16_t param1, uint8_t param2,
+                                         uint8_t u8ReadLen, uint8_t* pData,
+                                         uint8_t* cc)
+{
     int peci_fd = -1;
     struct peci_crashdump_disc_msg cmd = {0};
     EPECIStatus ret = PECI_CC_SUCCESS;
@@ -1308,6 +1655,7 @@
     cmd.param1 = param1;
     cmd.param2 = param2;
     cmd.rx_len = u8ReadLen;
+    cmd.domain_id = domainId;
 
     ret = HW_peci_issue_cmd(PECI_IOC_CRASHDUMP_DISC, (char*)&cmd, peci_fd);
     *cc = cmd.cc;
@@ -1325,13 +1673,27 @@
 }
 
 /*-------------------------------------------------------------------------
- *  This function provides crashdump GetFrame data over PECI
+ * This function provides crashdump GetFrame data over PECI
  *------------------------------------------------------------------------*/
 EPECIStatus peci_CrashDump_GetFrame(uint8_t target, uint16_t param0,
                                     uint16_t param1, uint16_t param2,
                                     uint8_t u8ReadLen, uint8_t* pData,
                                     uint8_t* cc)
 {
+    //  Default to domain ID 0
+    return peci_CrashDump_GetFrame_dom(target, 0, param0, param1, param2,
+                                       u8ReadLen, pData, cc);
+}
+
+/*-------------------------------------------------------------------------
+ * This function provides crashdump GetFrame data over PECI in the specified
+ * domain
+ *------------------------------------------------------------------------*/
+EPECIStatus peci_CrashDump_GetFrame_dom(uint8_t target, uint8_t domainId,
+                                        uint16_t param0, uint16_t param1,
+                                        uint16_t param2, uint8_t u8ReadLen,
+                                        uint8_t* pData, uint8_t* cc)
+{
     int peci_fd = -1;
     struct peci_crashdump_get_frame_msg cmd = {0};
     EPECIStatus ret = PECI_CC_SUCCESS;
@@ -1369,6 +1731,7 @@
     cmd.param1 = param1;
     cmd.param2 = param2;
     cmd.rx_len = u8ReadLen;
+    cmd.domain_id = domainId;
 
     ret = HW_peci_issue_cmd(PECI_IOC_CRASHDUMP_GET_FRAME, (char*)&cmd, peci_fd);
     *cc = cmd.cc;
diff --git a/peci.h b/peci.h
index aa482db..fb46010 100644
--- a/peci.h
+++ b/peci.h
@@ -105,42 +105,97 @@
                              uint8_t u8ReadLen, uint8_t* pPkgConfig,
                              uint8_t* cc);
 
+// Provides read access to the package configuration space within the processor
+// in the specified domain
+EPECIStatus peci_RdPkgConfig_dom(uint8_t target, uint8_t domainId,
+                                 uint8_t u8Index, uint16_t u16Value,
+                                 uint8_t u8ReadLen, uint8_t* pPkgConfig,
+                                 uint8_t* cc);
+
 // Allows sequential RdPkgConfig with the provided peci file descriptor
 EPECIStatus peci_RdPkgConfig_seq(uint8_t target, uint8_t u8Index,
                                  uint16_t u16Value, uint8_t u8ReadLen,
                                  uint8_t* pPkgConfig, int peci_fd, uint8_t* cc);
 
+// Allows sequential RdPkgConfig with the provided peci file descriptor in the
+// specified domain
+EPECIStatus peci_RdPkgConfig_seq_dom(uint8_t target, uint8_t domainId,
+                                     uint8_t u8Index, uint16_t u16Value,
+                                     uint8_t u8ReadLen, uint8_t* pPkgConfig,
+                                     int peci_fd, uint8_t* cc);
+
 // Provides write access to the package configuration space within the processor
 EPECIStatus peci_WrPkgConfig(uint8_t target, uint8_t u8Index, uint16_t u16Param,
                              uint32_t u32Value, uint8_t u8WriteLen,
                              uint8_t* cc);
 
+// Provides write access to the package configuration space within the processor
+// in the specified domain
+EPECIStatus peci_WrPkgConfig_dom(uint8_t target, uint8_t domainId,
+                                 uint8_t u8Index, uint16_t u16Param,
+                                 uint32_t u32Value, uint8_t u8WriteLen,
+                                 uint8_t* cc);
+
 // Allows sequential WrPkgConfig with the provided peci file descriptor
 EPECIStatus peci_WrPkgConfig_seq(uint8_t target, uint8_t u8Index,
                                  uint16_t u16Param, uint32_t u32Value,
                                  uint8_t u8WriteLen, int peci_fd, uint8_t* cc);
 
+// Allows sequential WrPkgConfig with the provided peci file descriptor in the
+// specified domain
+EPECIStatus peci_WrPkgConfig_seq_dom(uint8_t target, uint8_t domainId,
+                                     uint8_t u8Index, uint16_t u16Param,
+                                     uint32_t u32Value, uint8_t u8WriteLen,
+                                     int peci_fd, uint8_t* cc);
+
 // Provides read access to Model Specific Registers
 EPECIStatus peci_RdIAMSR(uint8_t target, uint8_t threadID, uint16_t MSRAddress,
                          uint64_t* u64MsrVal, uint8_t* cc);
 
+// Provides read access to Model Specific Registers in the specified domain
+EPECIStatus peci_RdIAMSR_dom(uint8_t target, uint8_t domainId, uint8_t threadID,
+                             uint16_t MSRAddress, uint64_t* u64MsrVal,
+                             uint8_t* cc);
+
 // Provides read access to PCI Configuration space
 EPECIStatus peci_RdPCIConfig(uint8_t target, uint8_t u8Bus, uint8_t u8Device,
                              uint8_t u8Fcn, uint16_t u16Reg, uint8_t* pPCIReg,
                              uint8_t* cc);
 
+// Provides read access to PCI Configuration space in the specified domain
+EPECIStatus peci_RdPCIConfig_dom(uint8_t target, uint8_t domainId,
+                                 uint8_t u8Bus, uint8_t u8Device, uint8_t u8Fcn,
+                                 uint16_t u16Reg, uint8_t* pPCIReg,
+                                 uint8_t* cc);
+
 // Allows sequential RdPCIConfig with the provided peci file descriptor
 EPECIStatus peci_RdPCIConfig_seq(uint8_t target, uint8_t u8Bus,
                                  uint8_t u8Device, uint8_t u8Fcn,
                                  uint16_t u16Reg, uint8_t* pPCIData,
                                  int peci_fd, uint8_t* cc);
 
+// Allows sequential RdPCIConfig with the provided peci file descriptor in the
+// specified domain
+EPECIStatus peci_RdPCIConfig_seq_dom(uint8_t target, uint8_t domainId,
+                                     uint8_t u8Bus, uint8_t u8Device,
+                                     uint8_t u8Fcn, uint16_t u16Reg,
+                                     uint8_t* pPCIData, int peci_fd,
+                                     uint8_t* cc);
+
 // Provides read access to the local PCI Configuration space
 EPECIStatus peci_RdPCIConfigLocal(uint8_t target, uint8_t u8Bus,
                                   uint8_t u8Device, uint8_t u8Fcn,
                                   uint16_t u16Reg, uint8_t u8ReadLen,
                                   uint8_t* pPCIReg, uint8_t* cc);
 
+// Provides read access to the local PCI Configuration space in the specified
+// domain
+EPECIStatus peci_RdPCIConfigLocal_dom(uint8_t target, uint8_t domainId,
+                                      uint8_t u8Bus, uint8_t u8Device,
+                                      uint8_t u8Fcn, uint16_t u16Reg,
+                                      uint8_t u8ReadLen, uint8_t* pPCIReg,
+                                      uint8_t* cc);
+
 // Allows sequential RdPCIConfigLocal with the provided peci file descriptor
 EPECIStatus peci_RdPCIConfigLocal_seq(uint8_t target, uint8_t u8Bus,
                                       uint8_t u8Device, uint8_t u8Fcn,
@@ -148,12 +203,28 @@
                                       uint8_t* pPCIReg, int peci_fd,
                                       uint8_t* cc);
 
+// Allows sequential RdPCIConfigLocal with the provided peci file descriptor in
+// the specified domain
+EPECIStatus peci_RdPCIConfigLocal_seq_dom(uint8_t target, uint8_t domainId,
+                                          uint8_t u8Bus, uint8_t u8Device,
+                                          uint8_t u8Fcn, uint16_t u16Reg,
+                                          uint8_t u8ReadLen, uint8_t* pPCIReg,
+                                          int peci_fd, uint8_t* cc);
+
 // Provides write access to the local PCI Configuration space
 EPECIStatus peci_WrPCIConfigLocal(uint8_t target, uint8_t u8Bus,
                                   uint8_t u8Device, uint8_t u8Fcn,
                                   uint16_t u16Reg, uint8_t DataLen,
                                   uint32_t DataVal, uint8_t* cc);
 
+// Provides write access to the local PCI Configuration space in the specified
+// domain
+EPECIStatus peci_WrPCIConfigLocal_dom(uint8_t target, uint8_t domainId,
+                                      uint8_t u8Bus, uint8_t u8Device,
+                                      uint8_t u8Fcn, uint16_t u16Reg,
+                                      uint8_t DataLen, uint32_t DataVal,
+                                      uint8_t* cc);
+
 // Provides read access to PCI configuration space
 EPECIStatus peci_RdEndPointConfigPci(uint8_t target, uint8_t u8Seg,
                                      uint8_t u8Bus, uint8_t u8Device,
@@ -161,6 +232,13 @@
                                      uint8_t u8ReadLen, uint8_t* pPCIData,
                                      uint8_t* cc);
 
+// Provides read access to PCI configuration space in the specified domain
+EPECIStatus peci_RdEndPointConfigPci_dom(uint8_t target, uint8_t domainId,
+                                         uint8_t u8Seg, uint8_t u8Bus,
+                                         uint8_t u8Device, uint8_t u8Fcn,
+                                         uint16_t u16Reg, uint8_t u8ReadLen,
+                                         uint8_t* pPCIData, uint8_t* cc);
+
 // Allows sequential RdEndPointConfig to PCI Configuration space
 EPECIStatus peci_RdEndPointConfigPci_seq(uint8_t target, uint8_t u8Seg,
                                          uint8_t u8Bus, uint8_t u8Device,
@@ -168,6 +246,15 @@
                                          uint8_t u8ReadLen, uint8_t* pPCIData,
                                          int peci_fd, uint8_t* cc);
 
+// Allows sequential RdEndPointConfig to PCI Configuration space in the
+// specified domain
+EPECIStatus peci_RdEndPointConfigPci_seq_dom(uint8_t target, uint8_t domainId,
+                                             uint8_t u8Seg, uint8_t u8Bus,
+                                             uint8_t u8Device, uint8_t u8Fcn,
+                                             uint16_t u16Reg, uint8_t u8ReadLen,
+                                             uint8_t* pPCIData, int peci_fd,
+                                             uint8_t* cc);
+
 // Provides read access to the local PCI configuration space
 EPECIStatus peci_RdEndPointConfigPciLocal(uint8_t target, uint8_t u8Seg,
                                           uint8_t u8Bus, uint8_t u8Device,
@@ -175,6 +262,15 @@
                                           uint8_t u8ReadLen, uint8_t* pPCIData,
                                           uint8_t* cc);
 
+// Provides read access to the local PCI configuration space in the specified
+// domain
+EPECIStatus peci_RdEndPointConfigPciLocal_dom(uint8_t target, uint8_t domainId,
+                                              uint8_t u8Seg, uint8_t u8Bus,
+                                              uint8_t u8Device, uint8_t u8Fcn,
+                                              uint16_t u16Reg,
+                                              uint8_t u8ReadLen,
+                                              uint8_t* pPCIData, uint8_t* cc);
+
 // Allows sequential RdEndPointConfig to the local PCI Configuration space
 EPECIStatus peci_RdEndPointConfigPciLocal_seq(uint8_t target, uint8_t u8Seg,
                                               uint8_t u8Bus, uint8_t u8Device,
@@ -183,6 +279,13 @@
                                               uint8_t* pPCIData, int peci_fd,
                                               uint8_t* cc);
 
+// Allows sequential RdEndPointConfig to the local PCI Configuration space in
+// the specified domain
+EPECIStatus peci_RdEndPointConfigPciLocal_seq_dom(
+    uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+    uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg, uint8_t u8ReadLen,
+    uint8_t* pPCIData, int peci_fd, uint8_t* cc);
+
 // Provides read access to PCI MMIO space
 EPECIStatus peci_RdEndPointConfigMmio(uint8_t target, uint8_t u8Seg,
                                       uint8_t u8Bus, uint8_t u8Device,
@@ -191,12 +294,27 @@
                                       uint8_t u8ReadLen, uint8_t* pMmioData,
                                       uint8_t* cc);
 
+// Provides read access to PCI MMIO space in the specified domain
+EPECIStatus peci_RdEndPointConfigMmio_dom(uint8_t target, uint8_t domainId,
+                                          uint8_t u8Seg, uint8_t u8Bus,
+                                          uint8_t u8Device, uint8_t u8Fcn,
+                                          uint8_t u8Bar, uint8_t u8AddrType,
+                                          uint64_t u64Offset, uint8_t u8ReadLen,
+                                          uint8_t* pMmioData, uint8_t* cc);
+
 // Allows sequential RdEndPointConfig to PCI MMIO space
 EPECIStatus peci_RdEndPointConfigMmio_seq(
     uint8_t target, uint8_t u8Seg, uint8_t u8Bus, uint8_t u8Device,
     uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType, uint64_t u64Offset,
     uint8_t u8ReadLen, uint8_t* pMmioData, int peci_fd, uint8_t* cc);
 
+// Allows sequential RdEndPointConfig to PCI MMIO space in the specified domain
+EPECIStatus peci_RdEndPointConfigMmio_seq_dom(
+    uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+    uint8_t u8Device, uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType,
+    uint64_t u64Offset, uint8_t u8ReadLen, uint8_t* pMmioData, int peci_fd,
+    uint8_t* cc);
+
 // Provides write access to the EP local PCI Configuration space
 EPECIStatus peci_WrEndPointPCIConfigLocal(uint8_t target, uint8_t u8Seg,
                                           uint8_t u8Bus, uint8_t u8Device,
@@ -204,6 +322,14 @@
                                           uint8_t DataLen, uint32_t DataVal,
                                           uint8_t* cc);
 
+// Provides write access to the EP local PCI Configuration space in the
+// specified domain
+EPECIStatus peci_WrEndPointPCIConfigLocal_dom(uint8_t target, uint8_t domainId,
+                                              uint8_t u8Seg, uint8_t u8Bus,
+                                              uint8_t u8Device, uint8_t u8Fcn,
+                                              uint16_t u16Reg, uint8_t DataLen,
+                                              uint32_t DataVal, uint8_t* cc);
+
 // Provides write access to the EP PCI Configuration space
 EPECIStatus peci_WrEndPointPCIConfig(uint8_t target, uint8_t u8Seg,
                                      uint8_t u8Bus, uint8_t u8Device,
@@ -211,6 +337,14 @@
                                      uint8_t DataLen, uint32_t DataVal,
                                      uint8_t* cc);
 
+// Provides write access to the EP PCI Configuration space in the specified
+// domain
+EPECIStatus peci_WrEndPointPCIConfig_dom(uint8_t target, uint8_t domainId,
+                                         uint8_t u8Seg, uint8_t u8Bus,
+                                         uint8_t u8Device, uint8_t u8Fcn,
+                                         uint16_t u16Reg, uint8_t DataLen,
+                                         uint32_t DataVal, uint8_t* cc);
+
 // Allows sequential write access to the EP PCI Configuration space
 EPECIStatus peci_WrEndPointConfig_seq(uint8_t target, uint8_t u8MsgType,
                                       uint8_t u8Seg, uint8_t u8Bus,
@@ -219,6 +353,15 @@
                                       uint32_t DataVal, int peci_fd,
                                       uint8_t* cc);
 
+// Allows sequential write access to the EP PCI Configuration space in the
+// specified domain
+EPECIStatus peci_WrEndPointConfig_seq_dom(uint8_t target, uint8_t domainId,
+                                          uint8_t u8MsgType, uint8_t u8Seg,
+                                          uint8_t u8Bus, uint8_t u8Device,
+                                          uint8_t u8Fcn, uint16_t u16Reg,
+                                          uint8_t DataLen, uint32_t DataVal,
+                                          int peci_fd, uint8_t* cc);
+
 // Provides write access to the EP PCI MMIO space
 EPECIStatus peci_WrEndPointConfigMmio(uint8_t target, uint8_t u8Seg,
                                       uint8_t u8Bus, uint8_t u8Device,
@@ -227,24 +370,53 @@
                                       uint8_t u8DataLen, uint64_t u64DataVal,
                                       uint8_t* cc);
 
+// Provides write access to the EP PCI MMIO space in the specified domain
+EPECIStatus peci_WrEndPointConfigMmio_dom(uint8_t target, uint8_t domainId,
+                                          uint8_t u8Seg, uint8_t u8Bus,
+                                          uint8_t u8Device, uint8_t u8Fcn,
+                                          uint8_t u8Bar, uint8_t u8AddrType,
+                                          uint64_t u64Offset, uint8_t u8DataLen,
+                                          uint64_t u64DataVal, uint8_t* cc);
+
 // Allows sequential write access to the EP PCI MMIO space
 EPECIStatus peci_WrEndPointConfigMmio_seq(
     uint8_t target, uint8_t u8Seg, uint8_t u8Bus, uint8_t u8Device,
     uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType, uint64_t u64Offset,
     uint8_t u8DataLen, uint64_t u64DataVal, int peci_fd, uint8_t* cc);
 
+// Allows sequential write access to the EP PCI MMIO space in the specified
+// domain
+EPECIStatus peci_WrEndPointConfigMmio_seq_dom(
+    uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+    uint8_t u8Device, uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType,
+    uint64_t u64Offset, uint8_t u8DataLen, uint64_t u64DataVal, int peci_fd,
+    uint8_t* cc);
+
 // Provides access to the Crashdump Discovery API
 EPECIStatus peci_CrashDump_Discovery(uint8_t target, uint8_t subopcode,
                                      uint8_t param0, uint16_t param1,
                                      uint8_t param2, uint8_t u8ReadLen,
                                      uint8_t* pData, uint8_t* cc);
 
+// Provides access to the Crashdump Discovery API in the specified domain
+EPECIStatus peci_CrashDump_Discovery_dom(uint8_t target, uint8_t domainId,
+                                         uint8_t subopcode, uint8_t param0,
+                                         uint16_t param1, uint8_t param2,
+                                         uint8_t u8ReadLen, uint8_t* pData,
+                                         uint8_t* cc);
+
 // Provides access to the Crashdump GetFrame API
 EPECIStatus peci_CrashDump_GetFrame(uint8_t target, uint16_t param0,
                                     uint16_t param1, uint16_t param2,
                                     uint8_t u8ReadLen, uint8_t* pData,
                                     uint8_t* cc);
 
+// Provides access to the Crashdump GetFrame API in the specified domain
+EPECIStatus peci_CrashDump_GetFrame_dom(uint8_t target, uint8_t domainId,
+                                        uint16_t param0, uint16_t param1,
+                                        uint16_t param2, uint8_t u8ReadLen,
+                                        uint8_t* pData, uint8_t* cc);
+
 // Provides raw PECI command access
 EPECIStatus peci_raw(uint8_t target, uint8_t u8ReadLen, const uint8_t* pRawCmd,
                      const uint32_t cmdSize, uint8_t* pRawResp,