clang-format: re-format for clang-18
clang-format-18 isn't compatible with the clang-format-17 output, so we
need to reformat the code with the latest version. The way clang-18
handles lambda formatting also changed, so we have made changes to the
organization default style format to better handle lambda formatting.
See I5e08687e696dd240402a2780158664b7113def0e for updated style.
See Iea0776aaa7edd483fa395e23de25ebf5a6288f71 for clang-18 enablement.
Change-Id: I6b1113d51f0f20dc477a39549f8c4ef1327f267b
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
diff --git a/peci.h b/peci.h
index 3083055..61dfea5 100644
--- a/peci.h
+++ b/peci.h
@@ -121,10 +121,9 @@
// Provides read access to the package configuration space within the
// processor in the specified domain
-EPECIStatus peci_RdPkgConfig_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Index, uint16_t u16Value,
- uint8_t u8ReadLen, uint8_t* pPkgConfig,
- uint8_t* cc);
+EPECIStatus peci_RdPkgConfig_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8Index, uint16_t u16Value,
+ uint8_t u8ReadLen, uint8_t* pPkgConfig, uint8_t* cc);
// Allows sequential RdPkgConfig with the provided peci file descriptor
EPECIStatus peci_RdPkgConfig_seq(uint8_t target, uint8_t u8Index,
@@ -133,10 +132,9 @@
// Allows sequential RdPkgConfig with the provided peci file descriptor in
// the specified domain
-EPECIStatus peci_RdPkgConfig_seq_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Index, uint16_t u16Value,
- uint8_t u8ReadLen, uint8_t* pPkgConfig,
- int peci_fd, uint8_t* cc);
+EPECIStatus peci_RdPkgConfig_seq_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8Index, uint16_t u16Value,
+ uint8_t u8ReadLen, uint8_t* pPkgConfig, int peci_fd, uint8_t* cc);
// Provides write access to the package configuration space within the
// processor
@@ -146,10 +144,9 @@
// Provides write access to the package configuration space within the
// processor in the specified domain
-EPECIStatus peci_WrPkgConfig_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Index, uint16_t u16Param,
- uint32_t u32Value, uint8_t u8WriteLen,
- uint8_t* cc);
+EPECIStatus peci_WrPkgConfig_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8Index, uint16_t u16Param,
+ uint32_t u32Value, uint8_t u8WriteLen, uint8_t* cc);
// Allows sequential WrPkgConfig with the provided peci file descriptor
EPECIStatus peci_WrPkgConfig_seq(uint8_t target, uint8_t u8Index,
@@ -158,10 +155,9 @@
// Allows sequential WrPkgConfig with the provided peci file descriptor in
// the specified domain
-EPECIStatus peci_WrPkgConfig_seq_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Index, uint16_t u16Param,
- uint32_t u32Value, uint8_t u8WriteLen,
- int peci_fd, uint8_t* cc);
+EPECIStatus peci_WrPkgConfig_seq_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8Index, uint16_t u16Param,
+ uint32_t u32Value, uint8_t u8WriteLen, int peci_fd, uint8_t* cc);
// Provides read access to Model Specific Registers
EPECIStatus peci_RdIAMSR(uint8_t target, uint8_t threadID, uint16_t MSRAddress,
@@ -178,121 +174,102 @@
uint8_t* cc);
// Provides read access to PCI Configuration space in the specified domain
-EPECIStatus peci_RdPCIConfig_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Bus, uint8_t u8Device, uint8_t u8Fcn,
- uint16_t u16Reg, uint8_t* pPCIReg,
- uint8_t* cc);
+EPECIStatus peci_RdPCIConfig_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8Bus, uint8_t u8Device,
+ uint8_t u8Fcn, uint16_t u16Reg, uint8_t* pPCIReg, uint8_t* cc);
// Allows sequential RdPCIConfig with the provided peci file descriptor
-EPECIStatus peci_RdPCIConfig_seq(uint8_t target, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint16_t u16Reg, uint8_t* pPCIData,
- int peci_fd, uint8_t* cc);
+EPECIStatus peci_RdPCIConfig_seq(
+ uint8_t target, uint8_t u8Bus, uint8_t u8Device, uint8_t u8Fcn,
+ uint16_t u16Reg, uint8_t* pPCIData, int peci_fd, uint8_t* cc);
// Allows sequential RdPCIConfig with the provided peci file descriptor in
// the specified domain
-EPECIStatus peci_RdPCIConfig_seq_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint16_t u16Reg,
- uint8_t* pPCIData, int peci_fd,
- uint8_t* cc);
+EPECIStatus
+ peci_RdPCIConfig_seq_dom(uint8_t target, uint8_t domainId, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg,
+ uint8_t* pPCIData, int peci_fd, uint8_t* cc);
// Provides read access to the local PCI Configuration space
-EPECIStatus peci_RdPCIConfigLocal(uint8_t target, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint16_t u16Reg, uint8_t u8ReadLen,
- uint8_t* pPCIReg, uint8_t* cc);
+EPECIStatus peci_RdPCIConfigLocal(
+ uint8_t target, uint8_t u8Bus, uint8_t u8Device, uint8_t u8Fcn,
+ uint16_t u16Reg, uint8_t u8ReadLen, uint8_t* pPCIReg, uint8_t* cc);
// Provides read access to the local PCI Configuration space in the
// specified domain
-EPECIStatus peci_RdPCIConfigLocal_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint16_t u16Reg,
- uint8_t u8ReadLen, uint8_t* pPCIReg,
- uint8_t* cc);
+EPECIStatus
+ peci_RdPCIConfigLocal_dom(uint8_t target, uint8_t domainId, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg,
+ uint8_t u8ReadLen, uint8_t* pPCIReg, uint8_t* cc);
// Allows sequential RdPCIConfigLocal with the provided peci file descriptor
-EPECIStatus peci_RdPCIConfigLocal_seq(uint8_t target, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint16_t u16Reg, uint8_t u8ReadLen,
- uint8_t* pPCIReg, int peci_fd,
- uint8_t* cc);
+EPECIStatus
+ peci_RdPCIConfigLocal_seq(uint8_t target, uint8_t u8Bus, uint8_t u8Device,
+ uint8_t u8Fcn, uint16_t u16Reg, uint8_t u8ReadLen,
+ uint8_t* pPCIReg, int peci_fd, uint8_t* cc);
// Allows sequential RdPCIConfigLocal with the provided peci file descriptor
// in the specified domain
-EPECIStatus peci_RdPCIConfigLocal_seq_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint16_t u16Reg,
- uint8_t u8ReadLen, uint8_t* pPCIReg,
- int peci_fd, uint8_t* cc);
+EPECIStatus peci_RdPCIConfigLocal_seq_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8Bus, uint8_t u8Device,
+ uint8_t u8Fcn, uint16_t u16Reg, uint8_t u8ReadLen, uint8_t* pPCIReg,
+ int peci_fd, uint8_t* cc);
// Provides write access to the local PCI Configuration space
-EPECIStatus peci_WrPCIConfigLocal(uint8_t target, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint16_t u16Reg, uint8_t DataLen,
- uint32_t DataVal, uint8_t* cc);
+EPECIStatus peci_WrPCIConfigLocal(
+ uint8_t target, uint8_t u8Bus, uint8_t u8Device, uint8_t u8Fcn,
+ uint16_t u16Reg, uint8_t DataLen, uint32_t DataVal, uint8_t* cc);
// Provides write access to the local PCI Configuration space in the
// specified domain
-EPECIStatus peci_WrPCIConfigLocal_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint16_t u16Reg,
- uint8_t DataLen, uint32_t DataVal,
- uint8_t* cc);
+EPECIStatus
+ peci_WrPCIConfigLocal_dom(uint8_t target, uint8_t domainId, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg,
+ uint8_t DataLen, uint32_t DataVal, uint8_t* cc);
// Provides read access to PCI configuration space
-EPECIStatus peci_RdEndPointConfigPci(uint8_t target, uint8_t u8Seg,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint16_t u16Reg,
- uint8_t u8ReadLen, uint8_t* pPCIData,
- uint8_t* cc);
+EPECIStatus
+ peci_RdEndPointConfigPci(uint8_t target, uint8_t u8Seg, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg,
+ uint8_t u8ReadLen, uint8_t* pPCIData, uint8_t* cc);
// Provides read access to PCI configuration space in the specified domain
-EPECIStatus peci_RdEndPointConfigPci_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Seg, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint16_t u16Reg, uint8_t u8ReadLen,
- uint8_t* pPCIData, uint8_t* cc);
+EPECIStatus peci_RdEndPointConfigPci_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg, uint8_t u8ReadLen,
+ uint8_t* pPCIData, uint8_t* cc);
// Allows sequential RdEndPointConfig to PCI Configuration space
-EPECIStatus peci_RdEndPointConfigPci_seq(uint8_t target, uint8_t u8Seg,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint16_t u16Reg,
- uint8_t u8ReadLen, uint8_t* pPCIData,
- int peci_fd, uint8_t* cc);
+EPECIStatus peci_RdEndPointConfigPci_seq(
+ uint8_t target, uint8_t u8Seg, uint8_t u8Bus, uint8_t u8Device,
+ uint8_t u8Fcn, uint16_t u16Reg, uint8_t u8ReadLen, uint8_t* pPCIData,
+ int peci_fd, uint8_t* cc);
// Allows sequential RdEndPointConfig to PCI Configuration space in the
// specified domain
-EPECIStatus peci_RdEndPointConfigPci_seq_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Seg, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint16_t u16Reg, uint8_t u8ReadLen,
- uint8_t* pPCIData, int peci_fd,
- uint8_t* cc);
+EPECIStatus peci_RdEndPointConfigPci_seq_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg, uint8_t u8ReadLen,
+ uint8_t* pPCIData, int peci_fd, uint8_t* cc);
// Provides read access to the local PCI configuration space
-EPECIStatus peci_RdEndPointConfigPciLocal(uint8_t target, uint8_t u8Seg,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint16_t u16Reg,
- uint8_t u8ReadLen, uint8_t* pPCIData,
- uint8_t* cc);
+EPECIStatus peci_RdEndPointConfigPciLocal(
+ uint8_t target, uint8_t u8Seg, uint8_t u8Bus, uint8_t u8Device,
+ uint8_t u8Fcn, uint16_t u16Reg, uint8_t u8ReadLen, uint8_t* pPCIData,
+ uint8_t* cc);
// Provides read access to the local PCI configuration space in the
// specified domain
-EPECIStatus peci_RdEndPointConfigPciLocal_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Seg, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint16_t u16Reg,
- uint8_t u8ReadLen,
- uint8_t* pPCIData, uint8_t* cc);
+EPECIStatus peci_RdEndPointConfigPciLocal_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg, uint8_t u8ReadLen,
+ uint8_t* pPCIData, uint8_t* cc);
// Allows sequential RdEndPointConfig to the local PCI Configuration space
-EPECIStatus peci_RdEndPointConfigPciLocal_seq(uint8_t target, uint8_t u8Seg,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint16_t u16Reg,
- uint8_t u8ReadLen,
- uint8_t* pPCIData, int peci_fd,
- uint8_t* cc);
+EPECIStatus peci_RdEndPointConfigPciLocal_seq(
+ uint8_t target, uint8_t u8Seg, uint8_t u8Bus, uint8_t u8Device,
+ uint8_t u8Fcn, uint16_t u16Reg, uint8_t u8ReadLen, uint8_t* pPCIData,
+ int peci_fd, uint8_t* cc);
// Allows sequential RdEndPointConfig to the local PCI Configuration space
// in the specified domain
@@ -302,20 +279,16 @@
uint8_t* pPCIData, int peci_fd, uint8_t* cc);
// Provides read access to PCI MMIO space
-EPECIStatus peci_RdEndPointConfigMmio(uint8_t target, uint8_t u8Seg,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint8_t u8Bar,
- uint8_t u8AddrType, uint64_t u64Offset,
- uint8_t u8ReadLen, uint8_t* pMmioData,
- uint8_t* cc);
+EPECIStatus peci_RdEndPointConfigMmio(
+ uint8_t target, uint8_t u8Seg, uint8_t u8Bus, uint8_t u8Device,
+ uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType, uint64_t u64Offset,
+ uint8_t u8ReadLen, uint8_t* pMmioData, uint8_t* cc);
// Provides read access to PCI MMIO space in the specified domain
-EPECIStatus peci_RdEndPointConfigMmio_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Seg, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint8_t u8Bar, uint8_t u8AddrType,
- uint64_t u64Offset, uint8_t u8ReadLen,
- uint8_t* pMmioData, uint8_t* cc);
+EPECIStatus peci_RdEndPointConfigMmio_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType,
+ uint64_t u64Offset, uint8_t u8ReadLen, uint8_t* pMmioData, uint8_t* cc);
// Allows sequential RdEndPointConfig to PCI MMIO space
EPECIStatus peci_RdEndPointConfigMmio_seq(
@@ -332,67 +305,55 @@
uint8_t* cc);
// Provides write access to the EP local PCI Configuration space
-EPECIStatus peci_WrEndPointPCIConfigLocal(uint8_t target, uint8_t u8Seg,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint16_t u16Reg,
- uint8_t DataLen, uint32_t DataVal,
- uint8_t* cc);
+EPECIStatus peci_WrEndPointPCIConfigLocal(
+ uint8_t target, uint8_t u8Seg, uint8_t u8Bus, uint8_t u8Device,
+ uint8_t u8Fcn, uint16_t u16Reg, uint8_t DataLen, uint32_t DataVal,
+ uint8_t* cc);
// Provides write access to the EP local PCI Configuration space in the
// specified domain
-EPECIStatus peci_WrEndPointPCIConfigLocal_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Seg, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint16_t u16Reg, uint8_t DataLen,
- uint32_t DataVal, uint8_t* cc);
+EPECIStatus peci_WrEndPointPCIConfigLocal_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg, uint8_t DataLen,
+ uint32_t DataVal, uint8_t* cc);
// Provides write access to the EP PCI Configuration space
-EPECIStatus peci_WrEndPointPCIConfig(uint8_t target, uint8_t u8Seg,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint16_t u16Reg,
- uint8_t DataLen, uint32_t DataVal,
- uint8_t* cc);
+EPECIStatus
+ peci_WrEndPointPCIConfig(uint8_t target, uint8_t u8Seg, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg,
+ uint8_t DataLen, uint32_t DataVal, uint8_t* cc);
// Provides write access to the EP PCI Configuration space in the specified
// domain
-EPECIStatus peci_WrEndPointPCIConfig_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Seg, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint16_t u16Reg, uint8_t DataLen,
- uint32_t DataVal, uint8_t* cc);
+EPECIStatus peci_WrEndPointPCIConfig_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg, uint8_t DataLen,
+ uint32_t DataVal, uint8_t* cc);
// Allows sequential write access to the EP PCI Configuration space
-EPECIStatus peci_WrEndPointConfig_seq(uint8_t target, uint8_t u8MsgType,
- uint8_t u8Seg, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint16_t u16Reg, uint8_t DataLen,
- uint32_t DataVal, int peci_fd,
- uint8_t* cc);
+EPECIStatus peci_WrEndPointConfig_seq(
+ uint8_t target, uint8_t u8MsgType, uint8_t u8Seg, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg, uint8_t DataLen,
+ uint32_t DataVal, int peci_fd, uint8_t* cc);
// Allows sequential write access to the EP PCI Configuration space in the
// specified domain
-EPECIStatus peci_WrEndPointConfig_seq_dom(uint8_t target, uint8_t domainId,
- uint8_t u8MsgType, uint8_t u8Seg,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint16_t u16Reg,
- uint8_t DataLen, uint32_t DataVal,
- int peci_fd, uint8_t* cc);
+EPECIStatus peci_WrEndPointConfig_seq_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8MsgType, uint8_t u8Seg,
+ uint8_t u8Bus, uint8_t u8Device, uint8_t u8Fcn, uint16_t u16Reg,
+ uint8_t DataLen, uint32_t DataVal, int peci_fd, uint8_t* cc);
// Provides write access to the EP PCI MMIO space
-EPECIStatus peci_WrEndPointConfigMmio(uint8_t target, uint8_t u8Seg,
- uint8_t u8Bus, uint8_t u8Device,
- uint8_t u8Fcn, uint8_t u8Bar,
- uint8_t u8AddrType, uint64_t u64Offset,
- uint8_t u8DataLen, uint64_t u64DataVal,
- uint8_t* cc);
+EPECIStatus peci_WrEndPointConfigMmio(
+ uint8_t target, uint8_t u8Seg, uint8_t u8Bus, uint8_t u8Device,
+ uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType, uint64_t u64Offset,
+ uint8_t u8DataLen, uint64_t u64DataVal, uint8_t* cc);
// Provides write access to the EP PCI MMIO space in the specified domain
-EPECIStatus peci_WrEndPointConfigMmio_dom(uint8_t target, uint8_t domainId,
- uint8_t u8Seg, uint8_t u8Bus,
- uint8_t u8Device, uint8_t u8Fcn,
- uint8_t u8Bar, uint8_t u8AddrType,
- uint64_t u64Offset, uint8_t u8DataLen,
- uint64_t u64DataVal, uint8_t* cc);
+EPECIStatus peci_WrEndPointConfigMmio_dom(
+ uint8_t target, uint8_t domainId, uint8_t u8Seg, uint8_t u8Bus,
+ uint8_t u8Device, uint8_t u8Fcn, uint8_t u8Bar, uint8_t u8AddrType,
+ uint64_t u64Offset, uint8_t u8DataLen, uint64_t u64DataVal, uint8_t* cc);
// Allows sequential write access to the EP PCI MMIO space
EPECIStatus peci_WrEndPointConfigMmio_seq(
@@ -409,29 +370,25 @@
uint8_t* cc);
// Provides access to the Crashdump Discovery API
-EPECIStatus peci_CrashDump_Discovery(uint8_t target, uint8_t subopcode,
- uint8_t param0, uint16_t param1,
- uint8_t param2, uint8_t u8ReadLen,
- uint8_t* pData, uint8_t* cc);
+EPECIStatus peci_CrashDump_Discovery(
+ uint8_t target, uint8_t subopcode, uint8_t param0, uint16_t param1,
+ uint8_t param2, uint8_t u8ReadLen, uint8_t* pData, uint8_t* cc);
// Provides access to the Crashdump Discovery API in the specified domain
-EPECIStatus peci_CrashDump_Discovery_dom(uint8_t target, uint8_t domainId,
- uint8_t subopcode, uint8_t param0,
- uint16_t param1, uint8_t param2,
- uint8_t u8ReadLen, uint8_t* pData,
- uint8_t* cc);
+EPECIStatus peci_CrashDump_Discovery_dom(
+ uint8_t target, uint8_t domainId, uint8_t subopcode, uint8_t param0,
+ uint16_t param1, uint8_t param2, uint8_t u8ReadLen, uint8_t* pData,
+ uint8_t* cc);
// Provides access to the Crashdump GetFrame API
-EPECIStatus peci_CrashDump_GetFrame(uint8_t target, uint16_t param0,
- uint16_t param1, uint16_t param2,
- uint8_t u8ReadLen, uint8_t* pData,
- uint8_t* cc);
+EPECIStatus peci_CrashDump_GetFrame(
+ uint8_t target, uint16_t param0, uint16_t param1, uint16_t param2,
+ uint8_t u8ReadLen, uint8_t* pData, uint8_t* cc);
// Provides access to the Crashdump GetFrame API in the specified domain
-EPECIStatus peci_CrashDump_GetFrame_dom(uint8_t target, uint8_t domainId,
- uint16_t param0, uint16_t param1,
- uint16_t param2, uint8_t u8ReadLen,
- uint8_t* pData, uint8_t* cc);
+EPECIStatus peci_CrashDump_GetFrame_dom(
+ uint8_t target, uint8_t domainId, uint16_t param0, uint16_t param1,
+ uint16_t param2, uint8_t u8ReadLen, uint8_t* pData, uint8_t* cc);
// Provides raw PECI command access
EPECIStatus peci_raw(uint8_t target, uint8_t u8ReadLen, const uint8_t* pRawCmd,