commit 37bc6ebbc79f7a1938ca8e42ead73250cddd3be6
author Thang Q. Nguyen <thang@os.amperecomputing.com> Wed Dec 23 04:45:53 2020 +0000
committer Thang Q. Nguyen <thang@os.amperecomputing.com> Thu Dec 24 01:29:17 2020 +0000
tree 41093b10f0a8c78dbc8948ff293d0dafc4baf60a
parent 80e56de67461a875ec237e4d80dab3a49a5c29e4

meta-ampere: u-boot: Disable internal PD resistors for GPIOs

Configure SCU8C - Multi-function pin control 4 to disable internal pull
down resistors for GPIOJ, GPIOG/GPIOAB, GPIOD/GPIOY, GPIOC/GPIOS as
external resistors are already installed.

Tested: scan I2C4 and check devices on the bus are detected

Signed-off-by: Thinh Pham <thinh.pham@amperecomputing.com>
Signed-off-by: Thang Q. Nguyen <thang@os.amperecomputing.com>
Change-Id: I5a4b682310b5243830bd9c7a66889b0a52c4770c

meta-jade/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend

diff --git a/meta-jade/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend b/meta-jade/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend
index 983dc24..c40bfcd 100644
--- a/meta-jade/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend
+++ b/meta-jade/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend
@@ -2,4 +2,5 @@
 
 SRC_URI += " \
             file://0001-aspeed-scu-Switch-PWM-pin-to-GPIO-input-mode.patch \
+            file://0002-aspeed-Disable-internal-PD-resistors-for-GPIOs.patch \
            "