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gerrit.openbmc.org / openbmc / meta-nuvoton / e7db9495062eab77a319e6eb322cdfe0f68719d8
commite7db9495062eab77a319e6eb322cdfe0f68719d8[log] [tgz]
authorBenjamin Fair <benjaminfair@google.com>Mon Dec 21 16:51:42 2020 -0800
committerBenjamin Fair <benjaminfair@google.com>Mon Dec 21 16:56:39 2020 -0800
treeebfbfc7e5851c97c868d17a1c485301748c218fb
parentf525a14ffcd06c41c512565ace585910a36e2c02 [diff]
meta-nuvoton: npcm7xx-bootblock: upgrade to 10.10.16

Changelog from 10.10.09:
 * MC: Enhanced training optimization.
 * SPI0 frequency is now only limited to be up to 50MHz (remove 40MHz
lower limit). This check is only performed if PLLs are changes (RUN_BMC
or new header frequency values).
 * Fix an issue in INTCR3 settings (FIU_FIX field).
 * MC: in enhanced training: change the sweep range accrording to the
location of the step. (run time optimization)

Change-Id: If9046785349b7eae9e98f57a40c3eb0c0e9994cc
Signed-off-by: Benjamin Fair <benjaminfair@google.com>
1 file changed
tree: ebfbfc7e5851c97c868d17a1c485301748c218fb
  1. conf/
  2. recipes-bsp/
  3. recipes-kernel/
  4. recipes-nuvoton/
  5. COPYING.apache-2.0
  6. COPYING.MIT
  7. LICENSE
  8. MAINTAINERS
  9. README.md
  10. recipes.txt
README.md

Nuvoton NPCM7XX

This is the Nuvoton NPCM7XX Board Support Package (BSP) layer. The NPCM7XX is an ARM based SoC with external DDR RAM and supports a large set of peripherals made by Nuvoton. More information about the NPCM7XX can be found here.