meta-quanta: runbmc-nuvoton: images: Add runbmc XML files
Nuvoton's full flash image includes also a bootloader called Bootblock,
and headers for it and for the u-boot. Generating headers and merging
the Bootblock and the u-boot are being done by Nuvoton's binary
generator tool (Bingo), which uses external paramteres from XML files
for that.
Change-Id: Ibf3c424c29fd81f88f86e38f50e95cef1e39386b
Signed-off-by: Joseph Liu <kwliu@nuvoton.com>
diff --git a/meta-runbmc-nuvoton/recipes-bsp/images/files/BootBlockAndHeader_RunBMC.xml b/meta-runbmc-nuvoton/recipes-bsp/images/files/BootBlockAndHeader_RunBMC.xml
new file mode 100644
index 0000000..58723e6
--- /dev/null
+++ b/meta-runbmc-nuvoton/recipes-bsp/images/files/BootBlockAndHeader_RunBMC.xml
@@ -0,0 +1,166 @@
+<!-- SPDX-License-Identifier: GPL-2.0
+#
+# Nuvoton IGPS: Image Generation And Programming Scripts For Poleg BMC
+#
+# Copyright (C) 2018 Nuvoton Technologies, All Rights Reserved
+#--------------------------------------------------------------------------->
+
+<?xml version="1.0" encoding="UTF-8"?>
+
+<Bin_Ecc_Map>
+ <!-- BMC mandatory fields -->
+ <ImageProperties>
+ <BinSize>0</BinSize> <!-- If 0 the binary size will be calculated by the tool -->
+ <PadValue>0xFF</PadValue> <!-- Byte value to pad the empty areas, default is 0 -->
+ </ImageProperties>
+
+ <BinField>
+ <!-- BootBlock tag (0x50 0x07 0x55 0xAA 0x54 0x4F 0x4F 0x42) or
+ uboot tag (0x55 0x42 0x4F 0x4F 0x54 0x42 0x4C 0x4B) -->
+ <name>StartTag</name> <!-- name of field -->
+ <config>
+ <offset>0</offset> <!-- offset in the header -->
+ <size>0x8</size> <!-- size in the header -->
+ </config>
+ <content format='bytes'>0x50 0x07 0x55 0xAA 0x54 0x4F 0x4F 0x42</content> <!-- content the user should fill -->
+ </BinField>
+
+ <BinField>
+ <!-- Code destination address, 32-bit aligned: for BootBlock should be 0xFFFD5E00 so code will run in 0xFFFD6000 as linked for -->
+ <name>DestAddr</name> <!-- name of field -->
+ <config>
+ <offset>0x140</offset> <!-- offset in the header -->
+ <size>0x4</size> <!-- size in the header -->
+ </config>
+ <content format='32bit'>0xFFFD5E00</content> <!-- content the user should fill -->
+ </BinField>
+
+ <BinField>
+ <!-- BootBlock or u-boot Code size -->
+ <name>CodeSize</name> <!-- name of field -->
+ <config>
+ <offset>0x144</offset> <!-- offset in the header -->
+ <size>0x4</size> <!-- size in the header -->
+ </config>
+ <content format='FileSize'>Poleg_bootblock.bin</content> <!-- content the user should fill -->
+ </BinField>
+
+ <BinField>
+ <!-- The BootBlock or u-boot binary file -->
+ <name>Code</name> <!-- name of field -->
+ <config>
+ <offset>0x200</offset> <!-- offset in the header -->
+ <size format='FileSize'>Poleg_bootblock.bin</size> <!-- size in the header calculated by tool-->
+ </config>
+ <content format='FileContent'>Poleg_bootblock.bin</content> <!-- content the user should fill -->
+ </BinField>
+
+ <!-- BMC optional fields -->
+ <BinField>
+ <!-- Word contents copied by ROM code to FIU0 FIU_DRD_CFG register -->
+ <name>FIU0_DRD_CFG_Set</name> <!-- name of field -->
+ <config>
+ <offset>0x108</offset> <!-- offset in the header -->
+ <size>0x4</size> <!-- size in the header -->
+ </config>
+ <content format='32bit'>0x030011BB</content> <!-- content the user should fill -->
+ </BinField>
+
+ <BinField>
+ <!-- Defines the clock divide ratio from AHB to FIU0 clock -->
+ <name>FIU_Clk_Divider</name> <!-- name of field -->
+ <config>
+ <offset>0x10C</offset> <!-- offset in the header -->
+ <size>0x1</size> <!-- size in the header -->
+ </config>
+ <content format='bytes'>4</content> <!-- content the user should fill -->
+ </BinField>
+
+ <BinField>
+ <!-- Version (Major.Minor) -->
+ <name>Version</name> <!-- name of field -->
+ <config>
+ <offset>0x148</offset> <!-- offset in the header -->
+ <size>0x4</size> <!-- size in the header -->
+ </config>
+ <content format='32bit'>0x0201</content> <!-- content the user should fill -->
+ </BinField>
+
+ <BinField>
+ <!-- Board manufaturer ( Dell = 0, Nuvoton = 100, Google = 1, MS = 2) -->
+ <name>BOARD_VENDOR</name> <!-- name of field -->
+ <config>
+ <offset>0x124</offset> <!-- offset in the header -->
+ <size>0x4</size> <!-- size in the header -->
+ </config>
+ <content format='32bit'>100</content> <!--Board_manufacturer: Nuvoton-->
+ </BinField>
+ <BinField>
+ <!-- Board type ( DRB = 0, SVB = 1, EB = 2,HORIZON = 3, SANDSTORM = 4, ROCKAWAY = 100 RunBMC = 10) -->
+ <!-- WARNING: Currently this value is only printed to serial. Set BOARD_VENDOR to 1 get Dell specific customization. -->
+ <name>BOARD_TYPE</name> <!-- name of field -->
+ <config>
+ <offset>0x120</offset> <!-- offset in the header -->
+ <size>0x4</size> <!-- size in the header -->
+ </config>
+ <content format='32bit'>0x0A</content> <!--Board_type: SVB-->
+ </BinField>
+
+ <!-- the next two fields are available since version 10.7.0 -->
+ <BinField>
+ <!-- supported values: 333,444,500,600,666,700,720,750,775,787,800,825,850,900,950,1000,1060 -->
+ <name>MC_FREQ_IN_MHZ</name> <!-- name of field -->
+ <config>
+ <offset>0x128</offset> <!-- offset in the header -->
+ <size>0x2</size> <!-- size in the header -->
+ </config>
+ <content format='32bit'>800</content>
+ </BinField>
+ <BinField>
+ <!-- supporeted values: 333,500,600,666,700,720,750,800,825,850,900,950,1000,1060 -->
+ <name>CPU_FREQ_IN_MHZ</name> <!-- name of field -->
+ <config>
+ <offset>0x12A</offset> <!-- offset in the header -->
+ <size>0x2</size> <!-- size in the header -->
+ </config>
+ <content format='32bit'>800</content>
+ </BinField>
+
+ <BinField>
+ <!-- MC_CONFIG.
+ Bit 0: MC_DISABLE_CAPABILITY_INPUT_DQS_ENHANCE_TRAINING (0x01)
+ Bit 1: MC_CAPABILITY_IGNORE_ECC_DEVICE (0x02) -->
+ <name>MC_CONFIG</name> <!-- name of field -->
+ <config>
+ <offset>0x12C</offset> <!-- offset in the header -->
+ <size>0x1</size> <!-- size in the header -->
+ </config>
+ <content format='32bit'>0x01</content>
+ </BinField>
+
+ <BinField>
+ <!-- HOST_IF.
+ 0xFF: LPC backward compatible
+ 0x00: LPC.
+ 0x01: eSPI
+ 0x02: GPIOs TRIS. -->
+ <name>HOST_IF</name> <!-- name of field -->
+ <config>
+ <offset>0x12D</offset> <!-- offset in the header -->
+ <size>0x1</size> <!-- size in the header -->
+ </config>
+ <content format='32bit'>0x00</content>
+ </BinField>
+
+ <!-- reserved fields -->
+ <BinField>
+ <!-- reserved field for sample -->
+ <name>My_reserved</name> <!-- name of field -->
+ <config>
+ <offset>0x110</offset> <!-- offset in the header -->
+ <size>0x4</size> <!-- size in the header -->
+ </config>
+ <content format='bytes'>0xFF 0xFF 0xFF 0xFF</content> <!-- content the user should fill -->
+ </BinField>
+
+</Bin_Ecc_Map>
diff --git a/meta-runbmc-nuvoton/recipes-bsp/images/files/UbootHeader_RunBMC.xml b/meta-runbmc-nuvoton/recipes-bsp/images/files/UbootHeader_RunBMC.xml
new file mode 100644
index 0000000..1612a83
--- /dev/null
+++ b/meta-runbmc-nuvoton/recipes-bsp/images/files/UbootHeader_RunBMC.xml
@@ -0,0 +1,191 @@
+<!-- SPDX-License-Identifier: GPL-2.0
+#
+# Nuvoton IGPS: Image Generation And Programming Scripts For Poleg BMC
+#
+# Copyright (C) 2018 Nuvoton Technologies, All Rights Reserved
+#--------------------------------------------------------------------------->
+
+<?xml version="1.0" encoding="UTF-8"?>
+
+<Bin_Ecc_Map>
+ <!-- BMC mandatory fields -->
+ <ImageProperties>
+ <BinSize>0</BinSize> <!-- If 0 the binary size will be calculated by the tool -->
+ <PadValue>0xFF</PadValue> <!-- Byte value to pad the empty areas, default is 0 -->
+ </ImageProperties>
+
+ <BinField>
+ <!-- BootBlock tag (0x50 0x07 0x55 0xAA 0x54 0x4F 0x4F 0x42) or
+ uboot tag (0x55 0x42 0x4F 0x4F 0x54 0x42 0x4C 0x4B) -->
+ <name>StartTag</name> <!-- name of field -->
+ <config>
+ <offset>0</offset> <!-- offset in the header -->
+ <size>0x8</size> <!-- size in the header -->
+ </config>
+ <content format='bytes'>0x55 0x42 0x4F 0x4F 0x54 0x42 0x4C 0x4B</content> <!-- content the user should fill -->
+ </BinField>
+
+ <BinField>
+ <!-- Code destination address, 32-bit aligned: for u-boot should be 0x80005000 so code will run in 0x80005200 as linked for -->
+ <name>DestAddr</name> <!-- name of field -->
+ <config>
+ <offset>0x140</offset> <!-- offset in the header -->
+ <size>0x4</size> <!-- size in the header -->
+ </config>
+ <content format='32bit'>0x8000</content> <!-- content the user should fill -->
+ </BinField>
+
+ <BinField>
+ <!-- BootBlock or u-boot Code size -->
+ <name>CodeSize</name> <!-- name of field -->
+ <config>
+ <offset>0x144</offset> <!-- offset in the header -->
+ <size>0x4</size> <!-- size in the header -->
+ </config>
+ <content format='FileSize'>u-boot.bin</content> <!-- content the user should fill -->
+ </BinField>
+
+ <BinField>
+ <!-- The BootBlock or u-boot binary file -->
+ <name>Code</name> <!-- name of field -->
+ <config>
+ <offset>0x200</offset> <!-- offset in the header -->
+ <size format='FileSize'>u-boot.bin</size> <!-- size in the header calculated by tool-->
+ </config>
+ <content format='FileContent'>u-boot.bin</content> <!-- content the user should fill -->
+ </BinField>
+
+ <!-- BMC optional fields -->
+ <BinField>
+ <!-- Word contents copied by ROM code to FIU0 FIU_DRD_CFG register -->
+ <name>FIU0_DRD_CFG_Set</name> <!-- name of field -->
+ <config>
+ <offset>0x108</offset> <!-- offset in the header -->
+ <size>0x4</size> <!-- size in the header -->
+ </config>
+ <content format='32bit'>0x030111BC</content> <!-- content the user should fill 0x030032EB -->
+ </BinField>
+
+ <BinField>
+ <!-- Defines the clock divide ratio from AHB to FIU0 clock -->
+ <name>FIU0_Clk_Divider</name> <!-- name of field -->
+ <config>
+ <offset>0x10C</offset> <!-- offset in the header -->
+ <size>0x1</size> <!-- size in the header -->
+ </config>
+ <content format='bytes'>0</content> <!-- content the user should fill -->
+ </BinField>
+
+ <BinField>
+ <!-- Defines if FIU0 CS1 is enabled -->
+ <name>fiu0_cs1_en</name> <!-- name of field -->
+ <config>
+ <offset>0x10D</offset> <!-- offset in the header -->
+ <size>0x1</size> <!-- size in the header -->
+ </config>
+ <content format='bytes'>0x0</content> <!-- content the user should fill -->
+ </BinField>
+
+ <BinField>
+ <!-- Defines if FIU0 CS2 is enabled -->
+ <name>fiu0_cs2_en</name> <!-- name of field -->
+ <config>
+ <offset>0x10E</offset> <!-- offset in the header -->
+ <size>0x1</size> <!-- size in the header -->
+ </config>
+ <content format='bytes'>0x0</content> <!-- content the user should fill -->
+ </BinField>
+
+ <BinField>
+ <!-- Defines if FIU0 CS3 is enabled -->
+ <name>fiu0_cs3_en</name> <!-- name of field -->
+ <config>
+ <offset>0x10F</offset> <!-- offset in the header -->
+ <size>0x1</size> <!-- size in the header -->
+ </config>
+ <content format='bytes'>0x0</content> <!-- content the user should fill -->
+ </BinField>
+
+ <!-- BMC optional fields -->
+ <BinField>
+ <!-- Word contents copied by ROM code to FIU3 FIU_DRD_CFG register -->
+ <name>FIU3_DRD_CFG_Set</name> <!-- name of field -->
+ <config>
+ <offset>0x110</offset> <!-- offset in the header -->
+ <size>0x4</size> <!-- size in the header -->
+ </config>
+ <content format='32bit'>0x030011BB</content> <!-- content the user should fill -->
+ </BinField>
+
+ <!-- BMC optional fields -->
+ <BinField>
+ <!-- Word contents copied by ROM code to FIU3 FIU_DRD_CFG register -->
+ <name>FIU3_DWR_CFG_Set</name> <!-- name of field -->
+ <config>
+ <offset>0x114</offset> <!-- offset in the header -->
+ <size>0x4</size> <!-- size in the header -->
+ </config>
+ <content format='32bit'>0x0</content> <!-- content the user should fill -->
+ </BinField>
+
+ <BinField>
+ <!-- Defines the clock divide ratio from AHB to FIU3 clock -->
+ <name>FIU3_Clk_Divider</name> <!-- name of field -->
+ <config>
+ <offset>0x118</offset> <!-- offset in the header -->
+ <size>0x1</size> <!-- size in the header -->
+ </config>
+ <content format='bytes'>0x0</content> <!-- content the user should fill -->
+ </BinField>
+
+ <BinField>
+ <!-- Defines if FIU3 CS0 is enabled -->
+ <name>fiu3_cs0_en</name> <!-- name of field -->
+ <config>
+ <offset>0x119</offset> <!-- offset in the header -->
+ <size>0x1</size> <!-- size in the header -->
+ </config>
+ <content format='bytes'>0x0</content> <!-- content the user should fill -->
+ </BinField>
+
+ <BinField>
+ <!-- Defines if FIU3 CS1 is enabled -->
+ <name>fiu3_cs1_en</name> <!-- name of field -->
+ <config>
+ <offset>0x11A</offset> <!-- offset in the header -->
+ <size>0x1</size> <!-- size in the header -->
+ </config>
+ <content format='bytes'>0x0</content> <!-- content the user should fill -->
+ </BinField>
+
+ <BinField>
+ <!-- Defines if FIU3 CS2 is enabled -->
+ <name>fiu3_cs2_en</name> <!-- name of field -->
+ <config>
+ <offset>0x11B</offset> <!-- offset in the header -->
+ <size>0x1</size> <!-- size in the header -->
+ </config>
+ <content format='bytes'>0x0</content> <!-- content the user should fill -->
+ </BinField>
+
+ <BinField>
+ <!-- Defines if FIU3 CS3 is enabled -->
+ <name>fiu3_cs3_en</name> <!-- name of field -->
+ <config>
+ <offset>0x11C</offset> <!-- offset in the header -->
+ <size>0x1</size> <!-- size in the header -->
+ </config>
+ <content format='bytes'>0x0</content> <!-- content the user should fill -->
+ </BinField>
+
+ <BinField>
+ <!-- Version (Major.Minor) -->
+ <name>Version</name> <!-- name of field -->
+ <config>
+ <offset>0x148</offset> <!-- offset in the header -->
+ <size>0x4</size> <!-- size in the header -->
+ </config>
+ <content format='32bit'>0x0201</content> <!-- content the user should fill -->
+ </BinField>
+
+</Bin_Ecc_Map>
diff --git a/meta-runbmc-nuvoton/recipes-bsp/images/npcm7xx-bingo-native_%.bbappend b/meta-runbmc-nuvoton/recipes-bsp/images/npcm7xx-bingo-native_%.bbappend
new file mode 100644
index 0000000..664fcb0
--- /dev/null
+++ b/meta-runbmc-nuvoton/recipes-bsp/images/npcm7xx-bingo-native_%.bbappend
@@ -0,0 +1,12 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+SRC_URI_remove = "file://BootBlockAndHeader_EB.xml"
+SRC_URI_remove = "file://UbootHeader_EB.xml"
+SRC_URI += " file://BootBlockAndHeader_RunBMC.xml"
+SRC_URI += " file://UbootHeader_RunBMC.xml"
+
+
+do_install_append() {
+ install ${WORKDIR}/BootBlockAndHeader_RunBMC.xml ${D}${bindir}/BootBlockAndHeader_EB.xml
+ install ${WORKDIR}/UbootHeader_RunBMC.xml ${D}${bindir}/UbootHeader_EB.xml
+}
+