commit b6d7b7e5091b5b2d72b51f100cedca78f4d857e3
author Sridevi Ramesh <sridevra@in.ibm.com> Tue Nov 07 03:49:52 2017 -0600
committer George Keishing <gkeishin@in.ibm.com> Fri Nov 17 05:55:40 2017 +0000
tree e0e197ce068e215ff9efdac2c3d889bb467ab24c
parent e7b0bb01241fdb8377e85569a734cbbc38085cce

Error injection through OS related automation [stage 3].

Automating error injection scenarios as shown below
RE TH limit 1 ---> NCUFIR
RE TH limit 32 --> EQFIR
UE ---> L2, L3, CXA

Resolves openbmc/openbmc-test-automation#1081

Change-Id: Ie87688fbf7fb456fda98b96085117c1395777ee2
Signed-off-by: Sridevi Ramesh <sridevra@in.ibm.com>

lib/ras/variables.py

diff --git a/lib/ras/variables.py b/lib/ras/variables.py
index 1bf97c8..0964259 100644
--- a/lib/ras/variables.py
+++ b/lib/ras/variables.py
@@ -29,7 +29,7 @@
 
 DES_L3_RECV1 = "'L3FIR[^17].*Received addr_error cresp'"
 DES_L3_RECV32 = "'L3FIR[^7].*L3 cache write data CE'"
-DES_L3_UE = "'L3FIR[^8].*L3 cache write data UE'"
+DES_L3_UE = "'L3FIR[^16].*addr_error cresp for mem'"
 
 DES_OCC_RECV1 = "'OCCFIR[^45].*C405_ECC_CE'"
 DES_CME_RECV1 = "'CMEFIR[^7].*PPE SRAM Uncorrectable Err'"
@@ -63,7 +63,7 @@
              'L2FIR_UE': ['10010800', '0040000000000000', DES_L2_UE],
              'L3FIR_RECV1': ['10011800','0000400000000000', DES_L3_RECV1],
              'L3FIR_RECV32': ['10011800', '0100000000000000', DES_L3_RECV32],
-             'L3FIR_UE': ['10011800', '0080000000000000', DES_L3_UE],
+             'L3FIR_UE': ['10011800', '0000800000000000', DES_L3_UE],
              'OCCFIR_RECV1': ['01010800', '0000000000040000', DES_OCC_RECV1],
              'CMEFIR_RECV1': ['10012000', '0100000000000000', DES_CME_RECV1],
              'EQFIR_RECV32': ['1004000A', '8000000000000000', DES_EQ_RECV32],