reset upstream subtrees to yocto 2.6
Reset the following subtrees on thud HEAD:
poky: 87e3a9739d
meta-openembedded: 6094ae18c8
meta-security: 31dc4e7532
meta-raspberrypi: a48743dc36
meta-xilinx: c42016e2e6
Also re-apply backports that didn't make it into thud:
poky:
17726d0 systemd-systemctl-native: handle Install wildcards
meta-openembedded:
4321a5d libtinyxml2: update to 7.0.1
042f0a3 libcereal: Add native and nativesdk classes
e23284f libcereal: Allow empty package
030e8d4 rsyslog: curl-less build with fmhttp PACKAGECONFIG
179a1b9 gtest: update to 1.8.1
Squashed OpenBMC subtree compatibility updates:
meta-aspeed:
Brad Bishop (1):
aspeed: add yocto 2.6 compatibility
meta-ibm:
Brad Bishop (1):
ibm: prepare for yocto 2.6
meta-ingrasys:
Brad Bishop (1):
ingrasys: set layer compatibility to yocto 2.6
meta-openpower:
Brad Bishop (1):
openpower: set layer compatibility to yocto 2.6
meta-phosphor:
Brad Bishop (3):
phosphor: set layer compatibility to thud
phosphor: libgpg-error: drop patches
phosphor: react to fitimage artifact rename
Ed Tanous (4):
Dropbear: upgrade options for latest upgrade
yocto2.6: update openssl options
busybox: remove upstream watchdog patch
systemd: Rebase CONFIG_CGROUP_BPF patch
Change-Id: I7b1fe71cca880d0372a82d94b5fd785323e3a9e7
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
diff --git a/poky/meta/recipes-core/glibc/glibc/0020-eglibc-Clear-cache-lines-on-ppc8xx.patch b/poky/meta/recipes-core/glibc/glibc/0020-eglibc-Clear-cache-lines-on-ppc8xx.patch
new file mode 100644
index 0000000..6e475a7
--- /dev/null
+++ b/poky/meta/recipes-core/glibc/glibc/0020-eglibc-Clear-cache-lines-on-ppc8xx.patch
@@ -0,0 +1,80 @@
+From 6c23660d035e71de0e20b40460ad3050bd057665 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Thu, 31 Dec 2015 15:15:09 -0800
+Subject: [PATCH] eglibc: Clear cache lines on ppc8xx
+
+2007-06-13 Nathan Sidwell <nathan@codesourcery.com>
+ Mark Shinwell <shinwell@codesourcery.com>
+
+ * sysdeps/unix/sysv/linux/powerpc/libc-start.c
+ (__libc_start_main): Detect 8xx parts and clear
+ __cache_line_size if detected.
+ * sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c
+ (DL_PLATFORM_AUXV): Likewise.
+
+Upstream-Status: Pending
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c | 14 +++++++++++++-
+ sysdeps/unix/sysv/linux/powerpc/libc-start.c | 16 +++++++++++++++-
+ 2 files changed, 28 insertions(+), 2 deletions(-)
+
+diff --git a/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c b/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c
+index 78051bc7bc..e24f442320 100644
+--- a/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c
++++ b/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c
+@@ -24,9 +24,21 @@ int __cache_line_size attribute_hidden;
+ /* Scan the Aux Vector for the "Data Cache Block Size" entry. If found
+ verify that the static extern __cache_line_size is defined by checking
+ for not NULL. If it is defined then assign the cache block size
+- value to __cache_line_size. */
++ value to __cache_line_size. This is used by memset to
++ optimize setting to zero. We have to detect 8xx processors, which
++ have buggy dcbz implementations that cannot report page faults
++ correctly. That requires reading SPR, which is a privileged
++ operation. Fortunately 2.2.18 and later emulates PowerPC mfspr
++ reads from the PVR register. */
+ #define DL_PLATFORM_AUXV \
+ case AT_DCACHEBSIZE: \
++ if (__LINUX_KERNEL_VERSION >= 0x020218) \
++ { \
++ unsigned pvr = 0; \
++ asm ("mfspr %0, 287" : "=r" (pvr)); \
++ if ((pvr & 0xffff0000) == 0x00500000) \
++ break; \
++ } \
+ __cache_line_size = av->a_un.a_val; \
+ break;
+
+diff --git a/sysdeps/unix/sysv/linux/powerpc/libc-start.c b/sysdeps/unix/sysv/linux/powerpc/libc-start.c
+index f2ad0c355d..3e6773795e 100644
+--- a/sysdeps/unix/sysv/linux/powerpc/libc-start.c
++++ b/sysdeps/unix/sysv/linux/powerpc/libc-start.c
+@@ -73,11 +73,25 @@ __libc_start_main (int argc, char **argv,
+
+ /* Initialize the __cache_line_size variable from the aux vector. For the
+ static case, we also need _dl_hwcap, _dl_hwcap2 and _dl_platform, so we
+- can call __tcb_parse_hwcap_and_convert_at_platform (). */
++ can call __tcb_parse_hwcap_and_convert_at_platform ().
++
++ This is used by memset to optimize setting to zero. We have to
++ detect 8xx processors, which have buggy dcbz implementations that
++ cannot report page faults correctly. That requires reading SPR,
++ which is a privileged operation. Fortunately 2.2.18 and later
++ emulates PowerPC mfspr reads from the PVR register. */
+ for (ElfW (auxv_t) * av = auxvec; av->a_type != AT_NULL; ++av)
+ switch (av->a_type)
+ {
+ case AT_DCACHEBSIZE:
++ if (__LINUX_KERNEL_VERSION >= 0x020218)
++ {
++ unsigned pvr = 0;
++
++ asm ("mfspr %0, 287" : "=r" (pvr) :);
++ if ((pvr & 0xffff0000) == 0x00500000)
++ break;
++ }
+ __cache_line_size = av->a_un.a_val;
+ break;
+ #ifndef SHARED