| From 5a9b6a004f89fdd95b0470e1324dc4dee8c41d24 Mon Sep 17 00:00:00 2001 |
| From: Claudiu Zissulescu <claziss@synopsys.com> |
| Date: Wed, 9 Jun 2021 12:12:57 +0300 |
| Subject: [PATCH] arc: Update doloop_end patterns |
| |
| ARC processor can use LP instruction to implement zero overlay loops. |
| The current inplementation doesn't handle the unlikely situation when |
| the loop iterator is located in memory. Refurbish the loop_end insn |
| pattern into a define_insn_and_split pattern. |
| |
| gcc/ |
| 2021-07-09 Claudiu Zissulescu <claziss@synopsys.com> |
| |
| * config/arc/arc.md (loop_end): Change it to |
| define_insn_and_split. |
| |
| Upstream-Status: Backport [https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=5a9b6a004f89fdd95b0470e1324dc4dee8c41d24] |
| |
| Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com> |
| (cherry picked from commit 174e75a210753b68de0f2c398a13ace0f512e35b) |
| Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> |
| --- |
| gcc/config/arc/arc.md | 46 ++++++++++++++++++++-------------------------- |
| 1 file changed, 20 insertions(+), 26 deletions(-) |
| |
| diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md |
| index 2a7e087ff72..d704044c13f 100644 |
| --- a/gcc/config/arc/arc.md |
| +++ b/gcc/config/arc/arc.md |
| @@ -4986,7 +4986,7 @@ core_3, archs4x, archs4xd, archs4xd_slow" |
| (define_expand "doloop_end" |
| [(parallel [(set (pc) |
| (if_then_else |
| - (ne (match_operand 0 "" "") |
| + (ne (match_operand 0 "nonimmediate_operand") |
| (const_int 1)) |
| (label_ref (match_operand 1 "" "")) |
| (pc))) |
| @@ -5012,44 +5012,38 @@ core_3, archs4x, archs4xd, archs4xd_slow" |
| |
| ;; if by any chance the lp_count is not used, then use an 'r' |
| ;; register, instead of going to memory. |
| -(define_insn "loop_end" |
| - [(set (pc) |
| - (if_then_else (ne (match_operand:SI 2 "nonimmediate_operand" "0,m") |
| - (const_int 1)) |
| - (label_ref (match_operand 1 "" "")) |
| - (pc))) |
| - (set (match_operand:SI 0 "nonimmediate_operand" "=r,m") |
| - (plus (match_dup 2) (const_int -1))) |
| - (unspec [(const_int 0)] UNSPEC_ARC_LP) |
| - (clobber (match_scratch:SI 3 "=X,&r"))] |
| - "" |
| - "; ZOL_END, begins @%l1" |
| - [(set_attr "length" "0") |
| - (set_attr "predicable" "no") |
| - (set_attr "type" "loop_end")]) |
| - |
| ;; split pattern for the very slim chance when the loop register is |
| ;; memory. |
| -(define_split |
| +(define_insn_and_split "loop_end" |
| [(set (pc) |
| - (if_then_else (ne (match_operand:SI 0 "memory_operand") |
| + (if_then_else (ne (match_operand:SI 0 "nonimmediate_operand" "+r,!m") |
| (const_int 1)) |
| - (label_ref (match_operand 1 "")) |
| + (label_ref (match_operand 1 "" "")) |
| (pc))) |
| (set (match_dup 0) (plus (match_dup 0) (const_int -1))) |
| (unspec [(const_int 0)] UNSPEC_ARC_LP) |
| - (clobber (match_scratch:SI 2))] |
| - "memory_operand (operands[0], SImode)" |
| + (clobber (match_scratch:SI 2 "=X,&r"))] |
| + "" |
| + "@ |
| + ; ZOL_END, begins @%l1 |
| + #" |
| + "reload_completed && memory_operand (operands[0], Pmode)" |
| [(set (match_dup 2) (match_dup 0)) |
| - (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) |
| + (parallel |
| + [(set (reg:CC_ZN CC_REG) |
| + (compare:CC_ZN (plus:SI (match_dup 2) (const_int -1)) |
| + (const_int 0))) |
| + (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))]) |
| (set (match_dup 0) (match_dup 2)) |
| - (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0))) |
| (set (pc) |
| - (if_then_else (ne (reg:CC CC_REG) |
| + (if_then_else (ne (reg:CC_ZN CC_REG) |
| (const_int 0)) |
| (label_ref (match_dup 1)) |
| (pc)))] |
| - "") |
| + "" |
| + [(set_attr "length" "0,24") |
| + (set_attr "predicable" "no") |
| + (set_attr "type" "loop_end")]) |
| |
| (define_insn "loop_fail" |
| [(set (reg:SI LP_COUNT) |
| -- |
| 2.16.2 |
| |