From 149cf4619622d27641a2886cd8bf38a49ad88f87 Mon Sep 17 00:00:00 2001
From: Mahesh Bodapati <mbodapat@xilinx.com>
Date: Mon, 19 Feb 2018 18:06:16 +0530
Subject: [PATCH 37/54] [Patch,Microblaze]: update in constraints for bitfield
 insert and extract instructions.

---
 gcc/config/microblaze/microblaze.md | 43 ++++++-------------------------------
 1 file changed, 7 insertions(+), 36 deletions(-)

diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
index 8072ffc..9bb87ec 100644
--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
@@ -2476,33 +2476,17 @@
   DONE;
 }")
 
-(define_expand "extvsi"
+(define_expand "extzvsi"
   [(set (match_operand:SI 0 "register_operand" "r")
 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
 			 (match_operand:SI 2 "immediate_operand" "I")
 			 (match_operand:SI 3 "immediate_operand" "I")))]
 "TARGET_HAS_BITFIELD"
-"
-{
-  unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
-  unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
-
-  if ((len == 0) || (pos + len > 32) )
-    FAIL;
-
-  ;;if (!register_operand (operands[1], VOIDmode))
-  ;;  FAIL;
-  if (operands[0] == operands[1])
-  FAIL;
-  if (GET_CODE (operands[1]) == ASHIFT)
-  FAIL;
-;;  operands[2] = GEN_INT(INTVAL(operands[2])+1 );
- emit_insn (gen_extv_32 (operands[0], operands[1],
-			  operands[2], operands[3]));
-  DONE;
-}")
+""
+)
 
-(define_insn "extv_32"
+
+(define_insn "extzv_32"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
 			 (match_operand:SI 2 "immediate_operand" "I")
@@ -2519,21 +2503,8 @@
 			 (match_operand:SI 2 "immediate_operand" "I"))
 	(match_operand:SI 3 "register_operand" "r"))]
  "TARGET_HAS_BITFIELD"
-  "
-{
-  unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
-  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
-
-  if (len <= 0 || pos + len > 32)
-    FAIL;
-
-  ;;if (!register_operand (operands[0], VOIDmode))
-  ;;  FAIL;
-
-  emit_insn (gen_insv_32 (operands[0], operands[1],
-			  operands[2], operands[3]));
-  DONE;
-}")
+""
+)
 
 (define_insn "insv_32"
   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
-- 
2.7.4