Add meta-xilinx subtree
Import git://git.yoctoproject.org/meta-xilinx from 5fccc46503 as
meta-xilinx subtree.
Change-Id: I3d59bcf3a57cee588aab7f5cdd0287af66450c8a
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
diff --git a/meta-xilinx/meta-xilinx-bsp/COPYING.MIT b/meta-xilinx/meta-xilinx-bsp/COPYING.MIT
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index 0000000..89de354
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/COPYING.MIT
@@ -0,0 +1,17 @@
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
diff --git a/meta-xilinx/meta-xilinx-bsp/README.booting.md b/meta-xilinx/meta-xilinx-bsp/README.booting.md
new file mode 100644
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+++ b/meta-xilinx/meta-xilinx-bsp/README.booting.md
@@ -0,0 +1,266 @@
+Booting meta-xilinx boards
+==========================
+
+Contents
+--------
+
+* [Loading via JTAG](#loading-via-jtag)
+ * [XSDB](#xsdb)
+ * [Load Bitstream](#load-bitstream)
+ * [Load U-Boot (MicroBlaze)](#load-u-boot-microblaze)
+ * [Load U-Boot (Zynq)](#load-u-boot-zynq)
+ * [U-Boot Console](#u-boot-console)
+ * [Kernel, Root Filesystem and Device Tree](#kernel-root-filesystem-and-device-tree)
+ * [Booting via U-Boot](#booting-via-u-boot)
+* [Loading via SD](#loading-via-sd)
+ * [Preparing SD/MMC](#preparing-sdmmc)
+ * [Installing U-Boot](#installing-u-boot)
+ * [Installing Kernel and Device Tree](#installing-kernel-and-device-tree)
+ * [Installing Root Filesystem](#installing-root-filesystem)
+ * [U-Boot Configuration File](#u-boot-configuration-file)
+ * [Booting](#booting)
+* [Loading via TFTP](#loading-via-tftp)
+ * [Kernel, Root Filesystem and Device Tree](#kernel-root-filesystem-and-device-tree-1)
+ * [Booting via U-Boot](#booting-via-u-boot-1)
+
+
+Loading via JTAG
+----------------
+This boot flow requires the use of the Xilinx tools, specifically XSDB and the
+associated JTAG device drivers. This also requires access to the JTAG interface
+on the board, a number of Xilinx and third-party boards come with on-board JTAG
+modules.
+
+### XSDB
+Start `xsdb` and connect. Ensure that the target chip is visible.
+
+ $ xsdb
+ xsdb% connect
+ xsdb% targets
+
+### Load Bitstream
+**(Note: This step is only required for platforms which have a bitstream e.g.
+MicroBlaze.)**
+
+Download the bitstream for the system using XSDB with the `fpga -f` command. If
+a bitstream is available from meta-xilinx is will be located in the
+`deploy/images/<machine-name>/` directory.
+
+ xsdb% fpga -f download.bit
+
+### Load U-Boot (MicroBlaze)
+Download `u-boot.elf` to the target CPU via the use of XSDB.
+
+ xsdb% targets -set -filter {name =~ "MicroBlaze*"}
+ xsdb% rst
+ xsdb% dow u-boot.elf
+ xsdb% con
+
+### Load U-Boot (Zynq)
+Ensure the board is configured to boot from JTAG. The Zynq platform requires the
+loading of SPL first, this can be done by loading the `u-boot-spl.bin` and
+executing it at location `0x0`. `u-boot-spl.bin` is not output to the deploy
+directory by default, it can be obtained from the work directory for U-Boot
+(`git/spl/u-boot-spl.bin`) or can be extracted from `boot.bin` using
+`dd if=boot.bin of=u-boot-spl.bin bs=1 skip=2240`.
+
+ xsdb% targets -set -filter {name =~ "ARM*#0"}
+ xsdb% dow -data u-boot-spl.bin 0x0
+ xsdb% rwr pc 0x0
+ xsdb% con
+
+On the UART console the following should appear, indicating SPL was loaded.
+
+ U-Boot SPL 2016.01
+ Trying to boot from unknown boot device
+ SPL: Unsupported Boot Device!
+ SPL: failed to boot from all boot devices
+ ### ERROR ### Please RESET the board ###
+
+Once SPL has loaded U-Boot can now be loaded into memory and executed. Download
+`u-boot.elf` to the target.
+
+ xsdb% stop
+ xsdb% dow u-boot.elf
+ xsdb% con
+
+### U-Boot Console
+U-Boot will load and the console will be available on the UART interface.
+
+ ...
+ Hit any key to stop autoboot: 0
+ U-Boot>
+
+### Kernel, Root Filesystem and Device Tree
+Whilst it is possible to load the images via JTAG this connection is slow and
+this process can take a long time to execute (more than 10 minutes). If your
+system has ethernet it is recommended that you use TFTP to load these images
+using U-Boot.
+
+Once U-Boot has been loaded, pause the execution using XSDB and use the `dow`
+command to load the images into the targets memory. Once the images are loaded
+continue the execution and return to the U-Boot console.
+
+MicroBlaze (kc705-microblazeel):
+
+ xsdb% stop
+ xsdb% dow -data linux.bin.ub 0x85000000
+ xsdb% dow -data core-image-minimal-kc705-microblazeel.cpio.gz.u-boot 0x86000000
+ xsdb% dow -data kc705-microblazeel.dtb 0x84000000
+ xsdb% con
+
+Zynq:
+
+ xsdb% stop
+ xsdb% dow -data uImage 0x2000000
+ xsdb% dow -data core-image-minimal-<machine name>.cpio.gz.u-boot 0x3000000
+ xsdb% dow -data <machine name>.dtb 0x2A00000
+ xsdb% con
+
+### Booting via U-Boot
+At the U-Boot console use the `bootm` command to execute the kernel.
+
+MicroBlaze (kc705-microblazeel):
+
+ U-Boot> bootm 0x85000000 0x86000000 0x84000000
+
+Zynq:
+
+ U-Boot> bootm 0x2000000 0x3000000 0x2A00000
+
+
+Loading via SD
+---------------------
+**(Note: This section only applies to Zynq and ZynqMP.)**
+
+### Preparing SD/MMC
+Setup the card with the first partition formatted as FAT16. If you intend to
+boot with the root filesystem located on the SD card, also create a second
+partition formatted as EXT4.
+
+It is recommended that the first partition be at least 64MB in size, however
+this value will depend on whether using a ramdisk for the root filesystem and
+how large the ramdisk is.
+
+This section describes how to manually prepare and populate an SD card image.
+There are automation tools in OpenEmbedded that can generate disk images already
+formatted and prepared such that they can be written directly to a disk. Refer
+to the Yocto Project Development Manual for more details:
+ http://www.yoctoproject.org/docs/current/dev-manual/dev-manual.html#creating-partitioned-images
+
+### Installing U-Boot (Zynq)
+Add the following files to the first partition:
+
+* `boot.bin`
+* `u-boot.img`
+
+### Installing U-Boot (ZynqMP)
+Add the following files to the first partition:
+
+* `boot.bin`
+* `u-boot.bin`
+
+### Installing Kernel and Device Tree (Zynq)
+Add the following files to the first partition:
+
+* `uImage`
+* `<machine name>.dtb`
+
+### Installing Kernel and Device Tree (ZynqMP)
+Add the following files to the first partition:
+
+* `Image`
+* `<machine name>.dtb`
+
+### Install ARM Trusted Firmware (ZynqMP)
+Add the following file to the first partition:
+
+ * `atf-uboot.ub`
+
+### Install U-boot environment file (ZynqMP)
+Add the following file to the first partition:
+
+ * `uEnv.txt`
+
+### Installing Root Filesystem
+If using a ramdisk also add the `.cpio.gz.u-boot` type of root filesystem image
+to the first partition.
+
+* `core-image-minimal-<machine name>.cpio.gz.u-boot`
+
+If using the SD card as the root filesystem, populate the second partition with
+the content of the root filesystem. To install the root filesystem extract the
+corresponding tarball into the root of the second partition (the following
+command assumes that the second partition is mounted at /media/root).
+
+ tar x -C /media/root -f core-image-minimal-<machine name>.tar.gz
+
+### U-Boot Configuration File
+Also create the file `uEnv.txt` on the first partition of the SD card partition,
+with the following contents. Replacing the names of files where appropriate.
+
+ kernel_image=uImage
+ devicetree_image=<machine name>.dtb
+
+If using a ramdisk root filesystem setup the `ramdisk_image` variable.
+
+ ramdisk_image=core-image-minimal-<machine name>.cpio.gz.u-boot
+
+If using the SD card as the root filesystem setup the kernel boot args, and
+`uenvcmd` variable.
+
+ bootargs=root=/dev/mmcblk0p2 rw rootwait
+ uenvcmd=fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && bootm 0x3000000 - 0x2A00000
+
+### Booting
+Insert the SD card and connect UART to a terminal program and power on the
+board. (For boards that have configurable boot jumper/switches ensure the board
+is configured for SD).
+
+Initially U-Boot SPL will load, which will in turn load U-Boot. U-Boot will use
+the `uEnv.txt` to automatically load and execute the kernel.
+
+
+Loading via TFTP
+----------------
+**(Note: This boot flow requires ethernet on the baord and a TFTP server)**
+
+Boot your system into U-Boot, using one of boot methods (e.g. JTAG, SD, QSPI).
+
+### Kernel, Root Filesystem and Device Tree
+Place the following images into the root of the TFTP server directory:
+
+* `core-image-minimal-<machine name>.cpio.gz.u-boot`
+* `uImage` (Zynq) or `linux.bin.ub` (MicroBlaze)
+* `<machine name>.dtb`
+
+### Booting via U-Boot
+The serial console of the target board will display the U-Boot console.
+Configure the `ipaddr` and `serverip` of the U-Boot environment.
+
+ U-Boot> set serverip <server ip>
+ U-Boot> set ipaddr <board ip>
+
+Using the U-Boot console; load the Kernel, root filesystem and the DTB into
+memory. And then boot Linux using the `bootm` command. (Note the load addresses
+will be dependant on machine used)
+
+MicroBlaze (kc705-microblazeel):
+
+ U-Boot> tftpboot 0x85000000 linux.bin.ub
+ U-Boot> tftpboot 0x86000000 core-image-minimal-kc705-microblazeel.cpio.gz.u-boot
+ U-Boot> tftpboot 0x84000000 kc705-microblazeel.dtb
+ U-Boot> bootm 0x85000000 0x86000000 0x84000000
+
+Zynq:
+
+ U-Boot> tftpboot 0x2000000 uImage
+ U-Boot> tftpboot 0x3000000 core-image-minimal-<machine name>.cpio.gz.u-boot
+ U-Boot> tftpboot 0x2A00000 <machine name>.dtb
+ U-Boot> bootm 0x2000000 0x3000000 0x2A00000
+
+U-Boot will prepare the Kernel for boot and then it will being to execute.
+
+ ...
+ Starting kernel...
+
diff --git a/meta-xilinx/meta-xilinx-bsp/README.building.md b/meta-xilinx/meta-xilinx-bsp/README.building.md
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+++ b/meta-xilinx/meta-xilinx-bsp/README.building.md
@@ -0,0 +1,36 @@
+Build Instructions
+==================
+
+The following instructions require OE-Core meta and BitBake. Poky provides these
+components, however they can be acquired separately.
+
+Initialize a build using the `oe-init-build-env` script. Once initialized
+configure `bblayers.conf` by adding the `meta-xilinx-bsp` and
+`meta-xilinx-contrib` layer. e.g.:
+
+ BBLAYERS ?= " \
+ <path to layer>/oe-core/meta \
+ <path to layer>/meta-xilinx-bsp \
+ <path to layer>/meta-xilinx-contrib \
+ "
+
+meta-xilinx-contrib is a contribution layer and is optional.
+
+To build a specific target BSP configure the associated machine in `local.conf`:
+
+ MACHINE ?= "zc702-zynq7"
+
+Build the target file system image using `bitbake`:
+
+ $ bitbake core-image-minimal
+
+Once complete the images for the target machine will be available in the output
+directory `tmp/deploy/images/<machine name>/`.
+
+Additional Information
+----------------------
+
+For more complete details on setting up and using Yocto/OE refer to the Yocto
+Project Quick Start guide available at:
+ http://www.yoctoproject.org/docs/current/yocto-project-qs/yocto-project-qs.html
+
diff --git a/meta-xilinx/meta-xilinx-bsp/README.md b/meta-xilinx/meta-xilinx-bsp/README.md
new file mode 100644
index 0000000..13ef6b6
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/README.md
@@ -0,0 +1,87 @@
+meta-xilinx
+===========
+
+This layer provides support for MicroBlaze, Zynq and ZynqMP.
+
+Additional documentation:
+
+* [Building](README.building.md)
+* [Booting](README.booting.md)
+
+Supported Boards/Machines
+=========================
+
+Boards/Machines supported by this layer:
+
+* MicroBlaze:
+ * [Xilinx ML605 (QEMU)](conf/machine/ml605-qemu-microblazeel.conf) - `ml605-qemu-microblazeel` (QEMU support)
+ * [Xilinx S3A DSP 1800 (QEMU)](conf/machine/s3adsp1800-qemu-microblazeeb.conf) - `s3adsp1800-qemu-microblazeeb` (QEMU support)
+ * [Xilinx KC705](conf/machine/kc705-microblazeel.conf) - `kc705-microblazeel`
+* Zynq:
+ * [Zynq (QEMU)](conf/machine/qemu-zynq7.conf) - `qemu-zynq7` (QEMU Support)
+ * [Xilinx ZC702](conf/machine/zc702-zynq7.conf) - `zc702-zynq7` (with QEMU support)
+ * [Xilinx ZC706](conf/machine/zc706-zynq7.conf) - `zc706-zynq7` (with QEMU support)
+ * [Avnet MicroZed](conf/machine/microzed-zynq7.conf) - `microzed-zynq7`
+ * [Avnet PicoZed](conf/machine/picozed-zynq7.conf) - `picozed-zynq7`
+ * [Avnet/Digilent ZedBoard](conf/machine/zedboard-zynq7.conf) - `zedboard-zynq7`
+ * [Digilent Zybo](conf/machine/zybo-zynq7.conf) - `zybo-zynq7`
+ * [Digilent Zybo Linux BD](conf/machine/zybo-linux-bd-zynq7.conf) - `zybo-linux-bd-zynq7`
+* ZynqMP:
+ * [Xilinx ZCU102](conf/machine/zcu102-zynqmp.conf) - `zcu102-zynqmp` (QEMU support)
+ * [Xilinx ZCU106](conf/machine/zcu106-zynqmp.conf) - `zcu106-zynqmp`
+ * [Xilinx ZCU104](conf/machine/zcu104-zynqmp.conf) - `zcu104-zynqmp`
+
+Additional information on Xilinx architectures can be found at:
+ http://www.xilinx.com/support/index.htm
+
+For Zybo Linux BD reference design, please see meta-xilinx-contrib layer
+
+Maintainers, Mailing list, Patches
+==================================
+
+Please send any patches, pull requests, comments or questions for this layer to
+the [meta-xilinx mailing list](https://lists.yoctoproject.org/listinfo/meta-xilinx):
+
+ meta-xilinx@lists.yoctoproject.org
+
+Maintainers:
+
+ Manjukumar Harthikote Matha <manjukumar.harthikote-matha@xilinx.com>
+
+Dependencies
+============
+
+This layer depends on:
+
+ URI: git://git.openembedded.org/bitbake
+
+ URI: git://git.openembedded.org/openembedded-core
+ layers: meta
+
+Recipe Licenses
+===============
+
+Due to licensing restrictions some recipes in this layer rely on closed source
+or restricted content provided by Xilinx. In order to use these recipes you must
+accept or agree to the licensing terms (e.g. EULA, Export Compliance, NDA,
+Redistribution, etc). This layer **does not enforce** any legal requirement, it
+is the **responsibility of the user** the ensure that they are in compliance
+with any licenses or legal requirements for content used.
+
+In order to use recipes that rely on restricted content the `xilinx` license
+flag must be white-listed in the build configuration (e.g. `local.conf`). This
+can be done on a per package basis:
+
+ LICENSE_FLAGS_WHITELIST += "xilinx_pmu-rom"
+
+or generally:
+
+ LICENSE_FLAGS_WHITELIST += "xilinx"
+
+Generally speaking Xilinx content that is provided as a restricted download
+cannot be obtained without a Xilinx account, in order to use this content you
+must first download it with your Xilinx account and place the downloaded content
+in the `downloads/` directory of your build or on a `PREMIRROR`. Attempting to
+fetch the content using bitbake will fail, indicating the URL from which to
+acquire the content.
+
diff --git a/meta-xilinx/meta-xilinx-bsp/README.qemu.md b/meta-xilinx/meta-xilinx-bsp/README.qemu.md
new file mode 100644
index 0000000..992e061
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/README.qemu.md
@@ -0,0 +1,25 @@
+
+ZynqMP - PMU ROM
+----------------
+
+Since Xilinx tool release v2017.1 multiple components (arm-trusted-firmware,
+linux, u-boot, etc.) require the PMU firmware to be loaded. For QEMU this also
+means that the PMU ROM must be loaded so that the PMU firmware can be used.
+
+The PMU ROM is not available for download separately from a location that can be
+accessed without a Xilinx account. As such the PMU ROM must be obtained manually
+by the user. The PMU ROM is available in the ZCU102 PetaLinux BSP, but can be
+extracted without the need for the PetaLinux tools.
+
+Download the BSP (you will need a Xilinx account and agreement to terms):
+
+https://www.xilinx.com/member/forms/download/xef.html?filename=xilinx-zcu102-v2017.1-final.bsp&akdm=1
+
+Once downloaded the PMU ROM can be extracted using the following command and
+place `pmu-rom.elf` in the `deploy/images/zcu102-zynqmp/` directory.
+
+```
+# tar -O -xf xilinx-zcu102-v2017.1-final.bsp \
+ xilinx-zcu102-2017.1/pre-built/linux/images/pmu_rom_qemu_sha3.elf > pmu-rom.elf
+```
+
diff --git a/meta-xilinx/meta-xilinx-bsp/classes/image-types-xilinx-qemu.bbclass b/meta-xilinx/meta-xilinx-bsp/classes/image-types-xilinx-qemu.bbclass
new file mode 100644
index 0000000..59dfabf
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/classes/image-types-xilinx-qemu.bbclass
@@ -0,0 +1,10 @@
+# Define the 'qemu-sd' conversion type
+#
+# This conversion type pads any image to the 256K boundary to ensure that the
+# image file can be used directly with QEMU's SD emulation which requires the
+# block device to match that of valid SD card sizes (which are multiples of
+# 256K).
+
+CONVERSIONTYPES_append = " qemu-sd"
+CONVERSION_CMD_qemu-sd = "cp ${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.${type} ${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.${type}.qemu-sd; truncate -s %256K ${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.${type}.qemu-sd"
+CONVERSION_DEPENDS_qemu-sd = "coreutils-native"
diff --git a/meta-xilinx/meta-xilinx-bsp/classes/qemuboot-xilinx.bbclass b/meta-xilinx/meta-xilinx-bsp/classes/qemuboot-xilinx.bbclass
new file mode 100644
index 0000000..024626c
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/classes/qemuboot-xilinx.bbclass
@@ -0,0 +1,27 @@
+
+# enable the overrides for the context of the conf only
+OVERRIDES .= ":qemuboot-xilinx"
+
+# setup the target binary
+QB_SYSTEM_NAME_prepend = "qemu-xilinx/"
+
+# Default machine targets for Xilinx QEMU (FDT Generic)
+QB_MACHINE_aarch64 = "-machine arm-generic-fdt"
+QB_MACHINE_arm = "-machine arm-generic-fdt-7series"
+QB_MACHINE_microblaze = "-machine microblaze-generic-fdt-plnx"
+
+# defaults
+QB_DEFAULT_KERNEL ?= "none"
+
+inherit qemuboot
+
+# rewrite the qemuboot with the custom sysroot bindir
+python do_write_qemuboot_conf_append() {
+ val = os.path.join(d.getVar('BASE_WORKDIR'), d.getVar('BUILD_SYS'), 'qemu-xilinx-helper-native/1.0-r1/recipe-sysroot-native/usr/bin/')
+ cf.set('config_bsp', 'STAGING_BINDIR_NATIVE', '%s' % val)
+
+ # write out the updated version from this append
+ with open(qemuboot, 'w') as f:
+ cf.write(f)
+}
+
diff --git a/meta-xilinx/meta-xilinx-bsp/classes/xilinx-fetch-restricted.bbclass b/meta-xilinx/meta-xilinx-bsp/classes/xilinx-fetch-restricted.bbclass
new file mode 100644
index 0000000..a778ec7
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/classes/xilinx-fetch-restricted.bbclass
@@ -0,0 +1,35 @@
+# This class is setup to override the default fetching for the target recipe.
+# When fetching it forces PREMIRROR only fetching so that no attempts are made
+# to fetch the Xilinx downloads that are restricted to authenticated users only.
+#
+# The purpose of this class is to allow for automatation with pre-downloaded
+# content or content that is available with curated/user defined pre-mirrors
+# and or pre-populated downloads/ directories.
+
+python do_fetch() {
+ xilinx_restricted_url = "xilinx.com/member/forms/download"
+
+ src_uri = (d.getVar('SRC_URI') or "").split()
+ if len(src_uri) == 0:
+ return
+
+ for i in src_uri:
+ if xilinx_restricted_url in i:
+ # force the use of premirrors only, do not attempt download from xilinx.com
+ d.setVar("BB_FETCH_PREMIRRORONLY", "1")
+ break
+
+ try:
+ fetcher = bb.fetch2.Fetch(src_uri, d)
+ fetcher.download()
+ except bb.fetch2.NetworkAccess as e:
+ if xilinx_restricted_url in e.url:
+ # fatal on access to xilinx.com restricted downloads, print the url for manual download
+ bb.fatal("The following download cannot be fetched automatically. " \
+ "Please manually download the file and place it in the 'downloads' directory (or on an available PREMIRROR).\n" \
+ " %s" % (e.url.split(";")[0]))
+ else:
+ bb.fatal(str(e))
+ except bb.fetch2.BBFetchException as e:
+ bb.fatal(str(e))
+}
diff --git a/meta-xilinx/meta-xilinx-bsp/classes/xilinx-platform-init.bbclass b/meta-xilinx/meta-xilinx-bsp/classes/xilinx-platform-init.bbclass
new file mode 100644
index 0000000..5d09950
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/classes/xilinx-platform-init.bbclass
@@ -0,0 +1,14 @@
+# This class should be included by any recipe that wants to access or provide
+# the platform init source files which are used to initialize a Zynq or ZynqMP
+# SoC.
+
+# Define the path to the xilinx platform init code/headers
+PLATFORM_INIT_DIR ?= "/usr/src/xilinx-platform-init"
+
+PLATFORM_INIT_STAGE_DIR = "${STAGING_DIR_HOST}${PLATFORM_INIT_DIR}"
+
+# Target files use for platform init
+PLATFORM_INIT_FILES ?= ""
+PLATFORM_INIT_FILES_zynq = "ps7_init_gpl.c ps7_init_gpl.h"
+PLATFORM_INIT_FILES_zynqmp = "psu_init_gpl.c psu_init_gpl.h"
+
diff --git a/meta-xilinx/meta-xilinx-bsp/classes/zynqmp-pmu.bbclass b/meta-xilinx/meta-xilinx-bsp/classes/zynqmp-pmu.bbclass
new file mode 100644
index 0000000..714eb96
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/classes/zynqmp-pmu.bbclass
@@ -0,0 +1,122 @@
+#
+# This class handles configuring a recipe to build for the ZynqMP PMU
+# architecture. The reason for this class is due to limitations of multilib
+# with regards to multiple architectures (which do not work correctly).
+#
+# This class is specifically intended to extend the binutils-cross, gcc-cross,
+# newlib, libgloss and pmu-firmware recipes so that binaries can be emitted
+# which target the PMU architecture alongside building for the APU architecture
+# (ARM64). But the class can be applied globally via BBCLASSEXTEND in for
+# example a <machine>.conf.
+#
+# This class is almost the same as a multilib variant with custom TUNE_* setup
+# to allow for a switched TUNE_ARCH.
+#
+
+ORIG_TARGET_ARCH := "${TARGET_ARCH}"
+
+# zynqmp-pmu target arch (hardcoded based on pre-gen data from arch-microblaze.inc)
+DEFAULTTUNE = "microblaze"
+ABIEXTENSION = ""
+TUNE_ARCH = "microblazeel"
+#TUNE_FEATURES_tune-microblaze += "v9.2 barrel-shift pattern-compare"
+TUNE_CCARGS = "-mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mno-xl-reorder -mcpu=v9.2 -mxl-soft-mul -mxl-soft-div"
+TUNE_LDARGS = ""
+TUNE_ASARGS = ""
+TUNE_PKGARCH = "microblazeel-v9.2-bs-cmp"
+TARGET_OS = "elf"
+TARGET_FPU = "fpu-soft"
+
+# rebuild the MACHINE overrides
+MACHINEOVERRIDES = "${MACHINE}${@':${SOC_FAMILY}' if d.getVar('SOC_FAMILY') else ''}:microblaze"
+
+# override tune provided archs
+PACKAGE_EXTRA_ARCHS = "${TUNE_PKGARCH}"
+
+# baremetal equivalent config (note the tclibc is not included, this is purely
+# for recipes/etc that check for the value)
+TCLIBC = "baremetal"
+LIBCEXTENSION = ""
+LIBCOVERRIDE = ":libc-baremetal"
+USE_NLS = "no"
+IMAGE_LINGUAS = ""
+LIBC_DEPENDENCIES = ""
+
+# gcc-cross specific baremetal setup (due to the override order this is important)
+EXTRA_OECONF_pn-${MLPREFIX}gcc-cross-${TARGET_ARCH}_append = " --without-headers"
+
+EXTRA_OECONF_GCC_FLOAT = ""
+
+# Setup a multiarch like prefix.
+prefix = "/usr/${TARGET_SYS}"
+# Make sure GCC can search in the prefix dir (for libgcc)
+TOOLCHAIN_OPTIONS += "-B${RECIPE_SYSROOT}${includedir}/ -B${RECIPE_SYSROOT}${libdir}/"
+TOOLCHAIN_OPTIONS += "-I =${includedir} -L =${libdir}"
+
+python multitarget_zynqmp_pmu_virtclass_handler () {
+ variant = "zynqmp-pmu"
+ pn = d.getVar("PN")
+ if not (pn.startswith(variant + "-") or pn.endswith("-" + variant)):
+ return
+
+ if bb.data.inherits_class('native', e.data) or bb.data.inherits_class('nativesdk', e.data) or bb.data.inherits_class('crosssdk', e.data):
+ raise bb.parse.SkipPackage("Can't extend native/nativesdk/crosssdk recipes")
+
+ initialpn = e.data.getVar("PN").replace("-" + variant, "").replace(variant + "-", "")
+ e.data.setVar("MLPREFIX", variant + "-")
+ e.data.setVar("OVERRIDES", e.data.getVar("OVERRIDES", False) + ":virtclass-" + variant)
+
+ # hide multilib variants, this class is not one but this works around recipes thinking it is (due to MLPREFIX).
+ e.data.setVar("MULTILIB_VARIANTS", "")
+
+ # work around for -cross recipes that embed the TARGET_ARCH value
+ if bb.data.inherits_class('cross', e.data):
+ if initialpn.endswith("-" + d.getVar("ORIG_TARGET_ARCH")):
+ initialpn = initialpn.replace("-" + d.getVar("ORIG_TARGET_ARCH"), "-" + d.getVar("TARGET_ARCH"))
+
+ e.data.setVar("PN", variant + "-" + initialpn)
+}
+
+addhandler multitarget_zynqmp_pmu_virtclass_handler
+multitarget_zynqmp_pmu_virtclass_handler[eventmask] = "bb.event.RecipePreFinalise"
+
+python () {
+ variant = "zynqmp-pmu"
+ pn = d.getVar("PN")
+ if not pn.startswith(variant + "-"):
+ return
+
+ if pn.endswith("gcc-cross-" + d.getVar("TARGET_ARCH")):
+ # work around, DEPENDS _remove being immediate in gcc-cross
+ d.setVar("DEPENDS_remove", "virtual/%slibc-for-gcc" % d.getVar("TARGET_PREFIX"))
+
+ if pn.endswith("libgcc"):
+ # work around, strip depends on libc via do_package* tasks (this class cannot set ASSUME_PROVIDED += libc)
+ for i in ["do_package", "do_package_write_ipk", "do_package_write_deb", "do_package_write_rpm"]:
+ sanitized = " ".join([dep for dep in d.getVarFlag(i, "depends").split() if not dep.startswith("virtual/%s-libc" % variant)])
+ d.setVarFlag(i, "depends", sanitized)
+
+ import oe.classextend
+
+ clsextend = oe.classextend.ClassExtender(variant, d)
+
+ clsextend.map_depends_variable("DEPENDS")
+ clsextend.map_variable("PROVIDES")
+
+ clsextend.rename_packages()
+ clsextend.rename_package_variables((d.getVar("PACKAGEVARS") or "").split())
+
+ clsextend.map_packagevars()
+ clsextend.map_regexp_variable("PACKAGES_DYNAMIC")
+ clsextend.map_variable("PACKAGE_INSTALL")
+}
+
+# microblaze elf insane definitions not currently in insane.bbclass
+PACKAGEQA_EXTRA_MACHDEFFUNCS += "package_qa_get_machine_dict_microblazeelf"
+def package_qa_get_machine_dict_microblazeelf(machdata, d):
+ machdata["elf"] = {
+ "microblaze": (189, 0, 0, False, 32),
+ "microblazeeb":(189, 0, 0, False, 32),
+ "microblazeel":(189, 0, 0, True, 32),
+ }
+ return machdata
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/layer.conf b/meta-xilinx/meta-xilinx-bsp/conf/layer.conf
new file mode 100644
index 0000000..55f6680
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/layer.conf
@@ -0,0 +1,15 @@
+# We have a conf and classes directory, add to BBPATH
+BBPATH .= ":${LAYERDIR}"
+
+# We have a packages directory, add to BBFILES
+BBFILES += "${LAYERDIR}/recipes-*/*/*.bb"
+BBFILES += "${LAYERDIR}/recipes-*/*/*.bbappend"
+
+BBFILE_COLLECTIONS += "xilinx"
+BBFILE_PATTERN_xilinx = "^${LAYERDIR}/"
+BBFILE_PRIORITY_xilinx = "5"
+
+LAYERDEPENDS_xilinx = "core"
+
+LAYERSERIES_COMPAT_xilinx = "sumo"
+
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-board.inc b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-board.inc
new file mode 100644
index 0000000..ba9a36b
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-board.inc
@@ -0,0 +1,6 @@
+# Default Xilinx Board settings
+
+EXTRA_IMAGEDEPENDS += "virtual/bootloader"
+
+IMAGE_BOOT_FILES ?= "${KERNEL_IMAGETYPE} ${UBOOT_BINARY}"
+
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-default.inc b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-default.inc
new file mode 100644
index 0000000..77fbec8
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-default.inc
@@ -0,0 +1,42 @@
+# Default Xilinx BSP Machine settings
+
+MACHINE_FEATURES_BACKFILL_CONSIDERED += "rtc"
+
+# File System Configuration
+IMAGE_FSTYPES ?= "tar.gz cpio cpio.gz.u-boot"
+
+# Kernel Configuration
+XILINX_DEFAULT_KERNEL := "linux-xlnx"
+XILINX_DEFAULT_KERNEL_microblaze := "linux-yocto"
+XILINX_DEFAULT_KERNEL_zynqmp := "linux-yocto"
+PREFERRED_PROVIDER_virtual/kernel ??= "${XILINX_DEFAULT_KERNEL}"
+
+# U-Boot Configuration
+XILINX_DEFAULT_UBOOT := "u-boot-xlnx"
+XILINX_DEFAULT_UBOOT_zynqmp := "u-boot"
+PREFERRED_PROVIDER_virtual/bootloader ??= "${XILINX_DEFAULT_UBOOT}"
+PREFERRED_PROVIDER_virtual/boot-bin ??= "${PREFERRED_PROVIDER_virtual/bootloader}"
+
+UBOOT_SUFFIX ?= "img"
+UBOOT_SUFFIX_zynqmp ?= "bin"
+UBOOT_SUFFIX_microblaze ?= "bin"
+
+UBOOT_BINARY ?= "u-boot.${UBOOT_SUFFIX}"
+UBOOT_ELF ?= "u-boot"
+UBOOT_ELF_aarch64 ?= "u-boot.elf"
+
+XSERVER ?= " \
+ xserver-xorg \
+ xf86-input-evdev \
+ xf86-input-mouse \
+ xf86-input-keyboard \
+ xf86-video-fbdev \
+ ${XSERVER_EXT} \
+ "
+
+XSERVER_EXT ?= ""
+XSERVER_EXT_zynqmp ?= "xf86-video-armsoc"
+
+# For MicroBlaze default all microblaze machines to use GDB 7.7.1 (for gdbserver/gdb)
+PREFERRED_VERSION_gdb_microblaze = "7.7.1"
+
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-overrides.inc b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-overrides.inc
new file mode 100644
index 0000000..30049bc
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-overrides.inc
@@ -0,0 +1,21 @@
+SOC_VARIANT ??= ""
+MACHINEOVERRIDES =. "${@['', '${SOC_FAMILY}${SOC_VARIANT}:']['${SOC_VARIANT}' != '']}"
+
+# Here we can extend overrides for the corresponding family and variant
+def get_soc_overrides(fam, var, d):
+ extender = ''
+ if (fam == 'zynqmp'):
+ if (var == 'eg'):
+ extender = 'mali400:'
+ elif (var == 'ev'):
+ extender = 'mali400:vcu:'
+ return extender
+
+# Gets OVERRIDES extender depending on the board
+SOC_OVERRIDES = "${@get_soc_overrides(d.getVar('SOC_FAMILY'),d.getVar('SOC_VARIANT'), d)}"
+
+MACHINEOVERRIDES =. "${SOC_OVERRIDES}"
+
+PACKAGE_EXTRA_ARCHS_append = " ${SOC_FAMILY}"
+PACKAGE_EXTRA_ARCHS_append = "${@['', ' ${SOC_FAMILY}${SOC_VARIANT}']['${SOC_VARIANT}' != '']}"
+
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-qemu.inc b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-qemu.inc
new file mode 100644
index 0000000..dd275f3
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-qemu.inc
@@ -0,0 +1,49 @@
+# This include is used to setup default QEMU and qemuboot config for meta-xilinx
+# machines.
+
+# depend on qemu-helper-native, which will depend on QEMU
+EXTRA_IMAGEDEPENDS += "qemu-helper-native"
+
+def qemu_default_dtb(d):
+ if d.getVar("IMAGE_BOOT_FILES", True):
+ dtbs = d.getVar("IMAGE_BOOT_FILES", True).split(" ")
+ # IMAGE_BOOT_FILES has extra renaming info in the format '<source>;<target>'
+ dtbs = [f.split(";")[0] for f in dtbs]
+ dtbs = [f for f in dtbs if f.endswith(".dtb")]
+ if len(dtbs) != 0:
+ return dtbs[0]
+ if d.getVar("KERNEL_DEVICETREE", True):
+ dtbs = d.getVar("KERNEL_DEVICETREE", True).split(" ")
+ dtbs = [os.path.basename(d) for d in dtbs]
+ if len(dtbs) != 0:
+ return d.getVar("KERNEL_IMAGETYPE", True) + "-" + dtbs[0]
+ return ""
+
+def qemu_default_serial(d):
+ if d.getVar("SERIAL_CONSOLE", True):
+ speed, console = d.getVar("SERIAL_CONSOLE", True).split(" ", 1)
+ # zynqmp uses earlycon and stdout (in dtb)
+ if "zynqmp" in d.getVar("MACHINEOVERRIDES", True).split(":"):
+ return ""
+ return "console=%s,%s earlyprintk" % (console, speed)
+ return ""
+
+def qemu_target_binary(d):
+ ta = d.getVar("TARGET_ARCH", True)
+ if ta == "microblazeeb":
+ ta = "microblaze"
+ elif ta == "arm":
+ ta = "aarch64"
+ return "qemu-system-%s" % ta
+
+def qemu_zynqmp_unhalt(d, multiarch):
+ if multiarch:
+ return "-global xlnx,zynqmp-boot.cpu-num=0 -global xlnx,zynqmp-boot.use-pmufw=true"
+ return "-device loader,addr=0xfd1a0104,data=0x8000000e,data-len=4 -device loader,addr=0xfd1a0104,data=0x8000000e,data-len=4"
+
+# For qemuboot, default setup across all machines in meta-xilinx
+QB_SYSTEM_NAME ?= "${@qemu_target_binary(d)}"
+QB_DEFAULT_FSTYPE ?= "cpio"
+QB_DTB ?= "${@qemu_default_dtb(d)}"
+QB_KERNEL_CMDLINE_APPEND ?= "${@qemu_default_serial(d)}"
+
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/tune-zynq.inc b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/tune-zynq.inc
new file mode 100644
index 0000000..270e2d9
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/tune-zynq.inc
@@ -0,0 +1,18 @@
+DEFAULTTUNE ?= "cortexa9thf-neon"
+SOC_FAMILY ?= "zynq"
+
+# Available SOC_VARIANT's for zynq:
+# 7zs - Zynq-7000 Single A9 Core
+# 7z - Zynq-7000 Dual A9 Core
+
+SOC_VARIANT ?= "7z"
+
+require conf/machine/include/tune-cortexa9.inc
+require conf/machine/include/soc-family.inc
+
+# Linux Configuration
+KERNEL_IMAGETYPE ?= "uImage"
+
+# Set default load address.
+# Override with KERNEL_EXTRA_ARGS_<board> += "..." in machine file if required
+KERNEL_EXTRA_ARGS_zynq += "UIMAGE_LOADADDR=0x8000"
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/tune-zynqmp.inc b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/tune-zynqmp.inc
new file mode 100644
index 0000000..225fa65
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/tune-zynqmp.inc
@@ -0,0 +1,18 @@
+DEFAULTTUNE ?= "aarch64"
+SOC_FAMILY ?= "zynqmp"
+
+# Available SOC_VARIANT's for zynqmp:
+# "cg" - Zynq UltraScale+ CG Devices
+# "eg" - Zynq UltraScale+ EG Devices
+# "ev" - Zynq UltraScale+ EV Devices
+
+SOC_VARIANT ?= "eg"
+
+require conf/machine/include/arm/arch-armv8.inc
+require conf/machine/include/soc-family.inc
+
+# Linux Configuration
+KERNEL_IMAGETYPE ?= "Image"
+
+# Support multilib on zynqmp
+DEFAULTTUNE_virtclass-multilib-lib32 ?= "armv7vethf-neon-vfpv4"
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/zynqmp-pmu-config.inc b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/zynqmp-pmu-config.inc
new file mode 100644
index 0000000..fd9e980
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/zynqmp-pmu-config.inc
@@ -0,0 +1,20 @@
+
+# Enable the use of zynqmp-pmu for specific recipes only
+def zynqmp_pmu_enable_for_bpns(d):
+ bpn = d.getVar("BPN")
+ crossbpns = ["binutils", "gcc"]
+ targetbpns = ["libgcc", "newlib", "libgloss"]
+ if bpn in targetbpns:
+ return True
+ if bpn in crossbpns and bb.data.inherits_class('cross', d):
+ return True
+ return False
+
+BBCLASSEXTEND_append = "${@' zynqmp-pmu' if zynqmp_pmu_enable_for_bpns(d) else ''}"
+
+# Add the pkgarch to the extra list, this is done to avoid warnings about
+# missing manifests due to implicit dependency chains on populate_sysroot when
+# a recipe/task depends on a IMAGE_EXTRADEPENDS/do_deploy task which is
+# provided by a zynqmp-pmu-* target.
+PACKAGE_EXTRA_ARCHS_append = " microblazeel-v9.2-bs-cmp"
+
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/kc705-microblazeel.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/kc705-microblazeel.conf
new file mode 100644
index 0000000..b777c24
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/kc705-microblazeel.conf
@@ -0,0 +1,25 @@
+#@TYPE: Machine
+#@NAME: kc705-microblazeel
+#@DESCRIPTION: Machine support for Xilinx KC705 Embedded Kit.
+#
+
+require conf/machine/include/tune-microblaze.inc
+require conf/machine/include/machine-xilinx-default.inc
+require conf/machine/include/machine-xilinx-board.inc
+
+TUNE_FEATURES_tune-microblaze += "v10.0 barrel-shift reorder pattern-compare multiply-high divide-hard"
+
+MACHINE_FEATURES = ""
+
+USE_VT = ""
+SERIAL_CONSOLE = "115200 ttyS0"
+
+KERNEL_IMAGETYPE ?= "linux.bin.ub"
+
+MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree"
+PREFERRED_PROVIDER_virtual/kernel ?= "linux-xlnx"
+PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot-xlnx"
+
+EXTRA_IMAGEDEPENDS += "virtual/bitstream"
+
+UBOOT_MACHINE ?= "microblaze-generic_config"
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/microzed-zynq7.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/microzed-zynq7.conf
new file mode 100644
index 0000000..9cc97ec
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/microzed-zynq7.conf
@@ -0,0 +1,33 @@
+#@TYPE: Machine
+#@NAME: microzed-zynq7
+#@DESCRIPTION: Machine support for microZed. (http://www.microzed.org/)
+
+SOC_VARIANT ?= "7z"
+
+require conf/machine/include/tune-zynq.inc
+require conf/machine/include/machine-xilinx-overrides.inc
+require conf/machine/include/machine-xilinx-default.inc
+require conf/machine/include/machine-xilinx-board.inc
+
+MACHINE_FEATURES = "ext2 vfat usbhost"
+
+# u-boot configuration
+PREFERRED_PROVIDER_virtual/bootloader = "u-boot"
+UBOOT_MACHINE = "zynq_microzed_config"
+SPL_BINARY = "spl/boot.bin"
+
+EXTRA_IMAGEDEPENDS += " \
+ u-boot-zynq-uenv \
+ virtual/boot-bin \
+ "
+
+SERIAL_CONSOLE = "115200 ttyPS0"
+
+MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree"
+
+IMAGE_BOOT_FILES += " \
+ boot.bin \
+ ${MACHINE}.dtb \
+ uEnv.txt \
+ "
+
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/ml605-qemu-microblazeel.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/ml605-qemu-microblazeel.conf
new file mode 100644
index 0000000..f4ddb6d
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/ml605-qemu-microblazeel.conf
@@ -0,0 +1,27 @@
+#@TYPE: Machine
+#@NAME: ml605-qemu-microblazeel
+#@DESCRIPTION: MicroBlaze QEMU machine support ('petalogix-ml605' model)
+
+require conf/machine/include/tune-microblaze.inc
+require conf/machine/include/machine-xilinx-default.inc
+require conf/machine/include/machine-xilinx-qemu.inc
+
+TUNE_FEATURES_tune-microblaze += "v8.50 barrel-shift reorder pattern-compare divide-hard multiply-high fpu-hard"
+
+MACHINE_FEATURES = ""
+
+USE_VT = ""
+SERIAL_CONSOLE = "115200 ttyS0"
+
+KERNEL_IMAGETYPE ?= "linux.bin.ub"
+
+# Use the networking setup from qemuarm
+FILESOVERRIDES_append_pn-init-ifupdown = ":qemuarm"
+
+# This machine is a targeting a QEMU model, runqemu setup:
+IMAGE_CLASSES += "qemuboot"
+QB_MEM = "-m 256"
+QB_MACHINE = "-machine petalogix-ml605"
+QB_OPT_APPEND = "-nographic -serial mon:stdio"
+QB_NETWORK_DEVICE = "-net nic,netdev=net0,macaddr=@MAC@"
+
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/picozed-zynq7.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/picozed-zynq7.conf
new file mode 100644
index 0000000..8762832
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/picozed-zynq7.conf
@@ -0,0 +1,37 @@
+#@TYPE: Machine
+#@NAME: picozed-zynq7
+#@DESCRIPTION: Machine support for picoZed. (http://www.picozed.org/)
+#
+# Note: This machine configuration is intended as a generic config for
+# the picozed SOM. It also covers the multiple SKUs for the picoZed
+# including 7010, 7020, 7015 and 7030.
+
+SOC_VARIANT ?= "7z"
+
+require conf/machine/include/tune-zynq.inc
+require conf/machine/include/machine-xilinx-overrides.inc
+require conf/machine/include/machine-xilinx-default.inc
+require conf/machine/include/machine-xilinx-board.inc
+
+MACHINE_FEATURES = "ext2 vfat usbhost usbgadget"
+
+# u-boot configuration
+PREFERRED_PROVIDER_virtual/bootloader = "u-boot"
+UBOOT_MACHINE = "zynq_picozed_config"
+SPL_BINARY = "spl/boot.bin"
+
+EXTRA_IMAGEDEPENDS += " \
+ u-boot-zynq-uenv \
+ virtual/boot-bin \
+ "
+
+SERIAL_CONSOLE = "115200 ttyPS0"
+
+MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree"
+
+IMAGE_BOOT_FILES += " \
+ boot.bin \
+ ${MACHINE}.dtb \
+ uEnv.txt \
+ "
+
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/qemu-zynq7.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/qemu-zynq7.conf
new file mode 100644
index 0000000..2c86edb
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/qemu-zynq7.conf
@@ -0,0 +1,28 @@
+#@TYPE: Machine
+#@NAME: qemu-zynq7
+#@DESCRIPTION: Zynq QEMU machine support ('xilinx-zynq-a9' model)
+
+SOC_VARIANT ?= "7z"
+
+require conf/machine/include/tune-zynq.inc
+require conf/machine/include/machine-xilinx-overrides.inc
+require conf/machine/include/machine-xilinx-default.inc
+require conf/machine/include/machine-xilinx-qemu.inc
+
+MACHINE_FEATURES = "ext2 vfat"
+
+SERIAL_CONSOLE = "115200 ttyPS0"
+
+MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree"
+IMAGE_BOOT_FILES += "${MACHINE}.dtb"
+
+# Use the networking setup from qemuarm
+FILESOVERRIDES_append_pn-init-ifupdown = ":qemuarm"
+
+# This machine is a targeting a QEMU model, runqemu setup:
+IMAGE_CLASSES += "qemuboot"
+QB_MEM = "-m 1024"
+QB_MACHINE = "-machine xilinx-zynq-a9"
+QB_OPT_APPEND = "-nographic -serial null -serial mon:stdio"
+QB_NETWORK_DEVICE = "-net nic,netdev=net0,macaddr=@MAC@"
+
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/s3adsp1800-qemu-microblazeeb.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/s3adsp1800-qemu-microblazeeb.conf
new file mode 100644
index 0000000..3a21eb7
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/s3adsp1800-qemu-microblazeeb.conf
@@ -0,0 +1,24 @@
+#@TYPE: Machine
+#@NAME: s3adsp1800-qemu-microblazeeb
+#@DESCRIPTION: MicroBlaze QEMU machine support ('petalogix-s3adsp1800' model)
+
+require conf/machine/include/tune-microblaze.inc
+require conf/machine/include/machine-xilinx-default.inc
+require conf/machine/include/machine-xilinx-qemu.inc
+
+TUNE_FEATURES_tune-microblaze += "v8.00 bigendian barrel-shift pattern-compare multiply-low"
+
+MACHINE_FEATURES = ""
+
+USE_VT = ""
+SERIAL_CONSOLE = "115200 ttyUL0"
+
+KERNEL_IMAGETYPE ?= "linux.bin.ub"
+
+# This machine is a targeting a QEMU model, runqemu setup:
+IMAGE_CLASSES += "qemuboot"
+QB_MEM = "-m 256"
+QB_MACHINE = "-machine petalogix-s3adsp1800"
+QB_OPT_APPEND = "-nographic -serial mon:stdio"
+QB_NETWORK_DEVICE = "-net nic,netdev=net0,macaddr=@MAC@"
+
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zc702-zynq7.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zc702-zynq7.conf
new file mode 100644
index 0000000..9b08d1b
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/zc702-zynq7.conf
@@ -0,0 +1,47 @@
+#@TYPE: Machine
+#@NAME: zc702-zynq7
+#@DESCRIPTION: Machine support for ZC702 Evaluation Board.
+#
+# For details on the Evaluation board:
+# http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm
+# For documentation and design files for the ZC702:
+# http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/boards_and_kits/zynq-7000_soc_boards_and_kits/zynq-7000_soc_zc702_evaluation_kit.html
+# For the FSBL 'zynq_fsbl_0.elf' refer to UG873 and the associated design files.
+#
+SOC_VARIANT ?= "7z"
+
+require conf/machine/include/tune-zynq.inc
+require conf/machine/include/machine-xilinx-overrides.inc
+require conf/machine/include/machine-xilinx-default.inc
+require conf/machine/include/machine-xilinx-board.inc
+require conf/machine/include/machine-xilinx-qemu.inc
+
+MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost"
+
+# u-boot configuration
+UBOOT_MACHINE = "zynq_zc702_config"
+SPL_BINARY = "spl/boot.bin"
+
+EXTRA_IMAGEDEPENDS += " \
+ u-boot-zynq-uenv \
+ virtual/boot-bin \
+ "
+
+SERIAL_CONSOLE = "115200 ttyPS0"
+
+KERNEL_DEVICETREE = "zynq-zc702.dtb"
+
+IMAGE_BOOT_FILES += "boot.bin uEnv.txt ${KERNEL_IMAGETYPE}-zynq-zc702.dtb"
+
+# Although not fully supported you can run this machine on the mainline QEMU 'xilinx-zynq-a9' machine
+IMAGE_CLASSES += "qemuboot"
+QB_MEM = "-m 1024"
+QB_MACHINE = "-machine xilinx-zynq-a9"
+QB_OPT_APPEND = "-nographic -serial null -serial mon:stdio"
+QB_NETWORK_DEVICE = "-net nic,netdev=net0,macaddr=@MAC@"
+
+# Xilinx's fork of QEMU has much better results, so let's default to that
+# Use qemu-xilinx instead of mainline
+PREFERRED_PROVIDER_qemu-helper-native = "qemu-xilinx-helper-native"
+
+IMAGE_CLASSES += "qemuboot-xilinx"
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zc706-zynq7.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zc706-zynq7.conf
new file mode 100644
index 0000000..628d404
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/zc706-zynq7.conf
@@ -0,0 +1,52 @@
+#@TYPE: Machine
+#@NAME: zc706-zynq7
+#@DESCRIPTION: Machine support for ZC706 Evaluation Board.
+#
+# For details on the Evaluation board:
+# http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm
+# For documentation and design files for the ZC702:
+# http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/boards_and_kits/zynq-7000_soc_boards_and_kits/zynq-7000_soc_zc706_evaluation_kit.html
+# For the FSBL 'zynq_fsbl_0.elf' refer to UG873 and the associated design files.
+#
+
+SOC_VARIANT ?= "7z"
+
+require conf/machine/include/tune-zynq.inc
+require conf/machine/include/machine-xilinx-overrides.inc
+require conf/machine/include/machine-xilinx-default.inc
+require conf/machine/include/machine-xilinx-board.inc
+require conf/machine/include/machine-xilinx-qemu.inc
+
+MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost usbgadget"
+
+# u-boot configuration
+UBOOT_MACHINE = "zynq_zc706_config"
+SPL_BINARY = "spl/boot.bin"
+
+EXTRA_IMAGEDEPENDS += " \
+ u-boot-zynq-uenv \
+ virtual/boot-bin \
+ "
+
+SERIAL_CONSOLE = "115200 ttyPS0"
+
+KERNEL_DEVICETREE = "zynq-zc706.dtb"
+
+IMAGE_BOOT_FILES += " \
+ boot.bin \
+ ${KERNEL_IMAGETYPE}-zynq-zc706.dtb \
+ uEnv.txt \
+ "
+
+# Although not fully supported you can run this machine on the mainline QEMU 'xilinx-zynq-a9' machine
+IMAGE_CLASSES += "qemuboot"
+QB_MEM = "-m 1024"
+QB_MACHINE = "-machine xilinx-zynq-a9"
+QB_OPT_APPEND = "-nographic -serial null -serial mon:stdio"
+QB_NETWORK_DEVICE = "-net nic,netdev=net0,macaddr=@MAC@"
+
+# Xilinx's fork of QEMU has much better results, so let's default to that
+# Use qemu-xilinx instead of mainline
+PREFERRED_PROVIDER_qemu-helper-native = "qemu-xilinx-helper-native"
+
+IMAGE_CLASSES += "qemuboot-xilinx"
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu102-zynqmp.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu102-zynqmp.conf
new file mode 100644
index 0000000..d7f19ca
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu102-zynqmp.conf
@@ -0,0 +1,81 @@
+#@TYPE: Machine
+#@NAME: zcu102-zynqmp
+#@DESCRIPTION: Machine support for ZCU102 Evaluation Board.
+
+SOC_VARIANT ?= "eg"
+
+require conf/machine/include/tune-zynqmp.inc
+require conf/machine/include/machine-xilinx-overrides.inc
+require conf/machine/include/machine-xilinx-default.inc
+require conf/machine/include/machine-xilinx-board.inc
+require conf/machine/include/machine-xilinx-qemu.inc
+include conf/machine/include/zynqmp-pmu-config.inc
+
+MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost"
+
+UBOOT_MACHINE = "xilinx_zynqmp_zcu102_rev1_0_defconfig"
+SPL_BINARY = "spl/boot.bin"
+
+# Default SD image build onfiguration, use qemu-sd to pad
+IMAGE_CLASSES += "image-types-xilinx-qemu"
+IMAGE_FSTYPES += "wic.qemu-sd"
+WKS_FILES ?= "sdimage-bootpart.wks"
+
+SERIAL_CONSOLE = "115200 ttyPS0"
+SERIAL_CONSOLES_CHECK = "${SERIAL_CONSOLES}"
+
+KERNEL_DEVICETREE = "xilinx/zynqmp-zcu102-rev1.0.dtb"
+
+PREFERRED_PROVIDER_virtual/kernel ?= "linux-xlnx"
+PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot-xlnx"
+PREFERRED_PROVIDER_virtual/pmu-firmware ?= "zynqmp-pmu-pmu-firmware"
+
+EXTRA_IMAGEDEPENDS += " \
+ u-boot-zynq-uenv \
+ arm-trusted-firmware \
+ qemu-devicetrees \
+ virtual/pmu-firmware \
+ virtual/boot-bin \
+ "
+
+IMAGE_BOOT_FILES += "uEnv.txt atf-uboot.ub ${KERNEL_IMAGETYPE}-zynqmp-zcu102-rev1.0.dtb"
+
+# This machine has a QEMU model, runqemu setup:
+IMAGE_CLASSES += "qemuboot-xilinx"
+QB_MACHINE = "-machine xlnx-zcu102"
+QB_MEM = "-m 4096"
+QB_OPT_APPEND = "-nographic -serial mon:stdio -serial null"
+QB_NETWORK_DEVICE = "-net nic -net nic -net nic -net nic,netdev=net0,macaddr=@MAC@"
+
+# Use qemu-xilinx instead of mainline
+PREFERRED_PROVIDER_qemu-helper-native = "qemu-xilinx-helper-native"
+
+# Use the multiarch script instead of launching QEMU directly
+QB_SYSTEM_NAME_append = "-multiarch"
+
+# Replicate BootROM like behaviour, having loaded SPL and PMU(ROM+FW)
+QB_OPT_APPEND_append_qemuboot-xilinx = " \
+ -hw-dtb ${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch/zcu102-arm.dtb \
+ ${@qemu_zynqmp_unhalt(d, True)} \
+ -device loader,file=${DEPLOY_DIR_IMAGE}/arm-trusted-firmware.elf,cpu-num=0 \
+ -device loader,file=${DEPLOY_DIR_IMAGE}/u-boot.elf \
+ "
+
+# Attach the rootfs disk image to the second SD interface of QEMU (which is SD0)
+QB_DEFAULT_FSTYPE_qemuboot-xilinx = "wic.qemu-sd"
+QB_OPT_APPEND_append_qemuboot-xilinx = " -boot mode=3"
+QB_ROOTFS_OPT_qemuboot-xilinx = " -drive if=sd,index=1,file=@ROOTFS@,format=raw"
+
+# PMU instance args
+PMU_ROM ?= "${DEPLOY_DIR_IMAGE}/pmu-rom.elf"
+QB_PMU_OPT = " \
+ -M microblaze-fdt \
+ -display none \
+ -hw-dtb ${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch/zynqmp-pmu.dtb \
+ -kernel ${PMU_ROM} \
+ -device loader,file=${DEPLOY_DIR_IMAGE}/pmu-firmware-${MACHINE}.elf \
+ -device loader,addr=0xfd1a0074,data=0x1011003,data-len=4 \
+ -device loader,addr=0xfd1a007C,data=0x1010f03,data-len=4 \
+ "
+QB_OPT_APPEND_append_qemuboot-xilinx = " -pmu-args '${QB_PMU_OPT}'"
+
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu104-zynqmp.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu104-zynqmp.conf
new file mode 100644
index 0000000..f5a2af9
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu104-zynqmp.conf
@@ -0,0 +1,38 @@
+#@TYPE: Machine
+#@NAME: zcu104-zynqmp
+#@DESCRIPTION: Machine support for ZCU104 Evaluation Board.
+#
+
+SOC_VARIANT ?= "ev"
+
+require conf/machine/include/tune-zynqmp.inc
+require conf/machine/include/machine-xilinx-overrides.inc
+require conf/machine/include/machine-xilinx-default.inc
+require conf/machine/include/machine-xilinx-board.inc
+include conf/machine/include/zynqmp-pmu-config.inc
+
+MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost"
+
+UBOOT_MACHINE = "xilinx_zynqmp_zcu104_revC_defconfig"
+SPL_BINARY = "spl/boot.bin"
+
+SERIAL_CONSOLE ?= "115200 ttyPS0"
+
+SERIAL_CONSOLES_CHECK = "${SERIAL_CONSOLES}"
+
+KERNEL_DEVICETREE = "xilinx/zynqmp-zcu104-revC.dtb"
+
+PREFERRED_PROVIDER_virtual/kernel ?= "linux-xlnx"
+PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot-xlnx"
+PREFERRED_PROVIDER_virtual/pmu-firmware ?= "zynqmp-pmu-pmu-firmware"
+
+EXTRA_IMAGEDEPENDS += " \
+ u-boot-zynq-uenv \
+ arm-trusted-firmware \
+ virtual/pmu-firmware \
+ virtual/boot-bin \
+ "
+IMAGE_BOOT_FILES += "uEnv.txt atf-uboot.ub ${KERNEL_IMAGETYPE}-zynqmp-zcu104-revC.dtb"
+
+MACHINE_HWCODECS = "libomxil-xlnx"
+
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu106-zynqmp.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu106-zynqmp.conf
new file mode 100644
index 0000000..628ec6c
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu106-zynqmp.conf
@@ -0,0 +1,36 @@
+#@TYPE: Machine
+#@NAME: zcu106-zynqmp
+#@DESCRIPTION: Machine support for ZCU106 Evaluation Board.
+
+SOC_VARIANT ?= "ev"
+
+require conf/machine/include/tune-zynqmp.inc
+require conf/machine/include/machine-xilinx-overrides.inc
+require conf/machine/include/machine-xilinx-default.inc
+require conf/machine/include/machine-xilinx-board.inc
+include conf/machine/include/zynqmp-pmu-config.inc
+
+MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost"
+
+UBOOT_MACHINE = "xilinx_zynqmp_zcu106_revA_defconfig"
+SPL_BINARY = "spl/boot.bin"
+
+SERIAL_CONSOLE = "115200 ttyPS0"
+SERIAL_CONSOLES_CHECK = "${SERIAL_CONSOLES}"
+
+KERNEL_DEVICETREE = "xilinx/zynqmp-zcu106-revA.dtb"
+
+PREFERRED_PROVIDER_virtual/kernel ?= "linux-xlnx"
+PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot-xlnx"
+PREFERRED_PROVIDER_virtual/pmu-firmware ?= "zynqmp-pmu-pmu-firmware"
+
+EXTRA_IMAGEDEPENDS += " \
+ u-boot-zynq-uenv \
+ arm-trusted-firmware \
+ virtual/pmu-firmware \
+ virtual/boot-bin \
+ "
+
+IMAGE_BOOT_FILES += "uEnv.txt atf-uboot.ub ${KERNEL_IMAGETYPE}-zynqmp-zcu106-revA.dtb"
+
+MACHINE_HWCODECS = "libomxil-xlnx"
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zedboard-zynq7.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zedboard-zynq7.conf
new file mode 100644
index 0000000..a329074
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/zedboard-zynq7.conf
@@ -0,0 +1,32 @@
+#@TYPE: Machine
+#@NAME: zedboard-zynq7
+#@DESCRIPTION: Machine support for ZedBoard. (http://www.zedboard.org/)
+#
+# For details on the Evaluation board:
+# http://www.zedboard.org/content/overview
+# For design files (including 'zynq_fsbl_0.elf') for the ZedBoard:
+# http://www.zedboard.org/reference-designs-categories/zynq-concepts-tools-and-techniques-zedboard
+#
+
+SOC_VARIANT ?= "7z"
+
+require conf/machine/include/tune-zynq.inc
+require conf/machine/include/machine-xilinx-overrides.inc
+require conf/machine/include/machine-xilinx-default.inc
+require conf/machine/include/machine-xilinx-board.inc
+
+# u-boot configuration
+UBOOT_MACHINE = "zynq_zed_config"
+SPL_BINARY = "spl/boot.bin"
+
+EXTRA_IMAGEDEPENDS += " \
+ u-boot-zynq-uenv \
+ virtual/boot-bin \
+ "
+
+SERIAL_CONSOLE = "115200 ttyPS0"
+
+KERNEL_DEVICETREE = "zynq-zed.dtb"
+
+IMAGE_BOOT_FILES += "boot.bin uEnv.txt ${KERNEL_IMAGETYPE}-zynq-zed.dtb"
+
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zybo-linux-bd-zynq7.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zybo-linux-bd-zynq7.conf
new file mode 100644
index 0000000..27b6d07
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/zybo-linux-bd-zynq7.conf
@@ -0,0 +1,43 @@
+#@TYPE: Machine
+#@NAME: zybo-linux-bd-zynq7
+#@DESCRIPTION: Machine support for zybo-linux-bd project.
+#
+# generated base on ZYBO linux-bd project
+#
+
+SOC_VARIANT ?= "7z"
+
+require conf/machine/include/tune-zynq.inc
+require conf/machine/include/machine-xilinx-overrides.inc
+require conf/machine/include/machine-xilinx-default.inc
+require conf/machine/include/machine-xilinx-board.inc
+
+PREFERRED_PROVIDER_virtual/kernel ?= "linux-xlnx"
+PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot"
+
+MACHINE_FEATURES = "ext2 vfat usbhost usbgadget keyboard screen alsa sdio"
+SERIAL_CONSOLE = "115200 ttyPS0"
+
+MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree"
+
+UBOOT_MACHINE = "zynq_zybo_config"
+SPL_BINARY = "spl/boot.bin"
+FORCE_PLATFORM_INIT = "1"
+
+EXTRA_IMAGEDEPENDS += " \
+ u-boot-zynq-uenv \
+ virtual/boot-bin \
+ virtual/bitstream \
+ "
+
+IMAGE_BOOT_FILES += " \
+ boot.bin \
+ ${MACHINE}.dtb \
+ bitstream \
+ uEnv.txt \
+ "
+
+KERNEL_FEATURES += " \
+ bsp/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.scc \
+ features/v4l2/v4l2-xilinx.scc \
+ "
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zybo-zynq7.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zybo-zynq7.conf
new file mode 100644
index 0000000..5b40563
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/zybo-zynq7.conf
@@ -0,0 +1,37 @@
+#@TYPE: Machine
+#@NAME: zybo-zynq7
+#@DESCRIPTION: Machine support for ZYBO.
+#
+# For details on the ZYBO board:
+# https://www.digilentinc.com/Products/Detail.cfm?Prod=ZYBO
+#
+
+SOC_VARIANT ?= "7z"
+
+require conf/machine/include/tune-zynq.inc
+require conf/machine/include/machine-xilinx-overrides.inc
+require conf/machine/include/machine-xilinx-default.inc
+require conf/machine/include/machine-xilinx-board.inc
+
+MACHINE_FEATURES = "ext2 vfat usbhost usbgadget"
+
+# u-boot configuration
+PREFERRED_PROVIDER_virtual/bootloader = "u-boot"
+UBOOT_MACHINE = "zynq_zybo_config"
+SPL_BINARY = "spl/boot.bin"
+
+EXTRA_IMAGEDEPENDS += " \
+ u-boot-zynq-uenv \
+ virtual/boot-bin \
+ "
+
+SERIAL_CONSOLE = "115200 ttyPS0"
+
+KERNEL_DEVICETREE = "zynq-zybo.dtb"
+
+IMAGE_BOOT_FILES += " \
+ boot.bin \
+ ${KERNEL_IMAGETYPE}-zynq-zybo.dtb \
+ uEnv.txt \
+ "
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc
new file mode 100644
index 0000000..02bbc73
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc
@@ -0,0 +1,69 @@
+DESCRIPTION = "ARM Trusted Firmware"
+
+LICENSE = "BSD"
+LIC_FILES_CHKSUM = "file://license.rst;md5=33065335ea03d977d0569f270b39603e"
+
+PROVIDES = "virtual/arm-trusted-firmware"
+
+inherit deploy
+
+DEPENDS += "u-boot-mkimage-native"
+
+S = "${WORKDIR}/git"
+B = "${WORKDIR}/build"
+
+XILINX_RELEASE_VERSION ?= ""
+ATF_VERSION ?= "1.4"
+ATF_VERSION_EXTENSION ?= "-xilinx-${XILINX_RELEASE_VERSION}"
+PV = "${ATF_VERSION}${ATF_VERSION_EXTENSION}+git${SRCPV}"
+
+BRANCH ?= ""
+REPO ?= "git://github.com/Xilinx/arm-trusted-firmware.git;protocol=https"
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
+
+ATF_BASE_NAME ?= "${PN}-${PKGE}-${PKGV}-${PKGR}-${DATETIME}"
+ATF_BASE_NAME[vardepsexclude] = "DATETIME"
+
+COMPATIBLE_MACHINE = "zynqmp"
+PLATFORM_zynqmp = "zynqmp"
+
+# requires CROSS_COMPILE set by hand as there is no configure script
+export CROSS_COMPILE="${TARGET_PREFIX}"
+
+# Let the Makefile handle setting up the CFLAGS and LDFLAGS as it is a standalone application
+CFLAGS[unexport] = "1"
+LDFLAGS[unexport] = "1"
+AS[unexport] = "1"
+LD[unexport] = "1"
+
+do_configure() {
+ :
+}
+
+do_compile() {
+ oe_runmake -C ${S} BUILD_BASE=${B} PLAT=${PLATFORM} RESET_TO_BL31=1 bl31
+}
+
+do_install() {
+ :
+}
+
+OUTPUT_DIR = "${B}/${PLATFORM}/release"
+
+do_deploy() {
+ install -d ${DEPLOYDIR}
+ install -m 0644 ${OUTPUT_DIR}/bl31/bl31.elf ${DEPLOYDIR}/${ATF_BASE_NAME}.elf
+ ln -sf ${ATF_BASE_NAME}.elf ${DEPLOYDIR}/${PN}.elf
+ install -m 0644 ${OUTPUT_DIR}/bl31.bin ${DEPLOYDIR}/${ATF_BASE_NAME}.bin
+ ln -sf ${ATF_BASE_NAME}.bin ${DEPLOYDIR}/${PN}.bin
+
+ # Get the entry point address from the elf.
+ BL31_BASE_ADDR=$(${READELF} -h ${OUTPUT_DIR}/bl31/bl31.elf | egrep -m 1 -i "entry point.*?0x" | sed -r 's/.*?(0x.*?)/\1/g')
+ mkimage -A arm64 -O arm-trusted-firmware -T kernel -C none \
+ -a $BL31_BASE_ADDR -e $BL31_BASE_ADDR \
+ -d ${OUTPUT_DIR}/bl31.bin ${DEPLOYDIR}/${ATF_BASE_NAME}.ub
+ ln -sf ${ATF_BASE_NAME}.ub ${DEPLOYDIR}/${PN}.ub
+ ln -sf ${ATF_BASE_NAME}.ub ${DEPLOYDIR}/atf-uboot.ub
+}
+addtask deploy before do_build after do_compile
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2018.1.bb b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2018.1.bb
new file mode 100644
index 0000000..6a9eea6
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2018.1.bb
@@ -0,0 +1,7 @@
+ATF_VERSION = "1.4"
+XILINX_RELEASE_VERSION = "v2018.1"
+BRANCH ?= "master"
+SRCREV ?= "df4a7e97d57494c7d79de51b1e0e450d982cea98"
+
+include arm-trusted-firmware.inc
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb
new file mode 100644
index 0000000..dc49cbb
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb
@@ -0,0 +1,85 @@
+SUMMARY = "Device Trees for BSPs"
+DESCRIPTION = "Device Tree generation and packaging for BSP Device Trees."
+SECTION = "bsp"
+
+LICENSE = "MIT & GPLv2"
+LIC_FILES_CHKSUM = " \
+ file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302 \
+ file://${COMMON_LICENSE_DIR}/GPL-2.0;md5=801f80980d171dd6425610833a22dbe6 \
+ "
+
+inherit deploy kernel-arch
+
+PROVIDES = "virtual/dtb"
+
+INHIBIT_DEFAULT_DEPS = "1"
+DEPENDS += "dtc-native"
+
+COMPATIBLE_MACHINE ?= "^$"
+
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+
+FILES_${PN} = "/boot/devicetree/*.dtb /boot/devicetree/*.dtbo"
+
+S = "${WORKDIR}"
+B = "${WORKDIR}/build"
+
+SYSROOT_DIRS += "/boot/devicetree"
+
+# By default provide the current kernel arch's boot/dts and boot/dts/include.
+KERNEL_DTS_INCLUDE ??= " \
+ ${STAGING_KERNEL_DIR}/arch/${ARCH}/boot/dts \
+ ${STAGING_KERNEL_DIR}/arch/${ARCH}/boot/dts/include \
+ "
+# For arm64/zynqmp the xilinx specific includes are subdired under a vendor directory.
+KERNEL_DTS_INCLUDE_append_zynqmp = " \
+ ${STAGING_KERNEL_DIR}/arch/${ARCH}/boot/dts/xilinx \
+ "
+
+DTS_FILES_PATH ?= "${S}"
+DTS_INCLUDE ?= "${DTS_FILES_PATH} ${KERNEL_DTS_INCLUDE}"
+
+DT_PADDING_SIZE ?= "0x3000"
+DEVICETREE_FLAGS ?= " \
+ -R 8 -p ${DT_PADDING_SIZE} -b 0 \
+ ${@' '.join(['-i %s' % i for i in d.getVar('DTS_INCLUDE', True).split()])} \
+ "
+DEVICETREE_OFLAGS ?= "-@ -H epapr"
+DEVICETREE_PP_FLAGS ?= " \
+ -nostdinc -Ulinux -x assembler-with-cpp \
+ ${@' '.join(['-I%s' % i for i in d.getVar('DTS_INCLUDE', True).split()])} \
+ "
+
+python () {
+ # auto add dependency on kernel tree
+ if d.getVar("KERNEL_DTS_INCLUDE") != "":
+ d.appendVarFlag("do_compile", "depends", " virtual/kernel:do_configure")
+}
+
+do_compile() {
+ for DTS_FILE in ${DTS_FILES_PATH}/*.dts; do
+ DTS_NAME=`basename -s .dts ${DTS_FILE}`
+ ${BUILD_CPP} ${DEVICETREE_PP_FLAGS} -o `basename ${DTS_FILE}`.pp ${DTS_FILE}
+
+ # for now use the existance of the '/plugin/' tag to detect overlays
+ if grep -qse "/plugin/;" `basename ${DTS_FILE}`.pp; then
+ dtc ${DEVICETREE_OFLAGS} -I dts -O dtb ${DEVICETREE_FLAGS} -o ${DTS_NAME}.dtbo `basename ${DTS_FILE}`.pp
+ else
+ dtc -I dts -O dtb ${DEVICETREE_FLAGS} -o ${DTS_NAME}.dtb `basename ${DTS_FILE}`.pp
+ fi
+ done
+}
+
+do_install() {
+ for DTB_FILE in `ls *.dtb *.dtbo`; do
+ install -Dm 0644 ${B}/${DTB_FILE} ${D}/boot/devicetree/${DTB_FILE}
+ done
+}
+
+do_deploy() {
+ for DTB_FILE in `ls *.dtb *.dtbo`; do
+ install -Dm 0644 ${B}/${DTB_FILE} ${DEPLOYDIR}/${DTB_FILE}
+ done
+}
+addtask deploy before do_build after do_install
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bbappend
new file mode 100644
index 0000000..e128e0e
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bbappend
@@ -0,0 +1,30 @@
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+
+# common zynq include
+SRC_URI_append_zynq = " file://zynq-7000-qspi-dummy.dtsi"
+
+# device tree sources for the various machines
+COMPATIBLE_MACHINE_picozed-zynq7 = ".*"
+SRC_URI_append_picozed-zynq7 = " file://picozed-zynq7.dts"
+
+COMPATIBLE_MACHINE_microzed-zynq7 = ".*"
+SRC_URI_append_microzed-zynq7 = " file://microzed-zynq7.dts"
+
+COMPATIBLE_MACHINE_qemu-zynq7 = ".*"
+SRC_URI_append_qemu-zynq7 = " file://qemu-zynq7.dts"
+
+COMPATIBLE_MACHINE_zybo-linux-bd-zynq7 = ".*"
+SRC_URI_append_zybo-linux-bd-zynq7 = " \
+ file://zybo-linux-bd-zynq7.dts \
+ file://pcw.dtsi \
+ file://pl.dtsi \
+ "
+
+COMPATIBLE_MACHINE_kc705-microblazeel = ".*"
+SRC_URI_append_kc705-microblazeel = " \
+ file://kc705-microblazeel.dts \
+ file://pl.dtsi \
+ file://system-conf.dtsi \
+ "
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/kc705-microblazeel.dts b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/kc705-microblazeel.dts
new file mode 100644
index 0000000..45e488c
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/kc705-microblazeel.dts
@@ -0,0 +1,56 @@
+/dts-v1/;
+/include/ "pl.dtsi"
+/include/ "system-conf.dtsi"
+/ {
+ hard-reset-gpios = <&reset_gpio 0 1>;
+ aliases {
+ ethernet0 = &axi_ethernet;
+ i2c0 = &iic_main;
+ serial0 = &rs232_uart;
+ };
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+};
+
+&iic_main {
+ i2cswitch@74 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ si570: clock-generator@5d {
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ temperature-stability = <50>;
+ reg = <0x5d>;
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ };
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ eeprom@54 {
+ compatible = "at,24c08";
+ reg = <0x54>;
+ };
+ };
+ };
+};
+
+&axi_ethernet {
+ phy-handle = <&phy0>;
+ axi_ethernet_mdio: mdio {
+ phy0: phy@7 {
+ device_type = "ethernet-phy";
+ reg = <7>;
+ };
+ };
+};
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/pl.dtsi b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/pl.dtsi
new file mode 100644
index 0000000..43bc2ab
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/pl.dtsi
@@ -0,0 +1,445 @@
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,microblaze";
+ model = "Xilinx MicroBlaze";
+ cpus {
+ #address-cells = <1>;
+ #cpus = <1>;
+ #size-cells = <0>;
+ microblaze_0: cpu@0 {
+ bus-handle = <&amba_pl>;
+ clock-frequency = <200000000>;
+ clocks = <&clk_cpu>;
+ compatible = "xlnx,microblaze-10.0";
+ d-cache-baseaddr = <0x0000000080000000>;
+ d-cache-highaddr = <0x00000000bfffffff>;
+ d-cache-line-size = <0x20>;
+ d-cache-size = <0x4000>;
+ device_type = "cpu";
+ i-cache-baseaddr = <0x0000000080000000>;
+ i-cache-highaddr = <0x00000000bfffffff>;
+ i-cache-line-size = <0x10>;
+ i-cache-size = <0x4000>;
+ interrupt-handle = <µblaze_0_axi_intc>;
+ model = "microblaze,10.0";
+ timebase-frequency = <200000000>;
+ xlnx,addr-size = <0x20>;
+ xlnx,addr-tag-bits = <0x10>;
+ xlnx,allow-dcache-wr = <0x1>;
+ xlnx,allow-icache-wr = <0x1>;
+ xlnx,area-optimized = <0x0>;
+ xlnx,async-interrupt = <0x1>;
+ xlnx,async-wakeup = <0x3>;
+ xlnx,avoid-primitives = <0x0>;
+ xlnx,base-vectors = <0x0000000000000000>;
+ xlnx,branch-target-cache-size = <0x0>;
+ xlnx,cache-byte-size = <0x4000>;
+ xlnx,d-axi = <0x1>;
+ xlnx,d-lmb = <0x1>;
+ xlnx,d-lmb-mon = <0x0>;
+ xlnx,daddr-size = <0x20>;
+ xlnx,data-size = <0x20>;
+ xlnx,dc-axi-mon = <0x0>;
+ xlnx,dcache-addr-tag = <0x10>;
+ xlnx,dcache-always-used = <0x1>;
+ xlnx,dcache-byte-size = <0x4000>;
+ xlnx,dcache-data-width = <0x0>;
+ xlnx,dcache-force-tag-lutram = <0x0>;
+ xlnx,dcache-line-len = <0x8>;
+ xlnx,dcache-use-writeback = <0x0>;
+ xlnx,dcache-victims = <0x0>;
+ xlnx,debug-counter-width = <0x20>;
+ xlnx,debug-enabled = <0x1>;
+ xlnx,debug-event-counters = <0x5>;
+ xlnx,debug-external-trace = <0x0>;
+ xlnx,debug-interface = <0x0>;
+ xlnx,debug-latency-counters = <0x1>;
+ xlnx,debug-profile-size = <0x0>;
+ xlnx,debug-trace-async-reset = <0x0>;
+ xlnx,debug-trace-size = <0x2000>;
+ xlnx,div-zero-exception = <0x1>;
+ xlnx,dp-axi-mon = <0x0>;
+ xlnx,dynamic-bus-sizing = <0x0>;
+ xlnx,ecc-use-ce-exception = <0x0>;
+ xlnx,edge-is-positive = <0x1>;
+ xlnx,enable-discrete-ports = <0x0>;
+ xlnx,endianness = <0x1>;
+ xlnx,fault-tolerant = <0x0>;
+ xlnx,fpu-exception = <0x0>;
+ xlnx,freq = <0xbebc200>;
+ xlnx,fsl-exception = <0x0>;
+ xlnx,fsl-links = <0x0>;
+ xlnx,i-axi = <0x0>;
+ xlnx,i-lmb = <0x1>;
+ xlnx,i-lmb-mon = <0x0>;
+ xlnx,iaddr-size = <0x20>;
+ xlnx,ic-axi-mon = <0x0>;
+ xlnx,icache-always-used = <0x1>;
+ xlnx,icache-data-width = <0x0>;
+ xlnx,icache-force-tag-lutram = <0x0>;
+ xlnx,icache-line-len = <0x4>;
+ xlnx,icache-streams = <0x1>;
+ xlnx,icache-victims = <0x8>;
+ xlnx,ill-opcode-exception = <0x1>;
+ xlnx,imprecise-exceptions = <0x0>;
+ xlnx,instr-size = <0x20>;
+ xlnx,interconnect = <0x2>;
+ xlnx,interrupt-is-edge = <0x0>;
+ xlnx,interrupt-mon = <0x0>;
+ xlnx,ip-axi-mon = <0x0>;
+ xlnx,lockstep-master = <0x0>;
+ xlnx,lockstep-select = <0x0>;
+ xlnx,lockstep-slave = <0x0>;
+ xlnx,mmu-dtlb-size = <0x4>;
+ xlnx,mmu-itlb-size = <0x2>;
+ xlnx,mmu-privileged-instr = <0x0>;
+ xlnx,mmu-tlb-access = <0x3>;
+ xlnx,mmu-zones = <0x2>;
+ xlnx,num-sync-ff-clk = <0x2>;
+ xlnx,num-sync-ff-clk-debug = <0x2>;
+ xlnx,num-sync-ff-clk-irq = <0x1>;
+ xlnx,num-sync-ff-dbg-clk = <0x1>;
+ xlnx,num-sync-ff-dbg-trace-clk = <0x2>;
+ xlnx,number-of-pc-brk = <0x1>;
+ xlnx,number-of-rd-addr-brk = <0x0>;
+ xlnx,number-of-wr-addr-brk = <0x0>;
+ xlnx,opcode-0x0-illegal = <0x1>;
+ xlnx,optimization = <0x0>;
+ xlnx,pc-width = <0x20>;
+ xlnx,piaddr-size = <0x20>;
+ xlnx,pvr = <0x2>;
+ xlnx,pvr-user1 = <0x00>;
+ xlnx,pvr-user2 = <0x00000000>;
+ xlnx,reset-msr = <0x00000000>;
+ xlnx,reset-msr-bip = <0x0>;
+ xlnx,reset-msr-dce = <0x0>;
+ xlnx,reset-msr-ee = <0x0>;
+ xlnx,reset-msr-eip = <0x0>;
+ xlnx,reset-msr-ice = <0x0>;
+ xlnx,reset-msr-ie = <0x0>;
+ xlnx,sco = <0x0>;
+ xlnx,trace = <0x0>;
+ xlnx,unaligned-exceptions = <0x1>;
+ xlnx,use-barrel = <0x1>;
+ xlnx,use-branch-target-cache = <0x0>;
+ xlnx,use-config-reset = <0x0>;
+ xlnx,use-dcache = <0x1>;
+ xlnx,use-div = <0x1>;
+ xlnx,use-ext-brk = <0x0>;
+ xlnx,use-ext-nm-brk = <0x0>;
+ xlnx,use-extended-fsl-instr = <0x0>;
+ xlnx,use-fpu = <0x0>;
+ xlnx,use-hw-mul = <0x2>;
+ xlnx,use-icache = <0x1>;
+ xlnx,use-interrupt = <0x2>;
+ xlnx,use-mmu = <0x3>;
+ xlnx,use-msr-instr = <0x1>;
+ xlnx,use-non-secure = <0x0>;
+ xlnx,use-pcmp-instr = <0x1>;
+ xlnx,use-reorder-instr = <0x1>;
+ xlnx,use-stack-protection = <0x0>;
+ };
+ };
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clk_cpu: clk_cpu@0 {
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "clk_cpu";
+ compatible = "fixed-clock";
+ reg = <0>;
+ };
+ clk_bus_0: clk_bus_0@1 {
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "clk_bus_0";
+ compatible = "fixed-clock";
+ reg = <1>;
+ };
+ };
+ amba_pl: amba_pl {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges ;
+ axi_ethernet: ethernet@40c00000 {
+ axistream-connected = <&axi_ethernet_dma>;
+ axistream-control-connected = <&axi_ethernet_dma>;
+ clock-frequency = <100000000>;
+ compatible = "xlnx,axi-ethernet-1.00.a";
+ device_type = "network";
+ interrupt-parent = <µblaze_0_axi_intc>;
+ interrupts = <4 2>;
+ phy-mode = "gmii";
+ reg = <0x40c00000 0x40000>;
+ xlnx = <0x0>;
+ xlnx,axiliteclkrate = <0x0>;
+ xlnx,axisclkrate = <0x0>;
+ xlnx,clockselection = <0x0>;
+ xlnx,enableasyncsgmii = <0x0>;
+ xlnx,gt-type = <0x0>;
+ xlnx,gtinex = <0x0>;
+ xlnx,gtlocation = <0x0>;
+ xlnx,gtrefclksrc = <0x0>;
+ xlnx,include-dre ;
+ xlnx,instantiatebitslice0 = <0x0>;
+ xlnx,phy-type = <0x1>;
+ xlnx,phyaddr = <0x1>;
+ xlnx,rable = <0x0>;
+ xlnx,rxcsum = <0x0>;
+ xlnx,rxlane0-placement = <0x0>;
+ xlnx,rxlane1-placement = <0x0>;
+ xlnx,rxmem = <0x1000>;
+ xlnx,rxnibblebitslice0used = <0x0>;
+ xlnx,tx-in-upper-nibble = <0x1>;
+ xlnx,txcsum = <0x0>;
+ xlnx,txlane0-placement = <0x0>;
+ xlnx,txlane1-placement = <0x0>;
+ axi_ethernet_mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ axi_ethernet_dma: dma@41e00000 {
+ #dma-cells = <1>;
+ axistream-connected = <&axi_ethernet>;
+ axistream-control-connected = <&axi_ethernet>;
+ clock-frequency = <200000000>;
+ clock-names = "s_axi_lite_aclk";
+ clocks = <&clk_bus_0>;
+ compatible = "xlnx,eth-dma";
+ interrupt-parent = <µblaze_0_axi_intc>;
+ interrupts = <3 2 2 2>;
+ reg = <0x41e00000 0x10000>;
+ xlnx,include-dre ;
+ };
+ axi_timer_0: timer@41c00000 {
+ clock-frequency = <200000000>;
+ clocks = <&clk_bus_0>;
+ compatible = "xlnx,xps-timer-1.00.a";
+ interrupt-parent = <µblaze_0_axi_intc>;
+ interrupts = <5 2>;
+ reg = <0x41c00000 0x10000>;
+ xlnx,count-width = <0x20>;
+ xlnx,gen0-assert = <0x1>;
+ xlnx,gen1-assert = <0x1>;
+ xlnx,one-timer-only = <0x0>;
+ xlnx,trig0-assert = <0x1>;
+ xlnx,trig1-assert = <0x1>;
+ };
+ calib_complete_gpio: gpio@40010000 {
+ #gpio-cells = <2>;
+ compatible = "xlnx,xps-gpio-1.00.a";
+ gpio-controller ;
+ reg = <0x40010000 0x10000>;
+ xlnx,all-inputs = <0x1>;
+ xlnx,all-inputs-2 = <0x0>;
+ xlnx,all-outputs = <0x0>;
+ xlnx,all-outputs-2 = <0x0>;
+ xlnx,dout-default = <0x00000000>;
+ xlnx,dout-default-2 = <0x00000000>;
+ xlnx,gpio-width = <0x1>;
+ xlnx,gpio2-width = <0x20>;
+ xlnx,interrupt-present = <0x0>;
+ xlnx,is-dual = <0x0>;
+ xlnx,tri-default = <0xFFFFFFFF>;
+ xlnx,tri-default-2 = <0xFFFFFFFF>;
+ };
+ dip_switches_4bits: gpio@40020000 {
+ #gpio-cells = <2>;
+ compatible = "xlnx,xps-gpio-1.00.a";
+ gpio-controller ;
+ reg = <0x40020000 0x10000>;
+ xlnx,all-inputs = <0x1>;
+ xlnx,all-inputs-2 = <0x0>;
+ xlnx,all-outputs = <0x0>;
+ xlnx,all-outputs-2 = <0x0>;
+ xlnx,dout-default = <0x00000000>;
+ xlnx,dout-default-2 = <0x00000000>;
+ xlnx,gpio-width = <0x4>;
+ xlnx,gpio2-width = <0x20>;
+ xlnx,interrupt-present = <0x0>;
+ xlnx,is-dual = <0x0>;
+ xlnx,tri-default = <0xFFFFFFFF>;
+ xlnx,tri-default-2 = <0xFFFFFFFF>;
+ };
+ iic_main: i2c@40800000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <200000000>;
+ clocks = <&clk_bus_0>;
+ compatible = "xlnx,xps-iic-2.00.a";
+ interrupt-parent = <µblaze_0_axi_intc>;
+ interrupts = <1 2>;
+ reg = <0x40800000 0x10000>;
+ };
+ led_8bits: gpio@40030000 {
+ #gpio-cells = <2>;
+ compatible = "xlnx,xps-gpio-1.00.a";
+ gpio-controller ;
+ reg = <0x40030000 0x10000>;
+ xlnx,all-inputs = <0x0>;
+ xlnx,all-inputs-2 = <0x0>;
+ xlnx,all-outputs = <0x1>;
+ xlnx,all-outputs-2 = <0x0>;
+ xlnx,dout-default = <0x00000000>;
+ xlnx,dout-default-2 = <0x00000000>;
+ xlnx,gpio-width = <0x8>;
+ xlnx,gpio2-width = <0x20>;
+ xlnx,interrupt-present = <0x0>;
+ xlnx,is-dual = <0x0>;
+ xlnx,tri-default = <0xFFFFFFFF>;
+ xlnx,tri-default-2 = <0xFFFFFFFF>;
+ };
+ linear_flash: flash@60000000 {
+ bank-width = <2>;
+ compatible = "cfi-flash";
+ reg = <0x60000000 0x8000000>;
+ xlnx,axi-clk-period-ps = <0x1388>;
+ xlnx,include-datawidth-matching-0 = <0x1>;
+ xlnx,include-datawidth-matching-1 = <0x1>;
+ xlnx,include-datawidth-matching-2 = <0x1>;
+ xlnx,include-datawidth-matching-3 = <0x1>;
+ xlnx,include-negedge-ioregs = <0x0>;
+ xlnx,lflash-period-ps = <0x1388>;
+ xlnx,linear-flash-sync-burst = <0x0>;
+ xlnx,max-mem-width = <0x10>;
+ xlnx,mem-a-lsb = <0x0>;
+ xlnx,mem-a-msb = <0x1f>;
+ xlnx,mem0-type = <0x2>;
+ xlnx,mem0-width = <0x10>;
+ xlnx,mem1-type = <0x0>;
+ xlnx,mem1-width = <0x10>;
+ xlnx,mem2-type = <0x0>;
+ xlnx,mem2-width = <0x10>;
+ xlnx,mem3-type = <0x0>;
+ xlnx,mem3-width = <0x10>;
+ xlnx,num-banks-mem = <0x1>;
+ xlnx,page-size = <0x10>;
+ xlnx,parity-type-mem-0 = <0x0>;
+ xlnx,parity-type-mem-1 = <0x0>;
+ xlnx,parity-type-mem-2 = <0x0>;
+ xlnx,parity-type-mem-3 = <0x0>;
+ xlnx,port-diff = <0x0>;
+ xlnx,s-axi-en-reg = <0x0>;
+ xlnx,s-axi-mem-addr-width = <0x20>;
+ xlnx,s-axi-mem-data-width = <0x20>;
+ xlnx,s-axi-mem-id-width = <0x1>;
+ xlnx,s-axi-reg-addr-width = <0x5>;
+ xlnx,s-axi-reg-data-width = <0x20>;
+ xlnx,synch-pipedelay-0 = <0x1>;
+ xlnx,synch-pipedelay-1 = <0x1>;
+ xlnx,synch-pipedelay-2 = <0x1>;
+ xlnx,synch-pipedelay-3 = <0x1>;
+ xlnx,tavdv-ps-mem-0 = <0x1fbd0>;
+ xlnx,tavdv-ps-mem-1 = <0x3a98>;
+ xlnx,tavdv-ps-mem-2 = <0x3a98>;
+ xlnx,tavdv-ps-mem-3 = <0x3a98>;
+ xlnx,tcedv-ps-mem-0 = <0x1fbd0>;
+ xlnx,tcedv-ps-mem-1 = <0x3a98>;
+ xlnx,tcedv-ps-mem-2 = <0x3a98>;
+ xlnx,tcedv-ps-mem-3 = <0x3a98>;
+ xlnx,thzce-ps-mem-0 = <0x88b8>;
+ xlnx,thzce-ps-mem-1 = <0x1b58>;
+ xlnx,thzce-ps-mem-2 = <0x1b58>;
+ xlnx,thzce-ps-mem-3 = <0x1b58>;
+ xlnx,thzoe-ps-mem-0 = <0x1b58>;
+ xlnx,thzoe-ps-mem-1 = <0x1b58>;
+ xlnx,thzoe-ps-mem-2 = <0x1b58>;
+ xlnx,thzoe-ps-mem-3 = <0x1b58>;
+ xlnx,tlzwe-ps-mem-0 = <0xc350>;
+ xlnx,tlzwe-ps-mem-1 = <0x0>;
+ xlnx,tlzwe-ps-mem-2 = <0x0>;
+ xlnx,tlzwe-ps-mem-3 = <0x0>;
+ xlnx,tpacc-ps-flash-0 = <0x61a8>;
+ xlnx,tpacc-ps-flash-1 = <0x61a8>;
+ xlnx,tpacc-ps-flash-2 = <0x61a8>;
+ xlnx,tpacc-ps-flash-3 = <0x61a8>;
+ xlnx,twc-ps-mem-0 = <0x11170>;
+ xlnx,twc-ps-mem-1 = <0x3a98>;
+ xlnx,twc-ps-mem-2 = <0x3a98>;
+ xlnx,twc-ps-mem-3 = <0x3a98>;
+ xlnx,twp-ps-mem-0 = <0x13880>;
+ xlnx,twp-ps-mem-1 = <0x2ee0>;
+ xlnx,twp-ps-mem-2 = <0x2ee0>;
+ xlnx,twp-ps-mem-3 = <0x2ee0>;
+ xlnx,twph-ps-mem-0 = <0x13880>;
+ xlnx,twph-ps-mem-1 = <0x2ee0>;
+ xlnx,twph-ps-mem-2 = <0x2ee0>;
+ xlnx,twph-ps-mem-3 = <0x2ee0>;
+ xlnx,use-startup = <0x0>;
+ xlnx,use-startup-int = <0x0>;
+ xlnx,wr-rec-time-mem-0 = <0x186a0>;
+ xlnx,wr-rec-time-mem-1 = <0x6978>;
+ xlnx,wr-rec-time-mem-2 = <0x6978>;
+ xlnx,wr-rec-time-mem-3 = <0x6978>;
+ };
+ microblaze_0_axi_intc: interrupt-controller@41200000 {
+ #interrupt-cells = <2>;
+ compatible = "xlnx,xps-intc-1.00.a";
+ interrupt-controller ;
+ reg = <0x41200000 0x10000>;
+ xlnx,kind-of-intr = <0x0>;
+ xlnx,num-intr-inputs = <0x6>;
+ };
+ push_buttons_5bits: gpio@40040000 {
+ #gpio-cells = <2>;
+ compatible = "xlnx,xps-gpio-1.00.a";
+ gpio-controller ;
+ reg = <0x40040000 0x10000>;
+ xlnx,all-inputs = <0x1>;
+ xlnx,all-inputs-2 = <0x0>;
+ xlnx,all-outputs = <0x0>;
+ xlnx,all-outputs-2 = <0x0>;
+ xlnx,dout-default = <0x00000000>;
+ xlnx,dout-default-2 = <0x00000000>;
+ xlnx,gpio-width = <0x5>;
+ xlnx,gpio2-width = <0x20>;
+ xlnx,interrupt-present = <0x0>;
+ xlnx,is-dual = <0x0>;
+ xlnx,tri-default = <0xFFFFFFFF>;
+ xlnx,tri-default-2 = <0xFFFFFFFF>;
+ };
+ reset_gpio: gpio@40000000 {
+ #gpio-cells = <2>;
+ compatible = "xlnx,xps-gpio-1.00.a";
+ gpio-controller ;
+ reg = <0x40000000 0x10000>;
+ xlnx,all-inputs = <0x0>;
+ xlnx,all-inputs-2 = <0x0>;
+ xlnx,all-outputs = <0x1>;
+ xlnx,all-outputs-2 = <0x0>;
+ xlnx,dout-default = <0x00000000>;
+ xlnx,dout-default-2 = <0x00000000>;
+ xlnx,gpio-width = <0x1>;
+ xlnx,gpio2-width = <0x20>;
+ xlnx,interrupt-present = <0x0>;
+ xlnx,is-dual = <0x0>;
+ xlnx,tri-default = <0xFFFFFFFF>;
+ xlnx,tri-default-2 = <0xFFFFFFFF>;
+ };
+ rs232_uart: serial@44a00000 {
+ clock-frequency = <200000000>;
+ clocks = <&clk_bus_0>;
+ compatible = "xlnx,xps-uart16550-2.00.a", "ns16550a";
+ current-speed = <115200>;
+ device_type = "serial";
+ interrupt-parent = <µblaze_0_axi_intc>;
+ interrupts = <0 2>;
+ port-number = <0>;
+ reg = <0x44a00000 0x10000>;
+ reg-offset = <0x1000>;
+ reg-shift = <2>;
+ xlnx,external-xin-clk-hz = <0x17d7840>;
+ xlnx,external-xin-clk-hz-d = <0x19>;
+ xlnx,has-external-rclk = <0x0>;
+ xlnx,has-external-xin = <0x0>;
+ xlnx,is-a-16550 = <0x1>;
+ xlnx,s-axi-aclk-freq-hz-d = "200.0";
+ xlnx,use-modem-ports = <0x1>;
+ xlnx,use-user-ports = <0x1>;
+ };
+ };
+};
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/system-conf.dtsi b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/system-conf.dtsi
new file mode 100644
index 0000000..09b26c6
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/system-conf.dtsi
@@ -0,0 +1,43 @@
+/*
+ * CAUTION: This file is automatically generated by PetaLinux SDK.
+ * DO NOT modify this file
+ */
+
+
+/ {
+ chosen {
+ bootargs = "console=ttyS0,115200 earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&axi_ethernet {
+ local-mac-address = [00 0a 35 00 22 01];
+};
+
+&linear_flash {
+ reg = <0x60000000 0x08000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0x00000000 {
+ label = "fpga";
+ reg = <0x00000000 0x00b00000>;
+ };
+ partition@0x00b00000 {
+ label = "boot";
+ reg = <0x00b00000 0x00080000>;
+ };
+ partition@0x00b80000 {
+ label = "bootenv";
+ reg = <0x00b80000 0x00020000>;
+ };
+ partition@0x00ba0000 {
+ label = "kernel";
+ reg = <0x00ba0000 0x00c00000>;
+ };
+ partition@0x017a0000 {
+ label = "spare";
+ reg = <0x017a0000 0x00000000>;
+ };
+};
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/microzed-zynq7.dts b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/microzed-zynq7.dts
new file mode 100644
index 0000000..b9376a4
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/microzed-zynq7.dts
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2011 - 2014 Xilinx
+ * Copyright (C) 2016 Jagan Teki <jteki@openedev.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+ model = "Zynq MicroZED Development Board";
+ compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
+
+ aliases {
+ ethernet0 = &gem0;
+ serial0 = &uart1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+};
+
+&clkc {
+ ps-clk-frequency = <33333333>;
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+};
+
+&pinctrl0 {
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ conf-rx {
+ pins = "MIO29", "MIO31", "MIO36";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
+ "MIO35", "MIO37", "MIO38", "MIO39";
+ bias-disable;
+ };
+ };
+};
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/picozed-zynq7.dts b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/picozed-zynq7.dts
new file mode 100644
index 0000000..4ec64f5
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/picozed-zynq7.dts
@@ -0,0 +1,98 @@
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+/include/ "zynq-7000-qspi-dummy.dtsi"
+
+/ {
+ model = "Avnet picoZed";
+ compatible = "avnet,picozed", "xlnx,zynq-7000";
+
+ aliases {
+ ethernet0 = &gem0;
+ serial0 = &uart1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ reset-gpios = <&gpio0 7 1>; /* MIO 7, GPIO_ACTIVE_LOW */
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ compatible = "marvell,88e1512";
+ device_type = "ethernet-phy";
+ reg = <0>;
+ };
+};
+
+&sdhci1 {
+ status = "okay";
+ /* SD1 is onnected to a non-removable eMMC flash device */
+ non-removable;
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
+
+&qspi {
+ status = "okay";
+ primary_flash: ps7-qspi@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,m25p80", "spansion,s25fl128s", "jedec,spi-nor";
+ reg = <0x0>;
+ spi-max-frequency = <50000000>;
+ /* Example 16M partition table using U-Boot + U-Boot SPL */
+ partition@0x0 {
+ label = "boot";
+ reg = <0x0 0xe0000>;
+ };
+ partition@0xe0000 {
+ label = "ubootenv";
+ reg = <0xe0000 0x20000>;
+ };
+ partition@0x100000 {
+ label = "uboot";
+ reg = <0x100000 0x100000>;
+ };
+ partition@0x200000 {
+ label = "kernel";
+ reg = <0x200000 0x4f0000>;
+ };
+ partition@0x6f0000 {
+ label = "devicetree";
+ reg = <0x6f0000 0x10000>;
+ };
+ partition@0x700000 {
+ label = "rootfs";
+ reg = <0x700000 0x400000>;
+ };
+ partition@0xb00000 {
+ label = "spare";
+ reg = <0xb00000 0x500000>;
+ };
+ };
+};
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/qemu-zynq7.dts b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/qemu-zynq7.dts
new file mode 100644
index 0000000..cd0694d
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/qemu-zynq7.dts
@@ -0,0 +1,85 @@
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+/include/ "zynq-7000-qspi-dummy.dtsi"
+
+/ {
+ model = "Zynq A9 QEMU";
+ compatible = "qemu,xilinx-zynq-a9", "xlnx,zynq-7000";
+
+ aliases {
+ ethernet0 = &gem0;
+ serial0 = &uart1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&amba {
+ /* Setup a fixed 25 MHz clock (100Mbps) to trick the ethernet driver */
+ fixednetclk: clock {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ };
+};
+
+&gem0 {
+ status = "okay";
+ clocks = <&clkc 30>, <&clkc 30>, <&fixednetclk>, <&fixednetclk>, <&clkc 30>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy@23 {
+ device_type = "ethernet-phy";
+ reg = <23>;
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ is-dual = <1>;
+ primary_flash: ps7-qspi@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p80";
+ reg = <0x0>;
+ spi-max-frequency = <50000000>;
+ partition@0x00000000 {
+ label = "boot";
+ reg = <0x00000000 0x00500000>;
+ };
+ partition@0x00500000 {
+ label = "bootenv";
+ reg = <0x00500000 0x00020000>;
+ };
+ partition@0x00520000 {
+ label = "config";
+ reg = <0x00520000 0x00020000>;
+ };
+ partition@0x00540000 {
+ label = "image";
+ reg = <0x00540000 0x00a80000>;
+ };
+ partition@0x00fc0000 {
+ label = "spare";
+ reg = <0x00fc0000 0x00000000>;
+ };
+ };
+};
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi
new file mode 100644
index 0000000..0f678d3
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi
@@ -0,0 +1,63 @@
+/*
+ * CAUTION: This file is automatically generated by Xilinx.
+ * Version: HSI 2015.4
+ * Today is: Fri Mar 4 15:40:49 2016
+*/
+
+
+/ {
+ cpus {
+ cpu@0 {
+ operating-points = <650000 1000000 325000 1000000>;
+ };
+ };
+};
+&gem0 {
+ phy-mode = "rgmii-id";
+ status = "okay";
+ xlnx,ptp-enet-clock = <0x6750918>;
+};
+&gpio0 {
+ emio-gpio-width = <64>;
+ gpio-mask-high = <0x0>;
+ gpio-mask-low = <0x5600>;
+};
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+};
+&i2c1 {
+ clock-frequency = <400000>;
+ status = "okay";
+};
+&intc {
+ num_cpus = <2>;
+ num_interrupts = <96>;
+};
+&qspi {
+ is-dual = <0>;
+ num-cs = <1>;
+ status = "okay";
+};
+&sdhci0 {
+ status = "okay";
+ xlnx,has-cd = <0x1>;
+ xlnx,has-power = <0x0>;
+ xlnx,has-wp = <0x1>;
+};
+&uart1 {
+ current-speed = <115200>;
+ device_type = "serial";
+ port-number = <0>;
+ status = "okay";
+};
+&usb0 {
+ dr_mode = "host";
+ phy_type = "ulpi";
+ status = "okay";
+ usb-reset = <&gpio0 46 0>;
+};
+&clkc {
+ fclk-enable = <0x3>;
+ ps-clk-frequency = <50000000>;
+};
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi
new file mode 100644
index 0000000..32bc768
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi
@@ -0,0 +1,215 @@
+/*
+ * CAUTION: This file is automatically generated by Xilinx.
+ * Version: HSI 2015.4
+ * Today is: Fri Mar 4 15:40:49 2016
+*/
+
+
+/ {
+ amba_pl: amba_pl {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges ;
+ axi_dynclk_0: axi_dynclk@43c10000 {
+ compatible = "xlnx,axi-dynclk-1.0";
+ reg = <0x43c10000 0x10000>;
+ xlnx,s00-axi-addr-width = <0x5>;
+ xlnx,s00-axi-data-width = <0x20>;
+ };
+ axi_gpio_btn: gpio@41210000 {
+ #gpio-cells = <2>;
+ compatible = "xlnx,xps-gpio-1.00.a";
+ gpio-controller ;
+ reg = <0x41210000 0x10000>;
+ xlnx,all-inputs = <0x1>;
+ xlnx,all-inputs-2 = <0x0>;
+ xlnx,all-outputs = <0x0>;
+ xlnx,all-outputs-2 = <0x0>;
+ xlnx,dout-default = <0x00000000>;
+ xlnx,dout-default-2 = <0x00000000>;
+ xlnx,gpio-width = <0x4>;
+ xlnx,gpio2-width = <0x20>;
+ xlnx,interrupt-present = <0x0>;
+ xlnx,is-dual = <0x0>;
+ xlnx,tri-default = <0xFFFFFFFF>;
+ xlnx,tri-default-2 = <0xFFFFFFFF>;
+ };
+ axi_gpio_hdmi: gpio@41230000 {
+ #gpio-cells = <2>;
+ compatible = "xlnx,xps-gpio-1.00.a";
+ gpio-controller ;
+ interrupt-parent = <&intc>;
+ interrupts = <0 29 4>;
+ reg = <0x41230000 0x10000>;
+ xlnx,all-inputs = <0x1>;
+ xlnx,all-inputs-2 = <0x0>;
+ xlnx,all-outputs = <0x0>;
+ xlnx,all-outputs-2 = <0x0>;
+ xlnx,dout-default = <0x00000000>;
+ xlnx,dout-default-2 = <0x00000000>;
+ xlnx,gpio-width = <0x1>;
+ xlnx,gpio2-width = <0x20>;
+ xlnx,interrupt-present = <0x1>;
+ xlnx,is-dual = <0x0>;
+ xlnx,tri-default = <0xFFFFFFFF>;
+ xlnx,tri-default-2 = <0xFFFFFFFF>;
+ };
+ axi_gpio_led: gpio@41200000 {
+ #gpio-cells = <2>;
+ compatible = "xlnx,xps-gpio-1.00.a";
+ gpio-controller ;
+ reg = <0x41200000 0x10000>;
+ xlnx,all-inputs = <0x0>;
+ xlnx,all-inputs-2 = <0x0>;
+ xlnx,all-outputs = <0x1>;
+ xlnx,all-outputs-2 = <0x0>;
+ xlnx,dout-default = <0x00000000>;
+ xlnx,dout-default-2 = <0x00000000>;
+ xlnx,gpio-width = <0x4>;
+ xlnx,gpio2-width = <0x20>;
+ xlnx,interrupt-present = <0x0>;
+ xlnx,is-dual = <0x0>;
+ xlnx,tri-default = <0xFFFFFFFF>;
+ xlnx,tri-default-2 = <0xFFFFFFFF>;
+ };
+ axi_gpio_sw: gpio@41220000 {
+ #gpio-cells = <2>;
+ compatible = "xlnx,xps-gpio-1.00.a";
+ gpio-controller ;
+ reg = <0x41220000 0x10000>;
+ xlnx,all-inputs = <0x1>;
+ xlnx,all-inputs-2 = <0x0>;
+ xlnx,all-outputs = <0x0>;
+ xlnx,all-outputs-2 = <0x0>;
+ xlnx,dout-default = <0x00000000>;
+ xlnx,dout-default-2 = <0x00000000>;
+ xlnx,gpio-width = <0x4>;
+ xlnx,gpio2-width = <0x20>;
+ xlnx,interrupt-present = <0x0>;
+ xlnx,is-dual = <0x0>;
+ xlnx,tri-default = <0xFFFFFFFF>;
+ xlnx,tri-default-2 = <0xFFFFFFFF>;
+ };
+ axi_i2s_adi_0: axi_i2s_adi@43c20000 {
+ compatible = "xlnx,axi-i2s-adi-1.0";
+ reg = <0x43c20000 0x10000>;
+ xlnx,bclk-pol = <0x0>;
+ xlnx,dma-type = <0x1>;
+ xlnx,has-rx = <0x1>;
+ xlnx,has-tx = <0x1>;
+ xlnx,lrclk-pol = <0x0>;
+ xlnx,num-ch = <0x1>;
+ xlnx,s-axi-min-size = <0x000001FF>;
+ xlnx,slot-width = <0x18>;
+ };
+ axi_vdma_0: dma@43000000 {
+ #dma-cells = <1>;
+ compatible = "xlnx,axi-vdma-1.00.a";
+ clocks = <&clkc 15>;
+ clock-names = "s_axi_lite_aclk";
+ interrupt-parent = <&intc>;
+ interrupts = <0 30 4>;
+ reg = <0x43000000 0x10000>;
+ xlnx,flush-fsync = <0x1>;
+ xlnx,num-fstores = <0x1>;
+ dma-channel@43000000 {
+ compatible = "xlnx,axi-vdma-mm2s-channel";
+ interrupts = <0 30 4>;
+ xlnx,datawidth = <0x20>;
+ xlnx,device-id = <0x0>;
+ };
+ };
+ v_tc_0: v_tc@43c00000 {
+ compatible = "xlnx,v-tc-6.1";
+ interrupt-parent = <&intc>;
+ interrupts = <0 31 4>;
+ reg = <0x43c00000 0x10000>;
+ xlnx,det-achroma-en = <0x0>;
+ xlnx,det-avideo-en = <0x1>;
+ xlnx,det-fieldid-en = <0x0>;
+ xlnx,det-hblank-en = <0x1>;
+ xlnx,det-hsync-en = <0x1>;
+ xlnx,det-vblank-en = <0x1>;
+ xlnx,det-vsync-en = <0x1>;
+ xlnx,detect-en = <0x0>;
+ xlnx,fsync-hstart0 = <0x0>;
+ xlnx,fsync-hstart1 = <0x0>;
+ xlnx,fsync-hstart10 = <0x0>;
+ xlnx,fsync-hstart11 = <0x0>;
+ xlnx,fsync-hstart12 = <0x0>;
+ xlnx,fsync-hstart13 = <0x0>;
+ xlnx,fsync-hstart14 = <0x0>;
+ xlnx,fsync-hstart15 = <0x0>;
+ xlnx,fsync-hstart2 = <0x0>;
+ xlnx,fsync-hstart3 = <0x0>;
+ xlnx,fsync-hstart4 = <0x0>;
+ xlnx,fsync-hstart5 = <0x0>;
+ xlnx,fsync-hstart6 = <0x0>;
+ xlnx,fsync-hstart7 = <0x0>;
+ xlnx,fsync-hstart8 = <0x0>;
+ xlnx,fsync-hstart9 = <0x0>;
+ xlnx,fsync-vstart0 = <0x0>;
+ xlnx,fsync-vstart1 = <0x0>;
+ xlnx,fsync-vstart10 = <0x0>;
+ xlnx,fsync-vstart11 = <0x0>;
+ xlnx,fsync-vstart12 = <0x0>;
+ xlnx,fsync-vstart13 = <0x0>;
+ xlnx,fsync-vstart14 = <0x0>;
+ xlnx,fsync-vstart15 = <0x0>;
+ xlnx,fsync-vstart2 = <0x0>;
+ xlnx,fsync-vstart3 = <0x0>;
+ xlnx,fsync-vstart4 = <0x0>;
+ xlnx,fsync-vstart5 = <0x0>;
+ xlnx,fsync-vstart6 = <0x0>;
+ xlnx,fsync-vstart7 = <0x0>;
+ xlnx,fsync-vstart8 = <0x0>;
+ xlnx,fsync-vstart9 = <0x0>;
+ xlnx,gen-achroma-en = <0x0>;
+ xlnx,gen-achroma-polarity = <0x1>;
+ xlnx,gen-auto-switch = <0x0>;
+ xlnx,gen-avideo-en = <0x1>;
+ xlnx,gen-avideo-polarity = <0x1>;
+ xlnx,gen-cparity = <0x0>;
+ xlnx,gen-f0-vblank-hend = <0x500>;
+ xlnx,gen-f0-vblank-hstart = <0x500>;
+ xlnx,gen-f0-vframe-size = <0x2ee>;
+ xlnx,gen-f0-vsync-hend = <0x500>;
+ xlnx,gen-f0-vsync-hstart = <0x500>;
+ xlnx,gen-f0-vsync-vend = <0x2d9>;
+ xlnx,gen-f0-vsync-vstart = <0x2d4>;
+ xlnx,gen-f1-vblank-hend = <0x500>;
+ xlnx,gen-f1-vblank-hstart = <0x500>;
+ xlnx,gen-f1-vframe-size = <0x2ee>;
+ xlnx,gen-f1-vsync-hend = <0x500>;
+ xlnx,gen-f1-vsync-hstart = <0x500>;
+ xlnx,gen-f1-vsync-vend = <0x2d9>;
+ xlnx,gen-f1-vsync-vstart = <0x2d4>;
+ xlnx,gen-fieldid-en = <0x0>;
+ xlnx,gen-fieldid-polarity = <0x1>;
+ xlnx,gen-hactive-size = <0x500>;
+ xlnx,gen-hblank-en = <0x1>;
+ xlnx,gen-hblank-polarity = <0x1>;
+ xlnx,gen-hframe-size = <0x672>;
+ xlnx,gen-hsync-en = <0x1>;
+ xlnx,gen-hsync-end = <0x596>;
+ xlnx,gen-hsync-polarity = <0x1>;
+ xlnx,gen-hsync-start = <0x56e>;
+ xlnx,gen-interlaced = <0x0>;
+ xlnx,gen-vactive-size = <0x2d0>;
+ xlnx,gen-vblank-en = <0x1>;
+ xlnx,gen-vblank-polarity = <0x1>;
+ xlnx,gen-video-format = <0x2>;
+ xlnx,gen-vsync-en = <0x1>;
+ xlnx,gen-vsync-polarity = <0x1>;
+ xlnx,generate-en = <0x1>;
+ xlnx,has-axi4-lite = <0x1>;
+ xlnx,has-intc-if = <0x0>;
+ xlnx,interlace-en = <0x0>;
+ xlnx,max-lines = <0x1000>;
+ xlnx,max-pixels = <0x1000>;
+ xlnx,num-fsyncs = <0x1>;
+ xlnx,sync-en = <0x0>;
+ };
+ };
+};
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts
new file mode 100644
index 0000000..1965439
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts
@@ -0,0 +1,184 @@
+/dts-v1/;
+/include/ "skeleton.dtsi"
+/include/ "zynq-7000.dtsi"
+/include/ "zynq-7000-qspi-dummy.dtsi"
+/include/ "pcw.dtsi"
+/include/ "pl.dtsi"
+
+/ {
+ model = "Digilent-Zybo-Linux-BD-v2015.4";
+ aliases {
+ serial0 = &uart1;
+ ethernet0 = &gem0;
+ spi0 = &qspi;
+ };
+ chosen {
+ bootargs = "";
+ stdout-path = "serial0:115200n8";
+ };
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x20000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ btn4 {
+ label = "btn4";
+ gpios = <&gpio0 50 0>;
+ linux,code = <108>; /* down */
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ btn5 {
+ label = "btn5";
+ gpios = <&gpio0 51 0>;
+ linux,code = <103>; /* up */
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ usb_phy0: usb_phy@0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ reset-gpios = <&gpio0 46 1>;
+ };
+};
+
+&amba {
+ u-boot,dm-pre-reloc;
+};
+
+&amba_pl {
+ encoder_0: digilent_encoder {
+ compatible = "digilent,drm-encoder";
+ dglnt,edid-i2c = <&i2c1>;
+ };
+
+ xilinx_drm {
+ compatible = "xlnx,drm";
+ xlnx,vtc = <&v_tc_0>;
+ xlnx,connector-type = "HDMIA";
+ xlnx,encoder-slave = <&encoder_0>;
+ clocks = <&axi_dynclk_0>;
+ planes {
+ xlnx,pixel-format = "xrgb8888";
+ plane0 {
+ dmas = <&axi_vdma_0 0>;
+ dma-names = "dma0";
+ };
+ };
+ };
+
+ i2s_clk: i2s_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12288000>;
+ clock-output-names = "i2s_clk";
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "ZYBO-Sound-Card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink0_master>;
+ simple-audio-card,frame-master = <&dailink0_master>;
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Line", "Line In Jack";
+ simple-audio-card,routing =
+ "MICIN", "Microphone Jack",
+ "Headphone Jack", "LHPOUT",
+ "Headphone Jack", "RHPOUT",
+ "LLINEIN", "Line In Jack",
+ "RLINEIN", "Line In Jack";
+ dailink0_master: simple-audio-card,cpu {
+ clocks = <&i2s_clk>;
+ sound-dai = <&axi_i2s_adi_0>;
+ };
+ simple-audio-card,codec {
+ clocks = <&i2s_clk>;
+ sound-dai = <&ssm2603>;
+ };
+ };
+};
+
+&axi_dynclk_0 {
+ compatible = "digilent,axi-dynclk";
+ #clock-cells = <0>;
+ clocks = <&clkc 15>;
+};
+
+&axi_i2s_adi_0 {
+ #sound-dai-cells = <0>;
+ compatible = "adi,axi-i2s-1.00.a";
+ clocks = <&clkc 15>, <&i2s_clk>;
+ clock-names = "axi", "ref";
+ dmas = <&dmac_s 0 &dmac_s 1>;
+ dma-names = "tx", "rx";
+};
+
+&gem0 {
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ local-mac-address = [];
+ phy0: phy@0 {
+ device_type = "ethernet-phy";
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ eeprom@50 {
+ /* Microchip 24AA02E48 */
+ compatible = "microchip,24c02";
+ reg = <0x50>;
+ };
+
+ ssm2603: ssm2603@1a{
+ #sound-dai-cells = <0>;
+ compatible = "adi,ssm2603";
+ reg = <0x1a>;
+ };
+};
+
+&qspi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ flash0: flash@0 {
+ compatible = "micron,m25p80", "s25fl128s";
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <50000000>;
+ partition@0x00000000 {
+ label = "boot";
+ reg = <0x00000000 0x00300000>;
+ };
+ partition@0x00300000 {
+ label = "bootenv";
+ reg = <0x00300000 0x00020000>;
+ };
+ partition@0x00320000 {
+ label = "kernel";
+ reg = <0x00320000 0x00a80000>;
+ };
+ partition@0x00da0000 {
+ label = "spare";
+ reg = <0x00da0000 0x00000000>;
+ };
+ };
+};
+
+&usb0 {
+ usb-phy = <&usb_phy0>;
+};
+
+&v_tc_0 {
+ compatible = "xlnx,v-tc-5.01.a";
+};
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zynq-7000-qspi-dummy.dtsi b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zynq-7000-qspi-dummy.dtsi
new file mode 100644
index 0000000..d059a2d
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/files/zynq-7000-qspi-dummy.dtsi
@@ -0,0 +1,4 @@
+&amba {
+ /* empty defintion for kernels that don't have qspi node */
+ qspi: spi@e000d000 { };
+};
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init.bb b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init.bb
new file mode 100644
index 0000000..32509b0
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init.bb
@@ -0,0 +1,38 @@
+SUMMARY = "Xilinx Platform Headers"
+DESCRPTION = "Xilinx ps*_init_gpl.c/h platform init code, used for building u-boot-spl and fsbl"
+HOMEPAGE = "http://www.xilinx.com"
+SECTION = "bsp"
+
+INHIBIT_DEFAULT_DEPS = "1"
+
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+
+inherit xilinx-platform-init
+
+COMPATIBLE_MACHINE = "$^"
+COMPATIBLE_MACHINE_picozed-zynq7 = "picozed-zynq7"
+
+LICENSE = "GPLv2+"
+LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/GPL-2.0;md5=801f80980d171dd6425610833a22dbe6"
+
+PROVIDES += "virtual/xilinx-platform-init"
+
+SRC_URI = "${@" ".join(["file://%s" % f for f in (d.getVar('PLATFORM_INIT_FILES') or "").split()])}"
+
+S = "${WORKDIR}"
+
+SYSROOT_DIRS += "${PLATFORM_INIT_DIR}"
+
+do_compile() {
+ :
+}
+
+do_install() {
+ install -d ${D}${PLATFORM_INIT_DIR}
+ for i in ${PLATFORM_INIT_FILES}; do
+ install -m 0644 ${S}/$i ${D}${PLATFORM_INIT_DIR}/
+ done
+}
+
+FILES_${PN} += "${PLATFORM_INIT_DIR}/*"
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c
new file mode 100644
index 0000000..5587ab2
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c
@@ -0,0 +1,13191 @@
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License along
+* with this program; if not, see <http://www.gnu.org/licenses/>
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include "ps7_init_gpl.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x4
+ // .. .. ==> 0XF8000110[7:4] = 0x00000004U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x3c
+ // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0x4
+ // .. .. ==> 0XF8000118[7:4] = 0x00000004U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000118[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x3c
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0x23
+ // .. ==> 0XF8000128[13:8] = 0x00000023U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
+ // .. DIVISOR1 = 0x3
+ // .. ==> 0XF8000128[25:20] = 0x00000003U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x10
+ // .. ==> 0XF8000140[13:8] = 0x00000010U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001000U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000140[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0xa
+ // .. ==> 0XF800014C[13:8] = 0x0000000AU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000150[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000150[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x28
+ // .. ==> 0XF8000150[13:8] = 0x00000028U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002800U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x28
+ // .. ==> 0XF8000154[13:8] = 0x00000028U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002800U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U),
+ // .. .. START: TRACE CLOCK
+ // .. .. FINISH: TRACE CLOCK
+ // .. .. CLKACT = 0x1
+ // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR = 0xa
+ // .. .. ==> 0XF8000168[13:8] = 0x0000000AU
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x14
+ // .. .. ==> 0XF8000170[13:8] = 0x00000014U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. .. DIVISOR1 = 0x1
+ // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x14
+ // .. .. ==> 0XF8000180[13:8] = 0x00000014U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. .. DIVISOR1 = 0x1
+ // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x3c
+ // .. .. ==> 0XF8000190[13:8] = 0x0000003CU
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U
+ // .. .. DIVISOR1 = 0x1
+ // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x28
+ // .. .. ==> 0XF80001A0[13:8] = 0x00000028U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U
+ // .. .. DIVISOR1 = 0x1
+ // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U),
+ // .. .. CLK_621_TRUE = 0x1
+ // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. .. DMA_CPU_2XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. USB0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. USB1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. .. GEM0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. .. GEM1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. SDI0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. SDI1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[11:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U
+ // .. .. SPI0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. SPI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. CAN0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. CAN1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. I2C0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. .. I2C1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. .. UART0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. UART1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. GPIO_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. .. SMC_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+ // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
+ // .. .. reserved_reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1a
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
+ // .. .. reg_ddrc_t_rfc_min = 0xa0
+ // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+ // .. .. reg_ddrc_wr2pre = 0x12
+ // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x16
+ // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x13
+ // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xe
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
+ // .. .. reg_ddrc_t_xp = 0x4
+ // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x4
+ // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x6
+ // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0x930
+ // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+ // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+ // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
+ // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+ // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
+ // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+ // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
+ // .. .. reg_ddrc_t_cksre = 0x6
+ // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_t_cksrx = 0x6
+ // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_t_ckesr = 0x4
+ // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+ // .. .. reg_ddrc_t_ckpde = 0x2
+ // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
+ // .. .. reg_ddrc_t_ckpdx = 0x2
+ // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. reg_ddrc_t_ckdpde = 0x2
+ // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_ckdpdx = 0x2
+ // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
+ // .. .. reg_ddrc_t_ckcsx = 0x3
+ // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. START: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+ // .. .. FINISH: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xa1
+ // .. .. ==> 0XF800612C[19:10] = 0x000000A1U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xa0
+ // .. .. ==> 0XF8006130[19:10] = 0x000000A0U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x7
+ // .. .. ==> 0XF8006134[9:0] = 0x00000007U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xad
+ // .. .. ==> 0XF8006134[19:10] = 0x000000ADU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x7
+ // .. .. ==> 0XF8006138[9:0] = 0x00000007U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xad
+ // .. .. ==> 0XF8006138[19:10] = 0x000000ADU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
+ // .. .. ==> 0XF8006154[9:0] = 0x0000007CU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
+ // .. .. ==> 0XF8006158[9:0] = 0x0000007CU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x87
+ // .. .. ==> 0XF800615C[9:0] = 0x00000087U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x87
+ // .. .. ==> 0XF8006160[9:0] = 0x00000087U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf6
+ // .. .. ==> 0XF8006168[10:0] = 0x000000F6U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
+ // .. .. ==> 0XF800616C[10:0] = 0x000000F5U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x102
+ // .. .. ==> 0XF8006170[10:0] = 0x00000102U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x102
+ // .. .. ==> 0XF8006174[10:0] = 0x00000102U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xbc
+ // .. .. ==> 0XF800617C[9:0] = 0x000000BCU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xbc
+ // .. .. ==> 0XF8006180[9:0] = 0x000000BCU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc7
+ // .. .. ==> 0XF8006184[9:0] = 0x000000C7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc7
+ // .. .. ==> 0XF8006188[9:0] = 0x000000C7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U),
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. reserved_SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x1
+ // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_SEL = 0x4
+ // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
+ // .. VREF_EXT_EN = 0x0
+ // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. reserved_VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. reserved_REFIO_TEST = 0x0
+ // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+ // .. ==> MASK : 0x00000C00U VAL : 0x00000000U
+ // .. reserved_REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. reserved_DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. reserved_CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reserved_VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reserved_VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reserved_VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reserved_VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reserved_VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reserved_INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reserved_TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reserved_TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reserved_TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. reserved_TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reserved_INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000700[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000700[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000700[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000704[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000704[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000708[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800070C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000710[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000714[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000718[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800071C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000720[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000724[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000724[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF8000728[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000728[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000728[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF800072C[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800072C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800072C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF8000730[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000730[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000730[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF8000734[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000734[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000734[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF8000738[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000738[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000738[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800073C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800073C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800073C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800073C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF800073C[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800073C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800073C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000740[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000744[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000748[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800074C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000750[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000754[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000758[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800075C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000760[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000764[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000768[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800076C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000770[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000774[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000778[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800077C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000780[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000784[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000788[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800078C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000790[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000794[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000798[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800079C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007A0[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007A4[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007A8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007AC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007B0[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007B4[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007B8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007BC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007BC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007BC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007BC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007BC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007BC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007CC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007CC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO1_CD_SEL = 58
+ // .. ==> 0XF8000834[21:16] = 0x0000003AU
+ // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: TPIU WIDTH IN CASE OF EMIO
+ // .. .. START: TRACE LOCK ACCESS REGISTER
+ // .. .. a = 0XC5ACCE55
+ // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+ // .. .. START: TRACE CURRENT PORT SIZE
+ // .. .. a = 2
+ // .. .. ==> 0XF8803004[31:0] = 0x00000002U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U),
+ // .. .. FINISH: TRACE CURRENT PORT SIZE
+ // .. .. START: TRACE LOCK ACCESS REGISTER
+ // .. .. a = 0X0
+ // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+ // .. FINISH: TPIU WIDTH IN CASE OF EMIO
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. DIRECTION_0 = 0x80
+ // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. OP_ENABLE_0 = 0x80
+ // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
+ // .. .. .. START: USB1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB1 RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. .. START: ENET0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET0 RESET
+ // .. .. .. START: ENET1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET1 RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. .. START: I2C0 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C0 RESET
+ // .. .. .. START: I2C1 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C1 RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_LVL_INP_EN_0 = 1
+ // .. ==> 0XF8000900[3:3] = 0x00000001U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. USER_LVL_OUT_EN_0 = 1
+ // .. ==> 0XF8000900[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. USER_LVL_INP_EN_1 = 1
+ // .. ==> 0XF8000900[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. USER_LVL_OUT_EN_1 = 1
+ // .. ==> 0XF8000900[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: TPIU WIDTH IN CASE OF EMIO
+ // .. .. START: TRACE LOCK ACCESS REGISTER
+ // .. .. a = 0XC5ACCE55
+ // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+ // .. .. START: TRACE CURRENT PORT SIZE
+ // .. .. a = 2
+ // .. .. ==> 0XF8803004[31:0] = 0x00000002U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U),
+ // .. .. FINISH: TRACE CURRENT PORT SIZE
+ // .. .. START: TRACE LOCK ACCESS REGISTER
+ // .. .. a = 0X0
+ // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+ // .. FINISH: TPIU WIDTH IN CASE OF EMIO
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. reserved_FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. reserved_FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. reserved_FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. reserved_FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. reserved_FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_3_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x4
+ // .. .. ==> 0XF8000110[7:4] = 0x00000004U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x3c
+ // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0x4
+ // .. .. ==> 0XF8000118[7:4] = 0x00000004U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000118[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x3c
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0x23
+ // .. ==> 0XF8000128[13:8] = 0x00000023U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
+ // .. DIVISOR1 = 0x3
+ // .. ==> 0XF8000128[25:20] = 0x00000003U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x10
+ // .. ==> 0XF8000140[13:8] = 0x00000010U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001000U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000140[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0xa
+ // .. ==> 0XF800014C[13:8] = 0x0000000AU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000150[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000150[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x28
+ // .. ==> 0XF8000150[13:8] = 0x00000028U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002800U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x28
+ // .. ==> 0XF8000154[13:8] = 0x00000028U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002800U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U),
+ // .. .. START: TRACE CLOCK
+ // .. .. FINISH: TRACE CLOCK
+ // .. .. CLKACT = 0x1
+ // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR = 0xa
+ // .. .. ==> 0XF8000168[13:8] = 0x0000000AU
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x14
+ // .. .. ==> 0XF8000170[13:8] = 0x00000014U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. .. DIVISOR1 = 0x1
+ // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x14
+ // .. .. ==> 0XF8000180[13:8] = 0x00000014U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. .. DIVISOR1 = 0x1
+ // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x3c
+ // .. .. ==> 0XF8000190[13:8] = 0x0000003CU
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U
+ // .. .. DIVISOR1 = 0x1
+ // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x28
+ // .. .. ==> 0XF80001A0[13:8] = 0x00000028U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U
+ // .. .. DIVISOR1 = 0x1
+ // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U),
+ // .. .. CLK_621_TRUE = 0x1
+ // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. .. DMA_CPU_2XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. USB0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. USB1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. .. GEM0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. .. GEM1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. SDI0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. SDI1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[11:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U
+ // .. .. SPI0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. SPI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. CAN0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. CAN1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. I2C0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. .. I2C1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. .. UART0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. UART1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. GPIO_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. .. SMC_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+ // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
+ // .. .. reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_block = 0x1
+ // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
+ // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+ // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+ // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_open_bank = 0x0
+ // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+ // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1a
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
+ // .. .. reg_ddrc_t_rfc_min = 0xa0
+ // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+ // .. .. reg_ddrc_wr2pre = 0x12
+ // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x16
+ // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x13
+ // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xe
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
+ // .. .. reg_ddrc_t_xp = 0x4
+ // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x4
+ // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x6
+ // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_sdram = 0x1
+ // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_clock_stop_en = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_loopback = 0x0
+ // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_max_rank_rd = 0xf
+ // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+ // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0x930
+ // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+ // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_debug_mode = 0x0
+ // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_phy_wr_level_start = 0x0
+ // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_phy_rd_level_start = 0x0
+ // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_dq0_wait_t = 0x0
+ // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reg_ddrc_rank1_rd_odt = 0x1
+ // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+ // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
+ // .. .. reg_ddrc_rank1_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reg_ddrc_rank2_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+ // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank2_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+ // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+ // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+ // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+ // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+ // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
+ // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+ // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
+ // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+ // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
+ // .. .. reg_ddrc_t_cksre = 0x6
+ // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_t_cksrx = 0x6
+ // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_t_ckesr = 0x4
+ // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+ // .. .. reg_ddrc_t_ckpde = 0x2
+ // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
+ // .. .. reg_ddrc_t_ckpdx = 0x2
+ // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. reg_ddrc_t_ckdpde = 0x2
+ // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_ckdpdx = 0x2
+ // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
+ // .. .. reg_ddrc_t_ckcsx = 0x3
+ // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+ // .. .. refresh_timer0_start_value_x32 = 0x0
+ // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
+ // .. .. refresh_timer1_start_value_x32 = 0x8
+ // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_2t_delay = 0x0
+ // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. .. reg_ddrc_dis_pre_bypass = 0x0
+ // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. START: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+ // .. .. FINISH: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xa1
+ // .. .. ==> 0XF800612C[19:10] = 0x000000A1U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xa0
+ // .. .. ==> 0XF8006130[19:10] = 0x000000A0U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x7
+ // .. .. ==> 0XF8006134[9:0] = 0x00000007U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xad
+ // .. .. ==> 0XF8006134[19:10] = 0x000000ADU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x7
+ // .. .. ==> 0XF8006138[9:0] = 0x00000007U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xad
+ // .. .. ==> 0XF8006138[19:10] = 0x000000ADU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
+ // .. .. ==> 0XF8006154[9:0] = 0x0000007CU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
+ // .. .. ==> 0XF8006158[9:0] = 0x0000007CU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x87
+ // .. .. ==> 0XF800615C[9:0] = 0x00000087U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x87
+ // .. .. ==> 0XF8006160[9:0] = 0x00000087U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf6
+ // .. .. ==> 0XF8006168[10:0] = 0x000000F6U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
+ // .. .. ==> 0XF800616C[10:0] = 0x000000F5U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x102
+ // .. .. ==> 0XF8006170[10:0] = 0x00000102U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x102
+ // .. .. ==> 0XF8006174[10:0] = 0x00000102U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xbc
+ // .. .. ==> 0XF800617C[9:0] = 0x000000BCU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xbc
+ // .. .. ==> 0XF8006180[9:0] = 0x000000BCU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc7
+ // .. .. ==> 0XF8006184[9:0] = 0x000000C7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc7
+ // .. .. ==> 0XF8006188[9:0] = 0x000000C7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U),
+ // .. .. reg_phy_loopback = 0x0
+ // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+ // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_use_rank0_delays = 0x1
+ // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_phy_int_lpbk = 0x0
+ // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_per_bank_refresh = 0x0
+ // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x1
+ // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_SEL = 0x4
+ // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
+ // .. VREF_EXT_EN = 0x0
+ // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. REFIO_TEST = 0x0
+ // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+ // .. ==> MASK : 0x00000C00U VAL : 0x00000000U
+ // .. REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000700[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000700[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000700[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000704[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000704[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000708[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800070C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000710[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000714[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000718[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800071C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000720[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000724[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000724[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF8000728[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000728[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000728[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF800072C[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800072C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800072C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF8000730[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000730[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000730[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF8000734[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000734[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000734[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF8000738[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000738[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000738[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800073C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800073C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800073C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800073C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF800073C[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800073C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800073C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000740[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000744[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000748[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800074C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000750[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000754[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000758[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800075C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000760[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000764[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000768[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800076C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000770[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000774[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000778[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800077C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000780[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000784[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000788[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800078C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000790[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000794[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000798[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800079C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007A0[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007A4[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007A8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007AC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007B0[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007B4[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007B8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007BC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007BC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007BC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007BC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007BC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007BC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007CC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007CC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO1_CD_SEL = 58
+ // .. ==> 0XF8000834[21:16] = 0x0000003AU
+ // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. IRMODE = 0x0
+ // .. ==> 0XE0001004[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. UCLKEN = 0x0
+ // .. ==> 0XE0001004[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: TPIU WIDTH IN CASE OF EMIO
+ // .. .. START: TRACE LOCK ACCESS REGISTER
+ // .. .. a = 0XC5ACCE55
+ // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+ // .. .. START: TRACE CURRENT PORT SIZE
+ // .. .. a = 2
+ // .. .. ==> 0XF8803004[31:0] = 0x00000002U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U),
+ // .. .. FINISH: TRACE CURRENT PORT SIZE
+ // .. .. START: TRACE LOCK ACCESS REGISTER
+ // .. .. a = 0X0
+ // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+ // .. FINISH: TPIU WIDTH IN CASE OF EMIO
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. DIRECTION_0 = 0x80
+ // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. OP_ENABLE_0 = 0x80
+ // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
+ // .. .. .. START: USB1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB1 RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. .. START: ENET0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET0 RESET
+ // .. .. .. START: ENET1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET1 RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. .. START: I2C0 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C0 RESET
+ // .. .. .. START: I2C1 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C1 RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_INP_ICT_EN_0 = 3
+ // .. ==> 0XF8000900[1:0] = 0x00000003U
+ // .. ==> MASK : 0x00000003U VAL : 0x00000003U
+ // .. USER_INP_ICT_EN_1 = 3
+ // .. ==> 0XF8000900[3:2] = 0x00000003U
+ // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: TPIU WIDTH IN CASE OF EMIO
+ // .. .. START: TRACE LOCK ACCESS REGISTER
+ // .. .. a = 0XC5ACCE55
+ // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+ // .. .. START: TRACE CURRENT PORT SIZE
+ // .. .. a = 2
+ // .. .. ==> 0XF8803004[31:0] = 0x00000002U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U),
+ // .. .. FINISH: TRACE CURRENT PORT SIZE
+ // .. .. START: TRACE LOCK ACCESS REGISTER
+ // .. .. a = 0X0
+ // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+ // .. FINISH: TPIU WIDTH IN CASE OF EMIO
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_2_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x4
+ // .. .. ==> 0XF8000110[7:4] = 0x00000004U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x3c
+ // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0x4
+ // .. .. ==> 0XF8000118[7:4] = 0x00000004U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000118[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x3c
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0x23
+ // .. ==> 0XF8000128[13:8] = 0x00000023U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
+ // .. DIVISOR1 = 0x3
+ // .. ==> 0XF8000128[25:20] = 0x00000003U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x10
+ // .. ==> 0XF8000140[13:8] = 0x00000010U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001000U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000140[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0xa
+ // .. ==> 0XF800014C[13:8] = 0x0000000AU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000150[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000150[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x28
+ // .. ==> 0XF8000150[13:8] = 0x00000028U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002800U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x28
+ // .. ==> 0XF8000154[13:8] = 0x00000028U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002800U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U),
+ // .. .. START: TRACE CLOCK
+ // .. .. FINISH: TRACE CLOCK
+ // .. .. CLKACT = 0x1
+ // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR = 0xa
+ // .. .. ==> 0XF8000168[13:8] = 0x0000000AU
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x14
+ // .. .. ==> 0XF8000170[13:8] = 0x00000014U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. .. DIVISOR1 = 0x1
+ // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x14
+ // .. .. ==> 0XF8000180[13:8] = 0x00000014U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. .. DIVISOR1 = 0x1
+ // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x3c
+ // .. .. ==> 0XF8000190[13:8] = 0x0000003CU
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U
+ // .. .. DIVISOR1 = 0x1
+ // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U),
+ // .. .. SRCSEL = 0x0
+ // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. DIVISOR0 = 0x28
+ // .. .. ==> 0XF80001A0[13:8] = 0x00000028U
+ // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U
+ // .. .. DIVISOR1 = 0x1
+ // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U),
+ // .. .. CLK_621_TRUE = 0x1
+ // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. .. DMA_CPU_2XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. USB0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. USB1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. .. GEM0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. .. GEM1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. SDI0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. SDI1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[11:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U
+ // .. .. SPI0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. SPI1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. CAN0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. CAN1_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. I2C0_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. .. I2C1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. .. UART0_CPU_1XCLKACT = 0x0
+ // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. UART1_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. GPIO_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. .. SMC_CPU_1XCLKACT = 0x1
+ // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+ // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
+ // .. .. reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_block = 0x1
+ // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
+ // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+ // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+ // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_open_bank = 0x0
+ // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+ // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1a
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
+ // .. .. reg_ddrc_t_rfc_min = 0xa0
+ // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+ // .. .. reg_ddrc_wr2pre = 0x12
+ // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x16
+ // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x13
+ // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xe
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
+ // .. .. reg_ddrc_t_xp = 0x4
+ // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x4
+ // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x6
+ // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_sdram = 0x1
+ // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_clock_stop_en = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_loopback = 0x0
+ // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_max_rank_rd = 0xf
+ // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+ // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0x930
+ // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+ // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_debug_mode = 0x0
+ // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_phy_wr_level_start = 0x0
+ // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_phy_rd_level_start = 0x0
+ // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_dq0_wait_t = 0x0
+ // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reg_ddrc_rank1_rd_odt = 0x1
+ // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+ // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
+ // .. .. reg_ddrc_rank1_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reg_ddrc_rank2_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+ // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank2_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+ // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+ // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+ // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+ // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. refresh_timer0_start_value_x32 = 0x0
+ // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
+ // .. .. refresh_timer1_start_value_x32 = 0x8
+ // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_2t_delay = 0x0
+ // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. .. reg_ddrc_dis_pre_bypass = 0x0
+ // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. START: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+ // .. .. FINISH: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xa1
+ // .. .. ==> 0XF800612C[19:10] = 0x000000A1U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xa0
+ // .. .. ==> 0XF8006130[19:10] = 0x000000A0U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x7
+ // .. .. ==> 0XF8006134[9:0] = 0x00000007U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xad
+ // .. .. ==> 0XF8006134[19:10] = 0x000000ADU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x7
+ // .. .. ==> 0XF8006138[9:0] = 0x00000007U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xad
+ // .. .. ==> 0XF8006138[19:10] = 0x000000ADU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
+ // .. .. ==> 0XF8006154[9:0] = 0x0000007CU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
+ // .. .. ==> 0XF8006158[9:0] = 0x0000007CU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x87
+ // .. .. ==> 0XF800615C[9:0] = 0x00000087U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x87
+ // .. .. ==> 0XF8006160[9:0] = 0x00000087U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf6
+ // .. .. ==> 0XF8006168[10:0] = 0x000000F6U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
+ // .. .. ==> 0XF800616C[10:0] = 0x000000F5U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x102
+ // .. .. ==> 0XF8006170[10:0] = 0x00000102U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x102
+ // .. .. ==> 0XF8006174[10:0] = 0x00000102U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xbc
+ // .. .. ==> 0XF800617C[9:0] = 0x000000BCU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xbc
+ // .. .. ==> 0XF8006180[9:0] = 0x000000BCU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc7
+ // .. .. ==> 0XF8006184[9:0] = 0x000000C7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc7
+ // .. .. ==> 0XF8006188[9:0] = 0x000000C7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U),
+ // .. .. reg_phy_loopback = 0x0
+ // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+ // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_use_rank0_delays = 0x1
+ // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_phy_int_lpbk = 0x0
+ // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_per_bank_refresh = 0x0
+ // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x1
+ // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_SEL = 0x4
+ // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
+ // .. VREF_EXT_EN = 0x0
+ // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000700[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000700[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000700[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000704[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000704[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000708[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800070C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000710[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000714[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000718[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800071C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000720[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000724[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000724[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF8000728[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000728[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000728[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF800072C[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800072C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800072C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF8000730[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000730[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000730[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF8000734[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000734[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000734[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF8000738[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000738[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000738[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800073C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800073C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800073C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800073C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF800073C[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800073C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800073C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000740[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000744[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000748[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800074C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000750[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000754[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000758[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800075C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000760[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000764[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000768[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800076C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000770[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000774[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000778[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800077C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000780[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000784[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000788[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800078C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000790[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000794[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000798[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800079C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007A0[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007A4[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007A8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007AC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007B0[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007B4[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007B8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007BC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007BC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007BC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007BC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007BC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007BC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007CC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007CC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO1_CD_SEL = 58
+ // .. ==> 0XF8000834[21:16] = 0x0000003AU
+ // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. IRMODE = 0x0
+ // .. ==> 0XE0001004[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. UCLKEN = 0x0
+ // .. ==> 0XE0001004[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: TPIU WIDTH IN CASE OF EMIO
+ // .. .. START: TRACE LOCK ACCESS REGISTER
+ // .. .. a = 0XC5ACCE55
+ // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+ // .. .. START: TRACE CURRENT PORT SIZE
+ // .. .. a = 2
+ // .. .. ==> 0XF8803004[31:0] = 0x00000002U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U),
+ // .. .. FINISH: TRACE CURRENT PORT SIZE
+ // .. .. START: TRACE LOCK ACCESS REGISTER
+ // .. .. a = 0X0
+ // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+ // .. FINISH: TPIU WIDTH IN CASE OF EMIO
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. DIRECTION_0 = 0x80
+ // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. OP_ENABLE_0 = 0x80
+ // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
+ // .. .. .. START: USB1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB1 RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. .. START: ENET0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET0 RESET
+ // .. .. .. START: ENET1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET1 RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. .. START: I2C0 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C0 RESET
+ // .. .. .. START: I2C1 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C1 RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_INP_ICT_EN_0 = 3
+ // .. ==> 0XF8000900[1:0] = 0x00000003U
+ // .. ==> MASK : 0x00000003U VAL : 0x00000003U
+ // .. USER_INP_ICT_EN_1 = 3
+ // .. ==> 0XF8000900[3:2] = 0x00000003U
+ // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: TPIU WIDTH IN CASE OF EMIO
+ // .. .. START: TRACE LOCK ACCESS REGISTER
+ // .. .. a = 0XC5ACCE55
+ // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+ // .. .. START: TRACE CURRENT PORT SIZE
+ // .. .. a = 2
+ // .. .. ==> 0XF8803004[31:0] = 0x00000002U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U),
+ // .. .. FINISH: TRACE CURRENT PORT SIZE
+ // .. .. START: TRACE LOCK ACCESS REGISTER
+ // .. .. a = 0X0
+ // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+ // .. FINISH: TPIU WIDTH IN CASE OF EMIO
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_1_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+ char* err_msg = "";
+ switch (key) {
+ case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
+ case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
+ case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
+ case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
+ case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
+ case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
+ default: err_msg = "Undefined error status"; break;
+ }
+
+ return err_msg;
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+ // Read PS version from MCTRL register [31:28]
+ unsigned long mask = 0xF0000000;
+ unsigned long *addr = (unsigned long*) 0XF8007080;
+ unsigned long ps_version = (*addr & mask) >> 28;
+ return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
+ unsigned long *addr = (unsigned long*) add;
+ *addr = ( val & mask ) | ( *addr & ~mask);
+ //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+ volatile unsigned long *addr = (volatile unsigned long*) add;
+ int i = 0;
+ while (!(*addr & mask)) {
+ if (i == PS7_MASK_POLL_TIME) {
+ return -1;
+ }
+ i++;
+ }
+ return 1;
+ //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+ unsigned long *addr = (unsigned long*) add;
+ unsigned long val = (*addr & mask);
+ //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+ return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init)
+{
+ unsigned long *ptr = ps7_config_init;
+
+ unsigned long opcode; // current instruction ..
+ unsigned long args[16]; // no opcode has so many args ...
+ int numargs; // number of arguments of this instruction
+ int j; // general purpose index
+
+ volatile unsigned long *addr; // some variable to make code readable
+ unsigned long val,mask; // some variable to make code readable
+
+ int finish = -1 ; // loop while this is negative !
+ int i = 0; // Timeout variable
+
+ while( finish < 0 ) {
+ numargs = ptr[0] & 0xF;
+ opcode = ptr[0] >> 4;
+
+ for( j = 0 ; j < numargs ; j ++ )
+ args[j] = ptr[j+1];
+ ptr += numargs + 1;
+
+
+ switch ( opcode ) {
+
+ case OPCODE_EXIT:
+ finish = PS7_INIT_SUCCESS;
+ break;
+
+ case OPCODE_CLEAR:
+ addr = (unsigned long*) args[0];
+ *addr = 0;
+ break;
+
+ case OPCODE_WRITE:
+ addr = (unsigned long*) args[0];
+ val = args[1];
+ *addr = val;
+ break;
+
+ case OPCODE_MASKWRITE:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ val = args[2];
+ *addr = ( val & mask ) | ( *addr & ~mask);
+ break;
+
+ case OPCODE_MASKPOLL:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ i = 0;
+ while (!(*addr & mask)) {
+ if (i == PS7_MASK_POLL_TIME) {
+ finish = PS7_INIT_TIMEOUT;
+ break;
+ }
+ i++;
+ }
+ break;
+ case OPCODE_MASKDELAY:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ int delay = get_number_of_cycles_for_delay(mask);
+ perf_reset_and_start_timer();
+ while ((*addr < delay)) {
+ }
+ break;
+ default:
+ finish = PS7_INIT_CORRUPT;
+ break;
+ }
+ }
+ return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config (ps7_post_config_1_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config (ps7_post_config_2_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else {
+ ret = ps7_config (ps7_post_config_3_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config (ps7_debug_1_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config (ps7_debug_2_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else {
+ ret = ps7_config (ps7_debug_3_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_init()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret;
+ //int pcw_ver = 0;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ps7_mio_init_data = ps7_mio_init_data_1_0;
+ ps7_pll_init_data = ps7_pll_init_data_1_0;
+ ps7_clock_init_data = ps7_clock_init_data_1_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+ //pcw_ver = 1;
+
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ps7_mio_init_data = ps7_mio_init_data_2_0;
+ ps7_pll_init_data = ps7_pll_init_data_2_0;
+ ps7_clock_init_data = ps7_clock_init_data_2_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+ //pcw_ver = 2;
+
+ } else {
+ ps7_mio_init_data = ps7_mio_init_data_3_0;
+ ps7_pll_init_data = ps7_pll_init_data_3_0;
+ ps7_clock_init_data = ps7_clock_init_data_3_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+ //pcw_ver = 3;
+ }
+
+ // MIO init
+ ret = ps7_config (ps7_mio_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // PLL init
+ ret = ps7_config (ps7_pll_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // Clock init
+ ret = ps7_config (ps7_clock_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // DDR init
+ ret = ps7_config (ps7_ddr_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+ // Peripherals init
+ ret = ps7_config (ps7_peripherals_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+ return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+ (1 << 3) | // Auto-increment
+ (0 << 8) // Pre-scale
+ );
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+ perf_disable_clock();
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay)
+{
+ // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+ return (APU_FREQ*delay/(2*1000));
+
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer()
+{
+ perf_reset_clock();
+ perf_start_clock();
+}
+
+
+
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h
new file mode 100644
index 0000000..df5205e
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h
@@ -0,0 +1,130 @@
+
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License along
+* with this program; if not, see <http://www.gnu.org/licenses/>
+*
+*
+*******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long * ps7_ddr_init_data;
+extern unsigned long * ps7_mio_init_data;
+extern unsigned long * ps7_pll_init_data;
+extern unsigned long * ps7_clock_init_data;
+extern unsigned long * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT 0U
+#define OPCODE_CLEAR 1U
+#define OPCODE_WRITE 2U
+#define OPCODE_MASKWRITE 3U
+#define OPCODE_MASKPOLL 4U
+#define OPCODE_MASKDELAY 5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
+#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes of PS7_Init */
+#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
+#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ 666666687
+#define DDR_FREQ 533333374
+#define DCI_FREQ 10158731
+#define QSPI_FREQ 200000000
+#define SMC_FREQ 10000000
+#define ENET0_FREQ 125000000
+#define ENET1_FREQ 10000000
+#define USB0_FREQ 60000000
+#define USB1_FREQ 60000000
+#define SDIO_FREQ 50000000
+#define UART_FREQ 50000000
+#define SPI_FREQ 10000000
+#define I2C_FREQ 111111115
+#define WDT_FREQ 111111115
+#define TTC_FREQ 50000000
+#define CAN_FREQ 10000000
+#define PCAP_FREQ 200000000
+#define TPIU_FREQ 200000000
+#define FPGA0_FREQ 100000000
+#define FPGA1_FREQ 100000000
+#define FPGA2_FREQ 33333336
+#define FPGA3_FREQ 50000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer();
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif
+
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/pmu-firmware/pmu-firmware_2018.1.bb b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/pmu-firmware/pmu-firmware_2018.1.bb
new file mode 100644
index 0000000..e54e103
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/pmu-firmware/pmu-firmware_2018.1.bb
@@ -0,0 +1,99 @@
+SUMMARY = "Firmware for the PMU on the ZynqMP Programmable Silicon"
+HOMEPAGE = "https://github.com/Xilinx/embeddedsw"
+SECTION = "bsp"
+
+INHIBIT_DEFAULT_DEPS = "1"
+DEPENDS = "virtual/${TARGET_PREFIX}gcc newlib libgloss libgcc"
+
+# force this recipe to provide a target virtual/pmu-firmware. this is applied
+# after any class extender mapping and results in this recipe always providing
+# 'virtual/pmu-firmware'.
+python append_target_provides () {
+ d.appendVar("PROVIDES", " virtual/pmu-firmware")
+}
+addhandler append_target_provides
+append_target_provides[eventmask] = "bb.event.RecipeParsed"
+
+# This source links in a number of components with differing licenses, and some
+# licenses are not Open Source compatible. Additionally the pmu-firmware source
+# itself is licensed under a modified MIT license which restricts use to Xilinx
+# devices only.
+LICENSE = "Proprietary"
+LIC_FILES_CHKSUM = "file://../../../../license.txt;md5=04841c5ad8409b474da7180de5391926"
+
+inherit deploy
+
+XILINX_RELEASE_VERSION = "v2018.1"
+SRCREV = "aaa566bc3fa19255de4d434ebfa57ae3a9d261b2"
+PV = "${XILINX_RELEASE_VERSION}+git${SRCPV}"
+
+SRC_URI = "git://github.com/Xilinx/embeddedsw.git;protocol=https;nobranch=1"
+
+COMPATIBLE_HOST = "microblaze.*-elf"
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE_zynqmp = "zynqmp"
+
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+
+S = "${WORKDIR}/git/lib/sw_apps/zynqmp_pmufw/src"
+
+# The makefile does not handle parallelization
+PARALLEL_MAKE = ""
+
+do_configure() {
+ # manually do the copy_bsp step first, so as to be able to fix up use of
+ # mb-* commands
+ ${S}/../misc/copy_bsp.sh
+}
+
+COMPILER = "${CC}"
+COMPILER_FLAGS = "-O2 -c"
+EXTRA_COMPILER_FLAGS = "-g -Wall -Wextra -Os -flto -ffat-lto-objects"
+ARCHIVER = "${AR}"
+
+# HACK: fix the dirty bug where xilsecure wants to call this PSVersion
+# function, which is not implemented for microblaze. The symbols never make it
+# into the final elf as the xilsecure function that uses it is not called in
+# pmufw.
+EXTRA_COMPILER_FLAGS_append = " -DXGetPSVersion_Info=atexit"
+
+BSP_DIR ?= "${S}/../misc/zynqmp_pmufw_bsp"
+BSP_TARGETS_DIR ?= "${BSP_DIR}/psu_pmu_0/libsrc"
+
+def bsp_make_vars(d):
+ s = ["COMPILER", "CC", "COMPILER_FLAGS", "EXTRA_COMPILER_FLAGS", "ARCHIVER", "AR", "AS"]
+ return " ".join(["\"%s=%s\"" % (v, d.getVar(v)) for v in s])
+
+do_compile() {
+ # the Makefile in ${S}/../misc/Makefile, does not handle CC, AR, AS, etc
+ # properly. So do its job manually. Preparing the includes first, then libs.
+ for i in $(ls ${BSP_TARGETS_DIR}/*/src/Makefile); do
+ oe_runmake -C $(dirname $i) -s include ${@bsp_make_vars(d)}
+ done
+ for i in $(ls ${BSP_TARGETS_DIR}/*/src/Makefile); do
+ oe_runmake -C $(dirname $i) -s libs ${@bsp_make_vars(d)}
+ done
+
+ # --build-id=none is required due to linker script not defining a location for it.
+ oe_runmake CC="${CC}" CC_FLAGS="-MMD -MP -Wl,--build-id=none"
+}
+
+do_install() {
+ :
+}
+
+PMU_FIRMWARE_BASE_NAME ?= "${BPN}-${PKGE}-${PKGV}-${PKGR}-${MACHINE}-${DATETIME}"
+PMU_FIRMWARE_BASE_NAME[vardepsexclude] = "DATETIME"
+
+do_deploy() {
+ install -Dm 0644 ${B}/executable.elf ${DEPLOYDIR}/${PMU_FIRMWARE_BASE_NAME}.elf
+ ln -sf ${PMU_FIRMWARE_BASE_NAME}.elf ${DEPLOYDIR}/${BPN}-${MACHINE}.elf
+ ln -sf ${BPN}-${MACHINE}.elf ${DEPLOYDIR}/pmu-${MACHINE}.elf
+ ${OBJCOPY} -O binary ${B}/executable.elf ${B}/executable.bin
+ install -m 0644 ${B}/executable.bin ${DEPLOYDIR}/${PMU_FIRMWARE_BASE_NAME}.bin
+ ln -sf ${PMU_FIRMWARE_BASE_NAME}.bin ${DEPLOYDIR}/${BPN}-${MACHINE}.bin
+ ln -sf ${BPN}-${MACHINE}.bin ${DEPLOYDIR}/pmu-${MACHINE}.bin
+}
+addtask deploy before do_build after do_install
+
+BBCLASSEXTEND = "zynqmp-pmu"
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/pmu-firmware/pmu-rom_2018.1.bb b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/pmu-firmware/pmu-rom_2018.1.bb
new file mode 100644
index 0000000..195c630
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/pmu-firmware/pmu-rom_2018.1.bb
@@ -0,0 +1,41 @@
+SUMMARY = "PMU ROM for QEMU"
+DESCRIPTION = "The ZynqMP PMU ROM for QEMU emulation"
+HOMEPAGE = "http://www.xilinx.com"
+SECTION = "bsp"
+
+# The BSP package does not include any license information.
+LICENSE = "Proprietary"
+LICENSE_FLAGS = "xilinx"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/Proprietary;md5=0557f9d92cf58f2ccdd50f62f8ac0b28"
+
+COMPATIBLE_MACHINE = "zcu102-zynqmp"
+
+inherit deploy
+inherit xilinx-fetch-restricted
+
+BSP_NAME = "xilinx-zcu102"
+BSP_FILE = "${BSP_NAME}-v${PV}-final.bsp"
+SRC_URI = "https://www.xilinx.com/member/forms/download/xef.html?filename=${BSP_FILE};downloadfilename=${BSP_FILE}"
+SRC_URI[md5sum] = "cea5f11761e7f38cbfcf0a07a19094e0"
+SRC_URI[sha256sum] = "7ac0ac3a5fb7dd162c0a922c66edb33b5737955ef6570a1a1d3b15b4344f7cc1"
+
+INHIBIT_DEFAULT_DEPS = "1"
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+
+do_compile() {
+ # Extract the rom into workdir
+ tar -xf ${WORKDIR}/${BSP_FILE} ${BSP_NAME}-${PV}/pre-built/linux/images/pmu_rom_qemu_sha3.elf -C ${S}
+ # tar preserves the tree, so use find to get the full path and move to to the root
+ for i in $(find ${S} -type f -name *.elf); do mv $i ${S}/pmu-rom.elf; done
+}
+
+do_install() {
+ :
+}
+
+do_deploy () {
+ install -D ${S}/pmu-rom.elf ${DEPLOYDIR}/pmu-rom.elf
+}
+
+addtask deploy before do_build after do_install
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2018.1.bb b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2018.1.bb
new file mode 100644
index 0000000..0b6ca20
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2018.1.bb
@@ -0,0 +1,48 @@
+SUMMARY = "KC705 Pre-built Bitstream"
+DESCRIPTION = "A Pre-built bitstream for the KC705, which is capable of booting a Linux system."
+HOMEPAGE = "http://www.xilinx.com"
+SECTION = "bsp"
+
+# The BSP package does not include any license information.
+LICENSE = "Proprietary"
+LICENSE_FLAGS = "xilinx"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/Proprietary;md5=0557f9d92cf58f2ccdd50f62f8ac0b28"
+
+COMPATIBLE_MACHINE = "kc705-microblazeel"
+
+inherit deploy
+inherit xilinx-fetch-restricted
+
+BSP_NAME = "xilinx-kc705"
+BSP_FILE = "${BSP_NAME}-v${PV}-final.bsp"
+SRC_URI = "https://www.xilinx.com/member/forms/download/xef.html?filename=${BSP_FILE};downloadfilename=${BSP_FILE}"
+SRC_URI[md5sum] = "53e5e0ad87d0388fe5b11fa5fc029288"
+SRC_URI[sha256sum] = "301f994bd836ad78ebfc92af6c16470b53253121ca31762dc1f770a9ff11dc18"
+
+PROVIDES = "virtual/bitstream"
+
+FILES_${PN} += "/boot/download.bit"
+
+INHIBIT_DEFAULT_DEPS = "1"
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+
+# deps needed to extract content from the .bsp file
+DEPENDS += "tar-native gzip-native"
+
+do_compile() {
+ # Extract the bitstream into workdir
+ tar -xf ${WORKDIR}/${BSP_FILE} ${BSP_NAME}-axi-full-${PV}/pre-built/linux/images/download.bit -C ${S}
+ # move the bit file to ${S}/ as it is in a subdir in the tar file
+ for i in $(find -type f -name download.bit); do mv $i ${S}; done
+}
+
+do_install() {
+ install -D ${S}/download.bit ${D}/boot/download.bit
+}
+
+do_deploy () {
+ install -D ${S}/download.bit ${DEPLOYDIR}/download.bit
+}
+
+addtask deploy before do_build after do_install
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-spl-zynq-init.inc b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-spl-zynq-init.inc
new file mode 100644
index 0000000..9cf09ff
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-spl-zynq-init.inc
@@ -0,0 +1,74 @@
+inherit xilinx-platform-init
+
+FORCE_PLATFORM_INIT[doc] = "This variable is used to force the overriding of all platform init files in u-boot source."
+
+PLATFORM_BOARD_DIR ?= ""
+PLATFORM_BOARD_DIR_zynq = "board/xilinx/zynq"
+PLATFORM_BOARD_DIR_zynqmp = "board/xilinx/zynqmp"
+
+do_zynq_platform_init() {
+ for f in ${PLATFORM_INIT_FILES}; do
+ if [ -d "${S}/${PLATFORM_BOARD_DIR}/custom_hw_platform" ]; then
+ cp ${PLATFORM_INIT_STAGE_DIR}/$f ${S}/${PLATFORM_BOARD_DIR}/custom_hw_platform/
+ else
+ cp ${PLATFORM_INIT_STAGE_DIR}/$f ${S}/${PLATFORM_BOARD_DIR}/
+ fi
+ # Newer u-boot sources use the init files in a sub directory named
+ # based on the name of the device tree. This is not straight forward to
+ # detect. Instead of detecting just overwrite all the platform init
+ # files so that the correct one is always used. This shotgun approach
+ # only works due to this recipe being machine arch specific. Do this
+ # overwrite un-conditionally as there is no guarantees that the chosen
+ # board config does not have the device tree config set.
+ for i in ${S}/${PLATFORM_BOARD_DIR}/*/; do
+ [ -d $i ] && cp ${PLATFORM_INIT_STAGE_DIR}/$f $i
+ done
+ done
+}
+
+python () {
+ # strip the tail _config/_defconfig for better comparison
+ def strip_config_name(c):
+ for i in ["_config", "_defconfig"]:
+ if c.endswith(i):
+ return c[0:len(c) - len(i)]
+ return c
+
+ if d.getVar("SOC_FAMILY") not in ["zynq", "zynqmp"]:
+ # continue on this is not a zynq/zynqmp target
+ return
+
+ # Determine if target machine needs to provide a custom platform init files
+ if d.getVar("SPL_BINARY"):
+ hasconfigs = [strip_config_name(c) for c in (d.getVar("HAS_PLATFORM_INIT") or "").split()]
+ currentconfig = strip_config_name(d.getVar("UBOOT_MACHINE"))
+
+ # only add the dependency if u-boot doesn't already provide the platform init files
+ if (currentconfig not in hasconfigs) or (d.getVar("FORCE_PLATFORM_INIT") == "1"):
+ # force the dependency on a recipe that provides the platform init files
+ d.appendVar("DEPENDS", " virtual/xilinx-platform-init")
+ # setup task to modify platform init after unpack and prepare_recipe_sysroot, and before configure
+ bb.build.addtask("do_zynq_platform_init", "do_configure", "do_unpack do_prepare_recipe_sysroot", d)
+
+ if "boot.bin" not in d.getVar("SPL_BINARY"):
+ # not deploying the boot.bin, just building SPL
+ return
+
+ # assume that U-Boot is to provide the boot.bin if no other provides are selected or U-Boot is selected
+ providesbin = not(d.getVar("PREFERRED_PROVIDER_virtual/boot-bin")) or d.getVar("PREFERRED_PROVIDER_virtual/boot-bin") == d.getVar("PN")
+ if providesbin:
+ # add provides, if U-Boot is set to provide boot.bin
+ d.appendVar("PROVIDES", " virtual/boot-bin")
+ else:
+ # prevent U-Boot from deploying the boot.bin
+ d.setVar("SPL_BINARY", "")
+
+ if providesbin and d.getVar("SOC_FAMILY") in ["zynqmp"]:
+ # depend on the pmu-firmware build
+ d.appendVar("DEPENDS", " virtual/pmu-firmware")
+ # determine the path relative to the source tree
+ relpath = os.path.relpath(d.expand("${DEPLOY_DIR_IMAGE}/pmu-${MACHINE}.bin"), d.getVar("S"))
+ # setup PMU Firmware path via MAKEFLAGS
+ d.appendVar("EXTRA_OEMAKE", " CONFIG_PMUFW_INIT_FILE=\"{0}\"".format(relpath))
+}
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx-dev.bb b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx-dev.bb
new file mode 100644
index 0000000..3e40bfa
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx-dev.bb
@@ -0,0 +1,28 @@
+# This recipe allows for a 'bleeding edge' u-boot-xlnx build.
+# Since this tree is frequently updated, AUTOREV is used to track its contents.
+#
+# To enable this recipe, set the following in your machine or local.conf
+# PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot-xlnx-dev"
+
+UBRANCH ?= "master"
+
+include u-boot-xlnx.inc
+include u-boot-spl-zynq-init.inc
+
+LICENSE = "GPLv2+"
+LIC_FILES_CHKSUM = "file://README;beginline=1;endline=6;md5=157ab8408beab40cd8ce1dc69f702a6c"
+
+SRCREV_DEFAULT = "aebea9d20a5aa32857f320c07ca8f9fd1b3dec1f"
+SRCREV ?= "${@oe.utils.conditional("PREFERRED_PROVIDER_virtual/bootloader", "u-boot-xlnx-dev", "${AUTOREV}", "${SRCREV_DEFAULT}", d)}"
+
+PV = "${UBRANCH}-xilinx-dev+git${SRCPV}"
+
+# Newer versions of u-boot have support for these
+HAS_PLATFORM_INIT ?= " \
+ zynq_microzed_config \
+ zynq_zed_config \
+ zynq_zc702_config \
+ zynq_zc706_config \
+ zynq_zybo_config \
+ "
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx.inc b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx.inc
new file mode 100644
index 0000000..689249f
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx.inc
@@ -0,0 +1,20 @@
+require recipes-bsp/u-boot/u-boot.inc
+
+DEPENDS += "bc-native dtc-native"
+
+XILINX_RELEASE_VERSION ?= ""
+UBOOT_VERSION_EXTENSION ?= "-xilinx-${XILINX_RELEASE_VERSION}"
+PV = "${UBOOT_VERSION}${UBOOT_VERSION_EXTENSION}+git${SRCPV}"
+
+UBOOTURI ?= "git://github.com/Xilinx/u-boot-xlnx.git;protocol=https"
+UBRANCH ?= ""
+UBRANCHARG = "${@['nobranch=1', 'branch=${UBRANCH}'][d.getVar('UBRANCH', True) != '']}"
+
+SRC_URI = "${UBOOTURI};${UBRANCHARG}"
+
+S = "${WORKDIR}/git"
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/u-boot:"
+FILESEXTRAPATHS_prepend := "${THISDIR}/u-boot-xlnx:"
+FILESEXTRAPATHS_prepend := "${@'${THISDIR}/u-boot-xlnx/${XILINX_RELEASE_VERSION}:' if d.getVar('XILINX_RELEASE_VERSION') else ''}"
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2018.1/microblaze-kc705-Convert-microblaze-generic-to-k.patch b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2018.1/microblaze-kc705-Convert-microblaze-generic-to-k.patch
new file mode 100644
index 0000000..ce8771f
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2018.1/microblaze-kc705-Convert-microblaze-generic-to-k.patch
@@ -0,0 +1,1168 @@
+From 539838b4fe4afecd9b6874c5ac397ab7f5b343d4 Mon Sep 17 00:00:00 2001
+From: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Date: Tue, 10 Apr 2018 18:34:45 -0700
+Subject: [PATCH] kc705-microblazeel: Convert microblaze-generic to
+ kc705-microblazeel
+
+This is an update to earlier kc705-trd patch done by Nathan Rossi.
+Starting from v2016.1, KC705 will no longer refer to deprecated KC705
+TRD application.
+
+Change the microblaze-generic board to match the kc705-microblazeel.
+This patch is not intended for upstream and serves as an intermediate
+solution until OF support in upstream u-boot allows for easy support for
+custom microblaze boards.
+
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Not-Upstreamable [meta-xilinx/kc705 specific]
+---
+ arch/microblaze/dts/microblaze-generic.dts | 590 ++++++++++++++++++++++++++++-
+ board/xilinx/microblaze-generic/config.mk | 30 +-
+ configs/microblaze-generic_defconfig | 57 ++-
+ include/configs/microblaze-generic.h | 396 ++++++++-----------
+ 4 files changed, 782 insertions(+), 291 deletions(-)
+
+diff --git a/arch/microblaze/dts/microblaze-generic.dts b/arch/microblaze/dts/microblaze-generic.dts
+index 08a1396..f8e616b 100644
+--- a/arch/microblaze/dts/microblaze-generic.dts
++++ b/arch/microblaze/dts/microblaze-generic.dts
+@@ -1,9 +1,587 @@
+ /dts-v1/;
++
+ / {
+- #address-cells = <1>;
+- #size-cells = <1>;
+- aliases {
+- } ;
++ #address-cells = <0x1>;
++ #size-cells = <0x1>;
++ compatible = "xlnx,microblaze";
++ model = "Xilinx MicroBlaze";
++ hard-reset-gpios = <0x1 0x0 0x1>;
++
++ cpus {
++ #address-cells = <0x1>;
++ #cpus = <0x1>;
++ #size-cells = <0x0>;
++
++ cpu@0 {
++ bus-handle = <0x2>;
++ clock-frequency = <0xbebc200>;
++ clocks = <0x3>;
++ compatible = "xlnx,microblaze-10.0";
++ d-cache-baseaddr = <0x80000000>;
++ d-cache-highaddr = <0xbfffffff>;
++ d-cache-line-size = <0x20>;
++ d-cache-size = <0x4000>;
++ device_type = "cpu";
++ i-cache-baseaddr = <0x80000000>;
++ i-cache-highaddr = <0xbfffffff>;
++ i-cache-line-size = <0x10>;
++ i-cache-size = <0x4000>;
++ interrupt-handle = <0x4>;
++ model = "microblaze,10.0";
++ timebase-frequency = <0xbebc200>;
++ xlnx,addr-size = <0x20>;
++ xlnx,addr-tag-bits = <0x10>;
++ xlnx,allow-dcache-wr = <0x1>;
++ xlnx,allow-icache-wr = <0x1>;
++ xlnx,area-optimized = <0x0>;
++ xlnx,async-interrupt = <0x1>;
++ xlnx,async-wakeup = <0x3>;
++ xlnx,avoid-primitives = <0x0>;
++ xlnx,base-vectors = <0x0>;
++ xlnx,branch-target-cache-size = <0x0>;
++ xlnx,cache-byte-size = <0x4000>;
++ xlnx,d-axi = <0x1>;
++ xlnx,d-lmb = <0x1>;
++ xlnx,d-lmb-mon = <0x0>;
++ xlnx,daddr-size = <0x20>;
++ xlnx,data-size = <0x20>;
++ xlnx,dc-axi-mon = <0x0>;
++ xlnx,dcache-addr-tag = <0x10>;
++ xlnx,dcache-always-used = <0x1>;
++ xlnx,dcache-byte-size = <0x4000>;
++ xlnx,dcache-data-width = <0x0>;
++ xlnx,dcache-force-tag-lutram = <0x0>;
++ xlnx,dcache-line-len = <0x8>;
++ xlnx,dcache-use-writeback = <0x0>;
++ xlnx,dcache-victims = <0x0>;
++ xlnx,debug-counter-width = <0x20>;
++ xlnx,debug-enabled = <0x1>;
++ xlnx,debug-event-counters = <0x5>;
++ xlnx,debug-external-trace = <0x0>;
++ xlnx,debug-interface = <0x0>;
++ xlnx,debug-latency-counters = <0x1>;
++ xlnx,debug-profile-size = <0x0>;
++ xlnx,debug-trace-async-reset = <0x0>;
++ xlnx,debug-trace-size = <0x2000>;
++ xlnx,div-zero-exception = <0x1>;
++ xlnx,dp-axi-mon = <0x0>;
++ xlnx,dynamic-bus-sizing = <0x0>;
++ xlnx,ecc-use-ce-exception = <0x0>;
++ xlnx,edge-is-positive = <0x1>;
++ xlnx,enable-discrete-ports = <0x0>;
++ xlnx,endianness = <0x1>;
++ xlnx,fault-tolerant = <0x0>;
++ xlnx,fpu-exception = <0x0>;
++ xlnx,freq = <0xbebc200>;
++ xlnx,fsl-exception = <0x0>;
++ xlnx,fsl-links = <0x0>;
++ xlnx,i-axi = <0x0>;
++ xlnx,i-lmb = <0x1>;
++ xlnx,i-lmb-mon = <0x0>;
++ xlnx,iaddr-size = <0x20>;
++ xlnx,ic-axi-mon = <0x0>;
++ xlnx,icache-always-used = <0x1>;
++ xlnx,icache-data-width = <0x0>;
++ xlnx,icache-force-tag-lutram = <0x0>;
++ xlnx,icache-line-len = <0x4>;
++ xlnx,icache-streams = <0x1>;
++ xlnx,icache-victims = <0x8>;
++ xlnx,ill-opcode-exception = <0x1>;
++ xlnx,imprecise-exceptions = <0x0>;
++ xlnx,instr-size = <0x20>;
++ xlnx,interconnect = <0x2>;
++ xlnx,interrupt-is-edge = <0x0>;
++ xlnx,interrupt-mon = <0x0>;
++ xlnx,ip-axi-mon = <0x0>;
++ xlnx,lockstep-master = <0x0>;
++ xlnx,lockstep-select = <0x0>;
++ xlnx,lockstep-slave = <0x0>;
++ xlnx,mmu-dtlb-size = <0x4>;
++ xlnx,mmu-itlb-size = <0x2>;
++ xlnx,mmu-privileged-instr = <0x0>;
++ xlnx,mmu-tlb-access = <0x3>;
++ xlnx,mmu-zones = <0x2>;
++ xlnx,num-sync-ff-clk = <0x2>;
++ xlnx,num-sync-ff-clk-debug = <0x2>;
++ xlnx,num-sync-ff-clk-irq = <0x1>;
++ xlnx,num-sync-ff-dbg-clk = <0x1>;
++ xlnx,num-sync-ff-dbg-trace-clk = <0x2>;
++ xlnx,number-of-pc-brk = <0x1>;
++ xlnx,number-of-rd-addr-brk = <0x0>;
++ xlnx,number-of-wr-addr-brk = <0x0>;
++ xlnx,opcode-0x0-illegal = <0x1>;
++ xlnx,optimization = <0x0>;
++ xlnx,pc-width = <0x20>;
++ xlnx,piaddr-size = <0x20>;
++ xlnx,pvr = <0x2>;
++ xlnx,pvr-user1 = <0x0>;
++ xlnx,pvr-user2 = <0x0>;
++ xlnx,reset-msr = <0x0>;
++ xlnx,reset-msr-bip = <0x0>;
++ xlnx,reset-msr-dce = <0x0>;
++ xlnx,reset-msr-ee = <0x0>;
++ xlnx,reset-msr-eip = <0x0>;
++ xlnx,reset-msr-ice = <0x0>;
++ xlnx,reset-msr-ie = <0x0>;
++ xlnx,sco = <0x0>;
++ xlnx,trace = <0x0>;
++ xlnx,unaligned-exceptions = <0x1>;
++ xlnx,use-barrel = <0x1>;
++ xlnx,use-branch-target-cache = <0x0>;
++ xlnx,use-config-reset = <0x0>;
++ xlnx,use-dcache = <0x1>;
++ xlnx,use-div = <0x1>;
++ xlnx,use-ext-brk = <0x0>;
++ xlnx,use-ext-nm-brk = <0x0>;
++ xlnx,use-extended-fsl-instr = <0x0>;
++ xlnx,use-fpu = <0x0>;
++ xlnx,use-hw-mul = <0x2>;
++ xlnx,use-icache = <0x1>;
++ xlnx,use-interrupt = <0x2>;
++ xlnx,use-mmu = <0x3>;
++ xlnx,use-msr-instr = <0x1>;
++ xlnx,use-non-secure = <0x0>;
++ xlnx,use-pcmp-instr = <0x1>;
++ xlnx,use-reorder-instr = <0x1>;
++ xlnx,use-stack-protection = <0x0>;
++ };
++ };
++
++ clocks {
++ #address-cells = <0x1>;
++ #size-cells = <0x0>;
++
++ clk_cpu@0 {
++ #clock-cells = <0x0>;
++ clock-frequency = <0xbebc200>;
++ clock-output-names = "clk_cpu";
++ compatible = "fixed-clock";
++ reg = <0x0>;
++ linux,phandle = <0x3>;
++ phandle = <0x3>;
++ };
++
++ clk_bus_0@1 {
++ #clock-cells = <0x0>;
++ clock-frequency = <0xbebc200>;
++ clock-output-names = "clk_bus_0";
++ compatible = "fixed-clock";
++ reg = <0x1>;
++ linux,phandle = <0x8>;
++ phandle = <0x8>;
++ };
++ };
++
++ amba_pl {
++ #address-cells = <0x1>;
++ #size-cells = <0x1>;
++ compatible = "simple-bus";
++ ranges;
++ linux,phandle = <0x2>;
++ phandle = <0x2>;
++
++ ethernet@40c00000 {
++ axistream-connected = <0x5>;
++ axistream-control-connected = <0x5>;
++ clock-frequency = <0x5f5e100>;
++ compatible = "xlnx,axi-ethernet-1.00.a";
++ device_type = "network";
++ interrupt-names = "interrupt";
++ interrupt-parent = <0x4>;
++ interrupts = <0x4 0x2>;
++ phy-mode = "gmii";
++ reg = <0x40c00000 0x40000>;
++ xlnx = <0x0>;
++ xlnx,axiliteclkrate = <0x0>;
++ xlnx,axisclkrate = <0x0>;
++ xlnx,clockselection = <0x0>;
++ xlnx,enableasyncsgmii = <0x0>;
++ xlnx,gt-type = <0x0>;
++ xlnx,gtinex = <0x0>;
++ xlnx,gtlocation = <0x0>;
++ xlnx,gtrefclksrc = <0x0>;
++ xlnx,include-dre;
++ xlnx,instantiatebitslice0 = <0x0>;
++ xlnx,phy-type = <0x1>;
++ xlnx,phyaddr = <0x1>;
++ xlnx,rable = <0x0>;
++ xlnx,rxcsum = <0x0>;
++ xlnx,rxlane0-placement = <0x0>;
++ xlnx,rxlane1-placement = <0x0>;
++ xlnx,rxmem = <0x1000>;
++ xlnx,rxnibblebitslice0used = <0x0>;
++ xlnx,tx-in-upper-nibble = <0x1>;
++ xlnx,txcsum = <0x0>;
++ xlnx,txlane0-placement = <0x0>;
++ xlnx,txlane1-placement = <0x0>;
++ phy-handle = <0x6>;
++ local-mac-address = [00 0a 35 00 22 01];
++ linux,phandle = <0x7>;
++ phandle = <0x7>;
++
++ mdio {
++ #address-cells = <0x1>;
++ #size-cells = <0x0>;
++
++ phy@7 {
++ device_type = "ethernet-phy";
++ reg = <0x7>;
++ linux,phandle = <0x6>;
++ phandle = <0x6>;
++ };
++ };
++ };
++
++ dma@41e00000 {
++ #dma-cells = <0x1>;
++ axistream-connected = <0x7>;
++ axistream-control-connected = <0x7>;
++ clock-frequency = <0xbebc200>;
++ clock-names = "s_axi_lite_aclk";
++ clocks = <0x8>;
++ compatible = "xlnx,eth-dma";
++ interrupt-names = "mm2s_introut", "s2mm_introut";
++ interrupt-parent = <0x4>;
++ interrupts = <0x3 0x2 0x2 0x2>;
++ reg = <0x41e00000 0x10000>;
++ xlnx,include-dre;
++ linux,phandle = <0x5>;
++ phandle = <0x5>;
++ };
++
++ timer@41c00000 {
++ clock-frequency = <0xbebc200>;
++ clocks = <0x8>;
++ compatible = "xlnx,xps-timer-1.00.a";
++ interrupt-names = "interrupt";
++ interrupt-parent = <0x4>;
++ interrupts = <0x5 0x2>;
++ reg = <0x41c00000 0x10000>;
++ xlnx,count-width = <0x20>;
++ xlnx,gen0-assert = <0x1>;
++ xlnx,gen1-assert = <0x1>;
++ xlnx,one-timer-only = <0x0>;
++ xlnx,trig0-assert = <0x1>;
++ xlnx,trig1-assert = <0x1>;
++ };
++
++ gpio@40010000 {
++ #gpio-cells = <0x2>;
++ clock-frequency = <0xbebc200>;
++ clock-names = "s_axi_aclk";
++ clocks = <0x8>;
++ compatible = "xlnx,xps-gpio-1.00.a";
++ gpio-controller;
++ reg = <0x40010000 0x10000>;
++ xlnx,all-inputs = <0x1>;
++ xlnx,all-inputs-2 = <0x0>;
++ xlnx,all-outputs = <0x0>;
++ xlnx,all-outputs-2 = <0x0>;
++ xlnx,dout-default = <0x0>;
++ xlnx,dout-default-2 = <0x0>;
++ xlnx,gpio-width = <0x1>;
++ xlnx,gpio2-width = <0x20>;
++ xlnx,interrupt-present = <0x0>;
++ xlnx,is-dual = <0x0>;
++ xlnx,tri-default = <0xffffffff>;
++ xlnx,tri-default-2 = <0xffffffff>;
++ };
++
++ gpio@40020000 {
++ #gpio-cells = <0x2>;
++ clock-frequency = <0xbebc200>;
++ clock-names = "s_axi_aclk";
++ clocks = <0x8>;
++ compatible = "xlnx,xps-gpio-1.00.a";
++ gpio-controller;
++ reg = <0x40020000 0x10000>;
++ xlnx,all-inputs = <0x1>;
++ xlnx,all-inputs-2 = <0x0>;
++ xlnx,all-outputs = <0x0>;
++ xlnx,all-outputs-2 = <0x0>;
++ xlnx,dout-default = <0x0>;
++ xlnx,dout-default-2 = <0x0>;
++ xlnx,gpio-width = <0x4>;
++ xlnx,gpio2-width = <0x20>;
++ xlnx,interrupt-present = <0x0>;
++ xlnx,is-dual = <0x0>;
++ xlnx,tri-default = <0xffffffff>;
++ xlnx,tri-default-2 = <0xffffffff>;
++ };
++
++ i2c@40800000 {
++ #address-cells = <0x1>;
++ #size-cells = <0x0>;
++ clock-frequency = <0xbebc200>;
++ clocks = <0x8>;
++ compatible = "xlnx,xps-iic-2.00.a";
++ interrupt-names = "iic2intc_irpt";
++ interrupt-parent = <0x4>;
++ interrupts = <0x1 0x2>;
++ reg = <0x40800000 0x10000>;
++
++ i2cswitch@74 {
++ compatible = "nxp,pca9548";
++ #address-cells = <0x1>;
++ #size-cells = <0x0>;
++ reg = <0x74>;
++
++ i2c@0 {
++ #address-cells = <0x1>;
++ #size-cells = <0x0>;
++ reg = <0x0>;
++
++ clock-generator@5d {
++ #clock-cells = <0x0>;
++ compatible = "silabs,si570";
++ temperature-stability = <0x32>;
++ reg = <0x5d>;
++ factory-fout = <0x9502f90>;
++ clock-frequency = <0x8d9ee20>;
++ };
++ };
++
++ i2c@3 {
++ #address-cells = <0x1>;
++ #size-cells = <0x0>;
++ reg = <0x3>;
++
++ eeprom@54 {
++ compatible = "at,24c08";
++ reg = <0x54>;
++ };
++ };
++ };
++ };
++
++ gpio@40030000 {
++ #gpio-cells = <0x2>;
++ clock-frequency = <0xbebc200>;
++ clock-names = "s_axi_aclk";
++ clocks = <0x8>;
++ compatible = "xlnx,xps-gpio-1.00.a";
++ gpio-controller;
++ reg = <0x40030000 0x10000>;
++ xlnx,all-inputs = <0x0>;
++ xlnx,all-inputs-2 = <0x0>;
++ xlnx,all-outputs = <0x1>;
++ xlnx,all-outputs-2 = <0x0>;
++ xlnx,dout-default = <0x0>;
++ xlnx,dout-default-2 = <0x0>;
++ xlnx,gpio-width = <0x8>;
++ xlnx,gpio2-width = <0x20>;
++ xlnx,interrupt-present = <0x0>;
++ xlnx,is-dual = <0x0>;
++ xlnx,tri-default = <0xffffffff>;
++ xlnx,tri-default-2 = <0xffffffff>;
++ };
++
++ flash@60000000 {
++ bank-width = <0x2>;
++ compatible = "cfi-flash";
++ reg = <0x60000000 0x8000000>;
++ xlnx,axi-clk-period-ps = <0x1388>;
++ xlnx,include-datawidth-matching-0 = <0x1>;
++ xlnx,include-datawidth-matching-1 = <0x1>;
++ xlnx,include-datawidth-matching-2 = <0x1>;
++ xlnx,include-datawidth-matching-3 = <0x1>;
++ xlnx,include-negedge-ioregs = <0x0>;
++ xlnx,lflash-period-ps = <0x1388>;
++ xlnx,linear-flash-sync-burst = <0x0>;
++ xlnx,max-mem-width = <0x10>;
++ xlnx,mem-a-lsb = <0x0>;
++ xlnx,mem-a-msb = <0x1f>;
++ xlnx,mem0-type = <0x2>;
++ xlnx,mem0-width = <0x10>;
++ xlnx,mem1-type = <0x0>;
++ xlnx,mem1-width = <0x10>;
++ xlnx,mem2-type = <0x0>;
++ xlnx,mem2-width = <0x10>;
++ xlnx,mem3-type = <0x0>;
++ xlnx,mem3-width = <0x10>;
++ xlnx,num-banks-mem = <0x1>;
++ xlnx,page-size = <0x10>;
++ xlnx,parity-type-mem-0 = <0x0>;
++ xlnx,parity-type-mem-1 = <0x0>;
++ xlnx,parity-type-mem-2 = <0x0>;
++ xlnx,parity-type-mem-3 = <0x0>;
++ xlnx,port-diff = <0x0>;
++ xlnx,s-axi-en-reg = <0x0>;
++ xlnx,s-axi-mem-addr-width = <0x20>;
++ xlnx,s-axi-mem-data-width = <0x20>;
++ xlnx,s-axi-mem-id-width = <0x1>;
++ xlnx,s-axi-reg-addr-width = <0x5>;
++ xlnx,s-axi-reg-data-width = <0x20>;
++ xlnx,synch-pipedelay-0 = <0x1>;
++ xlnx,synch-pipedelay-1 = <0x1>;
++ xlnx,synch-pipedelay-2 = <0x1>;
++ xlnx,synch-pipedelay-3 = <0x1>;
++ xlnx,tavdv-ps-mem-0 = <0x1fbd0>;
++ xlnx,tavdv-ps-mem-1 = <0x3a98>;
++ xlnx,tavdv-ps-mem-2 = <0x3a98>;
++ xlnx,tavdv-ps-mem-3 = <0x3a98>;
++ xlnx,tcedv-ps-mem-0 = <0x1fbd0>;
++ xlnx,tcedv-ps-mem-1 = <0x3a98>;
++ xlnx,tcedv-ps-mem-2 = <0x3a98>;
++ xlnx,tcedv-ps-mem-3 = <0x3a98>;
++ xlnx,thzce-ps-mem-0 = <0x88b8>;
++ xlnx,thzce-ps-mem-1 = <0x1b58>;
++ xlnx,thzce-ps-mem-2 = <0x1b58>;
++ xlnx,thzce-ps-mem-3 = <0x1b58>;
++ xlnx,thzoe-ps-mem-0 = <0x1b58>;
++ xlnx,thzoe-ps-mem-1 = <0x1b58>;
++ xlnx,thzoe-ps-mem-2 = <0x1b58>;
++ xlnx,thzoe-ps-mem-3 = <0x1b58>;
++ xlnx,tlzwe-ps-mem-0 = <0xc350>;
++ xlnx,tlzwe-ps-mem-1 = <0x0>;
++ xlnx,tlzwe-ps-mem-2 = <0x0>;
++ xlnx,tlzwe-ps-mem-3 = <0x0>;
++ xlnx,tpacc-ps-flash-0 = <0x61a8>;
++ xlnx,tpacc-ps-flash-1 = <0x61a8>;
++ xlnx,tpacc-ps-flash-2 = <0x61a8>;
++ xlnx,tpacc-ps-flash-3 = <0x61a8>;
++ xlnx,twc-ps-mem-0 = <0x11170>;
++ xlnx,twc-ps-mem-1 = <0x3a98>;
++ xlnx,twc-ps-mem-2 = <0x3a98>;
++ xlnx,twc-ps-mem-3 = <0x3a98>;
++ xlnx,twp-ps-mem-0 = <0x13880>;
++ xlnx,twp-ps-mem-1 = <0x2ee0>;
++ xlnx,twp-ps-mem-2 = <0x2ee0>;
++ xlnx,twp-ps-mem-3 = <0x2ee0>;
++ xlnx,twph-ps-mem-0 = <0x13880>;
++ xlnx,twph-ps-mem-1 = <0x2ee0>;
++ xlnx,twph-ps-mem-2 = <0x2ee0>;
++ xlnx,twph-ps-mem-3 = <0x2ee0>;
++ xlnx,use-startup = <0x0>;
++ xlnx,use-startup-int = <0x0>;
++ xlnx,wr-rec-time-mem-0 = <0x186a0>;
++ xlnx,wr-rec-time-mem-1 = <0x6978>;
++ xlnx,wr-rec-time-mem-2 = <0x6978>;
++ xlnx,wr-rec-time-mem-3 = <0x6978>;
++ #address-cells = <0x1>;
++ #size-cells = <0x1>;
++
++ partition@0x00000000 {
++ label = "fpga";
++ reg = <0x0 0xb00000>;
++ };
++
++ partition@0x00b00000 {
++ label = "boot";
++ reg = <0xb00000 0x80000>;
++ };
++
++ partition@0x00b80000 {
++ label = "bootenv";
++ reg = <0xb80000 0x20000>;
++ };
++
++ partition@0x00ba0000 {
++ label = "kernel";
++ reg = <0xba0000 0xc00000>;
++ };
++
++ partition@0x017a0000 {
++ label = "spare";
++ reg = <0x17a0000 0x0>;
++ };
++ };
++
++ interrupt-controller@41200000 {
++ #interrupt-cells = <0x2>;
++ compatible = "xlnx,xps-intc-1.00.a";
++ interrupt-controller;
++ reg = <0x41200000 0x10000>;
++ xlnx,kind-of-intr = <0x0>;
++ xlnx,num-intr-inputs = <0x6>;
++ linux,phandle = <0x4>;
++ phandle = <0x4>;
++ };
++
++ gpio@40040000 {
++ #gpio-cells = <0x2>;
++ clock-frequency = <0xbebc200>;
++ clock-names = "s_axi_aclk";
++ clocks = <0x8>;
++ compatible = "xlnx,xps-gpio-1.00.a";
++ gpio-controller;
++ reg = <0x40040000 0x10000>;
++ xlnx,all-inputs = <0x1>;
++ xlnx,all-inputs-2 = <0x0>;
++ xlnx,all-outputs = <0x0>;
++ xlnx,all-outputs-2 = <0x0>;
++ xlnx,dout-default = <0x0>;
++ xlnx,dout-default-2 = <0x0>;
++ xlnx,gpio-width = <0x5>;
++ xlnx,gpio2-width = <0x20>;
++ xlnx,interrupt-present = <0x0>;
++ xlnx,is-dual = <0x0>;
++ xlnx,tri-default = <0xffffffff>;
++ xlnx,tri-default-2 = <0xffffffff>;
++ };
++
++ gpio@40000000 {
++ #gpio-cells = <0x2>;
++ clock-frequency = <0xbebc200>;
++ clock-names = "s_axi_aclk";
++ clocks = <0x8>;
++ compatible = "xlnx,xps-gpio-1.00.a";
++ gpio-controller;
++ reg = <0x40000000 0x10000>;
++ xlnx,all-inputs = <0x0>;
++ xlnx,all-inputs-2 = <0x0>;
++ xlnx,all-outputs = <0x1>;
++ xlnx,all-outputs-2 = <0x0>;
++ xlnx,dout-default = <0x0>;
++ xlnx,dout-default-2 = <0x0>;
++ xlnx,gpio-width = <0x1>;
++ xlnx,gpio2-width = <0x20>;
++ xlnx,interrupt-present = <0x0>;
++ xlnx,is-dual = <0x0>;
++ xlnx,tri-default = <0xffffffff>;
++ xlnx,tri-default-2 = <0xffffffff>;
++ linux,phandle = <0x1>;
++ phandle = <0x1>;
++ };
++
++ serial@44a00000 {
++ clock-frequency = <0xbebc200>;
++ clocks = <0x8>;
++ compatible = "xlnx,xps-uart16550-2.00.a", "ns16550a";
++ current-speed = <0x1c200>;
++ device_type = "serial";
++ interrupt-names = "ip2intc_irpt";
++ interrupt-parent = <0x4>;
++ interrupts = <0x0 0x2>;
++ port-number = <0x0>;
++ reg = <0x44a00000 0x10000>;
++ reg-offset = <0x1000>;
++ reg-shift = <0x2>;
++ xlnx,external-xin-clk-hz = <0x17d7840>;
++ xlnx,external-xin-clk-hz-d = <0x19>;
++ xlnx,has-external-rclk = <0x0>;
++ xlnx,has-external-xin = <0x0>;
++ xlnx,is-a-16550 = <0x1>;
++ xlnx,s-axi-aclk-freq-hz-d = "200.0";
++ xlnx,use-modem-ports = <0x1>;
++ xlnx,use-user-ports = <0x1>;
++ };
++ };
++
+ chosen {
+- } ;
+-} ;
++ bootargs = "console=ttyS0,115200 earlyprintk";
++ stdout-path = "serial0:115200n8";
++ };
++
++ aliases {
++ ethernet0 = "/amba_pl/ethernet@40c00000";
++ i2c0 = "/amba_pl/i2c@40800000";
++ serial0 = "/amba_pl/serial@44a00000";
++ };
++
++ memory {
++ device_type = "memory";
++ reg = <0x80000000 0x40000000>;
++ };
++};
++
+diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk
+index 1dee2d6..cb75fde 100644
+--- a/board/xilinx/microblaze-generic/config.mk
++++ b/board/xilinx/microblaze-generic/config.mk
+@@ -1,20 +1,10 @@
+-#
+-# (C) Copyright 2007 - 2016 Michal Simek
+-#
+-# Michal SIMEK <monstr@monstr.eu>
+-#
+-# SPDX-License-Identifier: GPL-2.0+
+-#
+-
+-CPU_VER := $(shell echo $(CONFIG_XILINX_MICROBLAZE0_HW_VER))
+-
+-# USE_HW_MUL can be 0, 1, or 2, defining a hierarchy of HW Mul support.
+-CPUFLAGS-$(subst 1,,$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)) += -mxl-multiply-high
+-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL) += -mno-xl-soft-mul
+-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_DIV) += -mno-xl-soft-div
+-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_BARREL) += -mxl-barrel-shift
+-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR) += -mxl-pattern-compare
+-
+-CPUFLAGS-1 += $(call cc-option,-mcpu=v$(CPU_VER))
+-
+-PLATFORM_CPPFLAGS += $(CPUFLAGS-1) $(CPUFLAGS-2)
++TEXT_BASE = 0x80400000
++CONFIG_SYS_TEXT_BASE = 0x80400000
++
++PLATFORM_CPPFLAGS += -mxl-barrel-shift
++PLATFORM_CPPFLAGS += -mno-xl-soft-div
++PLATFORM_CPPFLAGS += -mxl-pattern-compare
++PLATFORM_CPPFLAGS += -mxl-multiply-high
++PLATFORM_CPPFLAGS += -mno-xl-soft-mul
++PLATFORM_CPPFLAGS += -mcpu=v10.0
++PLATFORM_CPPFLAGS += -fgnu89-inline
+diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
+index 08d99f2..bac6939 100644
+--- a/configs/microblaze-generic_defconfig
++++ b/configs/microblaze-generic_defconfig
+@@ -1,5 +1,4 @@
+ CONFIG_MICROBLAZE=y
+-CONFIG_SYS_TEXT_BASE=0x29000000
+ CONFIG_SPL_LIBCOMMON_SUPPORT=y
+ CONFIG_SPL_LIBGENERIC_SUPPORT=y
+ CONFIG_SPL_SERIAL_SUPPORT=y
+@@ -8,50 +7,50 @@ CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
+ CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
+ CONFIG_XILINX_MICROBLAZE0_USE_DIV=1
+ CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1
++CONFIG_SYS_TEXT_BASE=0x80400000
+ CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
+ CONFIG_FIT=y
+ CONFIG_FIT_VERBOSE=y
+-CONFIG_BOOTDELAY=-1
+-CONFIG_USE_BOOTARGS=y
+-CONFIG_BOOTARGS="root=romfs"
++CONFIG_BOOTDELAY=4
+ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+-CONFIG_SPL=y
+-CONFIG_SPL_BOARD_INIT=y
+-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+ CONFIG_SPL_NOR_SUPPORT=y
+ CONFIG_SPL_OS_BOOT=y
+ CONFIG_SYS_OS_BASE=0x2c060000
+ CONFIG_HUSH_PARSER=y
+-CONFIG_SYS_PROMPT="U-Boot-mONStR> "
+-CONFIG_CMD_IMLS=y
+-CONFIG_CMD_SPL=y
++CONFIG_SYS_PROMPT="U-Boot> "
+ CONFIG_CMD_ASKENV=y
+-CONFIG_CMD_GPIO=y
+ CONFIG_CMD_SAVES=y
+ # CONFIG_CMD_SETEXPR is not set
+-CONFIG_CMD_TFTPPUT=y
++CONFIG_SYS_ENET=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_CMD_NET=y
+ CONFIG_CMD_DHCP=y
++CONFIG_CMD_NFS=y
+ CONFIG_CMD_MII=y
+ CONFIG_CMD_PING=y
+ CONFIG_CMD_JFFS2=y
+-CONFIG_SPL_OF_CONTROL=y
+ CONFIG_OF_EMBED=y
+-CONFIG_ENV_IS_IN_FLASH=y
+-CONFIG_NETCONSOLE=y
+-CONFIG_SPL_DM=y
+-CONFIG_MTD_NOR_FLASH=y
+-CONFIG_PHY_ATHEROS=y
+-CONFIG_PHY_BROADCOM=y
+-CONFIG_PHY_DAVICOM=y
+-CONFIG_PHY_LXT=y
+-CONFIG_PHY_MARVELL=y
+-CONFIG_PHY_MICREL=y
+-CONFIG_PHY_MICREL_KSZ90X1=y
+-CONFIG_PHY_NATSEMI=y
+-CONFIG_PHY_REALTEK=y
+-CONFIG_PHY_VITESSE=y
+ CONFIG_DM_ETH=y
++CONFIG_SYS_MALLOC_F=y
++CONFIG_SYS_GENERIC_BOARD=y
+ CONFIG_XILINX_AXIEMAC=y
+-CONFIG_XILINX_EMACLITE=y
+ CONFIG_SYS_NS16550=y
+-CONFIG_XILINX_UARTLITE=y
++CONFIG_CMD_FLASH=y
++CONFIG_MTD_NOR_FLASH=y
++CONFIG_CMD_IMLS=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_TFTPPUT=y
++CONFIG_NETCONSOLE=y
++CONFIG_XILINX_FSL_LINKS=0
++CONFIG_PHY_GIGE=y
++CONFIG_ENV_IS_IN_FLASH=y
++CONFIG_PHY_MICREL=y
++CONFIG_PHY_MICREL_KSZ90X1=y
++CONFIG_SPL_DM_SERIAL=y
++CONFIG_SPL_OF_LIBFDT=y
++CONFIG_PHY_XILINX=y
++# CONFIG_SPL is not set
++# CONFIG_CMD_EEPROM is not set
++# CONFIG_BOOTARGS is not set
++# CONFIG_USE_BOOTARGS is not set
+diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
+index 16481cb..1377c5e 100644
+--- a/include/configs/microblaze-generic.h
++++ b/include/configs/microblaze-generic.h
+@@ -1,254 +1,178 @@
+-/*
+- * (C) Copyright 2007-2010 Michal Simek
+- *
+- * Michal SIMEK <monstr@monstr.eu>
+- *
+- * SPDX-License-Identifier: GPL-2.0+
+- */
+-
+ #ifndef __CONFIG_H
+ #define __CONFIG_H
+
+-#include "../board/xilinx/microblaze-generic/xparameters.h"
+-
+-/* MicroBlaze CPU */
+-#define MICROBLAZE_V5 1
+-
+-/* linear and spi flash memory */
+-#ifdef XILINX_FLASH_START
+-#define FLASH
+-#undef SPIFLASH
+-#undef RAMENV /* hold environment in flash */
+-#else
+-#ifdef XILINX_SPI_FLASH_BASEADDR
+-#undef FLASH
+-#define SPIFLASH
+-#undef RAMENV /* hold environment in flash */
+-#else
+-#undef FLASH
+-#undef SPIFLASH
+-#define RAMENV /* hold environment in RAM */
+-#endif
+-#endif
+-
+-/* uart */
+-/* The following table includes the supported baudrates */
+-# define CONFIG_SYS_BAUDRATE_TABLE \
+- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+-
+-/* setting reset address */
+-/*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/
+-
+-/* gpio */
+-#ifdef XILINX_GPIO_BASEADDR
+-# define CONFIG_XILINX_GPIO
+-# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
+-#endif
+-
+-/* watchdog */
+-#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
+-# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
+-# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
+-# ifndef CONFIG_SPL_BUILD
+-# define CONFIG_HW_WATCHDOG
+-# define CONFIG_XILINX_TB_WATCHDOG
+-# endif
+-#endif
+-
+-#define CONFIG_SYS_MALLOC_LEN 0xC0000
+-
+-/* Stack location before relocation */
+-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \
+- CONFIG_SYS_MALLOC_F_LEN)
+-
+-/*
+- * CFI flash memory layout - Example
+- * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
+- * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
+- *
+- * SECT_SIZE = 0x20000; 128kB is one sector
+- * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
+- *
+- * 0x2200_0000 CONFIG_SYS_FLASH_BASE
+- * FREE 256kB
+- * 0x2204_0000 CONFIG_ENV_ADDR
+- * ENV_AREA 128kB
+- * 0x2206_0000
+- * FREE
+- * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
+- *
+- */
+-
+-#ifdef FLASH
+-# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
+-# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
+-# define CONFIG_SYS_FLASH_CFI 1
+-# define CONFIG_FLASH_CFI_DRIVER 1
+-/* ?empty sector */
+-# define CONFIG_SYS_FLASH_EMPTY_INFO 1
+-/* max number of memory banks */
+-# define CONFIG_SYS_MAX_FLASH_BANKS 1
+-/* max number of sectors on one chip */
+-# define CONFIG_SYS_MAX_FLASH_SECT 512
+-/* hardware flash protection */
+-# define CONFIG_SYS_FLASH_PROTECTION
+-/* use buffered writes (20x faster) */
+-# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+-# ifdef RAMENV
+-# define CONFIG_ENV_SIZE 0x1000
+-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
+-
+-# else /* FLASH && !RAMENV */
+-/* 128K(one sector) for env */
+-# define CONFIG_ENV_SECT_SIZE 0x20000
+-# define CONFIG_ENV_ADDR \
+- (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
+-# define CONFIG_ENV_SIZE 0x20000
+-# endif /* FLASH && !RAMBOOT */
+-#else /* !FLASH */
+-
+-#ifdef SPIFLASH
+-# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
+-# define CONFIG_SPI 1
+-# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
+-# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
+-# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
+-
+-# ifdef RAMENV
+-# define CONFIG_ENV_SIZE 0x1000
+-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
+-
+-# else /* SPIFLASH && !RAMENV */
+-# define CONFIG_ENV_SPI_MODE SPI_MODE_3
+-# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+-# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
+-/* 128K(two sectors) for env */
+-# define CONFIG_ENV_SECT_SIZE 0x10000
+-# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
+-/* Warning: adjust the offset in respect of other flash content and size */
+-# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
+-# endif /* SPIFLASH && !RAMBOOT */
+-#else /* !SPIFLASH */
+-
+-/* ENV in RAM */
+-# define CONFIG_ENV_SIZE 0x1000
+-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
+-#endif /* !SPIFLASH */
+-#endif /* !FLASH */
+-
+-#if defined(XILINX_USE_ICACHE)
+-# define CONFIG_ICACHE
+-#else
+-# undef CONFIG_ICACHE
+-#endif
+-
+-#if defined(XILINX_USE_DCACHE)
+-# define CONFIG_DCACHE
+-#else
+-# undef CONFIG_DCACHE
+-#endif
+-
+-#ifndef XILINX_DCACHE_BYTE_SIZE
+-#define XILINX_DCACHE_BYTE_SIZE 32768
+-#endif
+-
+-/*
+- * BOOTP options
+- */
++#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
++
++/* processor - microblaze_0 */
++#define XILINX_USE_MSR_INSTR 1
++#define XILINX_USE_ICACHE 1
++#define XILINX_USE_DCACHE 1
++#define XILINX_DCACHE_BYTE_SIZE 16384
++#define XILINX_PVR 2
++#define MICROBLAZE_V5
++#define CONFIG_CMD_IRQ
++#define CONFIG_DCACHE
++#define CONFIG_ICACHE
++
++/* main_memory - ddr3_sdram */
++
++
++/* uart - rs232_uart */
++#define CONFIG_SYS_NS16550_COM1 ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
++#define CONFIG_SYS_NS16550_REG_SIZE -4
++#define CONSOLE_ARG "console=console=ttyS0,115200\0"
++#define CONFIG_SYS_NS16550_SERIAL
++#define CONFIG_CONS_INDEX 1
++#define ESERIAL0 "eserial0=setenv stdout eserial0;setenv stdin eserial0\0"
++#define SERIAL_MULTI "serial=setenv stdout serial;setenv stdin serial\0"
++#define CONFIG_SYS_NS16550_CLK 200000000
++#define CONFIG_BAUDRATE 115200
++
++/* ethernet - axi_ethernet */
++#define CONFIG_PHY_XILINX
++#define CONFIG_MII
++#define CONFIG_PHY_MARVELL
++#define CONFIG_PHY_NATSEMI
++#define CONFIG_NET_MULTI
++#define CONFIG_PHY_REALTEK
++#define CONFIG_NETCONSOLE 1
++#define CONFIG_SERVERIP 172.25.229.115
++#define CONFIG_IPADDR
++
++/* nor_flash - linear_flash */
++#define CONFIG_SYS_FLASH_BASE 0x60000000
++#define CONFIG_FLASH_END 0x68000000
++#define CONFIG_SYS_MAX_FLASH_SECT 2048
++#define CONFIG_SYS_FLASH_PROTECTION
++#define CONFIG_SYS_FLASH_EMPTY_INFO
++#define CONFIG_SYS_FLASH_CFI
++#define CONFIG_FLASH_CFI_DRIVER
++#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
++#define CONFIG_SYS_MAX_FLASH_BANKS 1
++
++/* timer - axi_timer_0 */
++
++/* gpio - reset_gpio */
++#define XILINX_GPIO_BASEADDR 0x40000000
++#define CONFIG_SYS_GPIO_0_ADDR 0x40000000
++#define CONFIG_XILINX_GPIO
++
++/* intc - microblaze_0_axi_intc */
++
++/* FPGA */
++
++/* Memory testing handling */
++#define CONFIG_SYS_MEMTEST_START 0x80000000
++#define CONFIG_SYS_MEMTEST_END (0x80000000 + 0x1000)
++#define CONFIG_SYS_LOAD_ADDR 0x80000000 /* default load address */
++
++/* global pointer options */
++#define CONFIG_SYS_GBL_DATA_OFFSET (0x40000000 - GENERATED_GBL_DATA_SIZE)
++
++/* Size of malloc() pool */
++#define SIZE 0x100000
++#define CONFIG_SYS_MALLOC_LEN SIZE
++#define CONFIG_SYS_MONITOR_LEN SIZE
++#define CONFIG_SYS_MONITOR_BASE (0x80000000 + CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE)
++#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
++
++/* stack */
++#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_F_LEN)
++
++/* No of_control support yet*/
++
++/* BOOTP options */
++#define CONFIG_BOOTP_SERVERIP
+ #define CONFIG_BOOTP_BOOTFILESIZE
+ #define CONFIG_BOOTP_BOOTPATH
+ #define CONFIG_BOOTP_GATEWAY
+ #define CONFIG_BOOTP_HOSTNAME
++#define CONFIG_BOOTP_MAY_FAIL
++#define CONFIG_BOOTP_DNS
++#define CONFIG_BOOTP_SUBNETMASK
++#define CONFIG_BOOTP_PXE
+
+-#if defined(CONFIG_CMD_JFFS2)
+-# define CONFIG_MTD_PARTITIONS
+-#endif
+-
+-#if defined(CONFIG_CMD_UBI)
+-# define CONFIG_MTD_PARTITIONS
+-#endif
+-
+-#if defined(CONFIG_MTD_PARTITIONS)
+-/* MTD partitions */
+-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+-#define CONFIG_FLASH_CFI_MTD
+-
+-/* default mtd partition table */
+-#endif
+-
+-/* size of console buffer */
+-#define CONFIG_SYS_CBSIZE 512
+-/* max number of command args */
+-#define CONFIG_SYS_MAXARGS 15
+-#define CONFIG_SYS_LONGHELP
+-/* default load address */
+-#define CONFIG_SYS_LOAD_ADDR 0
+-
+-#define CONFIG_HOSTNAME XILINX_BOARD_NAME
+-#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
+-
+-/* architecture dependent code */
+-#define CONFIG_SYS_USR_EXCEP /* user exception */
+-
+-#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
+-
+-#ifndef CONFIG_EXTRA_ENV_SETTINGS
+-#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
+- "nor0=flash-0\0"\
+- "mtdparts=mtdparts=flash-0:"\
+- "256k(u-boot),256k(env),3m(kernel),"\
+- "1m(romfs),1m(cramfs),-(jffs2)\0"\
+- "nc=setenv stdout nc;"\
+- "setenv stdin nc\0" \
+- "serial=setenv stdout serial;"\
+- "setenv stdin serial\0"
+-#endif
+-
++/*Command line configuration.*/
+ #define CONFIG_CMDLINE_EDITING
++#define CONFIG_AUTO_COMPLETE
+
+-/* Enable flat device tree support */
+-#define CONFIG_LMB 1
+-
+-#if defined(CONFIG_XILINX_AXIEMAC)
+-# define CONFIG_MII 1
+-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
+-#else
+-# undef CONFIG_MII
+-#endif
+-
+-/* SPL part */
+-#define CONFIG_SPL_FRAMEWORK
++/* Miscellaneous configurable options */
++#define CONFIG_SYS_CBSIZE 2048/* Console I/O Buffer Size */
++#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
++#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+-#ifdef CONFIG_SYS_FLASH_BASE
+-# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
+-#endif
+-
+-/* for booting directly linux */
+
+-#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
+- 0x40000)
+-#define CONFIG_SYS_FDT_SIZE (16<<10)
+-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
+- 0x1000000)
++/* Use the HUSH parser */
++#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+-/* SP location before relocation, must use scratch RAM */
+-/* BRAM start */
+-#define CONFIG_SYS_INIT_RAM_ADDR 0x0
+-/* BRAM size - will be generated */
+-#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
++#define CONFIG_ENV_VARS_UBOOT_CONFIG
++#define CONFIG_ENV_OVERWRITE /* Allow to overwrite the u-boot environment variables */
+
+-# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+- CONFIG_SYS_INIT_RAM_SIZE - \
+- CONFIG_SYS_MALLOC_F_LEN)
++#define CONFIG_LMB
+
+-/* Just for sure that there is a space for stack */
+-#define CONFIG_SPL_STACK_SIZE 0x100
++/* FDT support */
++#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+-#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+
+-#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
+- CONFIG_SYS_INIT_RAM_ADDR - \
+- CONFIG_SYS_MALLOC_F_LEN - \
+- CONFIG_SPL_STACK_SIZE)
++/* architecture dependent code */
++#define CONFIG_SYS_USR_EXCEP /* user exception */
++#define CONFIG_SYS_HZ 1000
++
++/* Boot Argument Buffer Size */
++#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
++#define CONFIG_SYS_LONGHELP
++/* Initial memory map for Linux */
++#define CONFIG_SYS_BOOTMAPSZ 0x8000000
++
++/* Environment settings*/
++#define CONFIG_ENV_ADDR 0x60b80000
++#define CONFIG_ENV_SIZE 0x20000
++#define CONFIG_ENV_SECT_SIZE 0x20000
++/* PREBOOT */
++#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot; echo; dhcp"
++
++/* Extra U-Boot Env settings */
++#define CONFIG_EXTRA_ENV_SETTINGS \
++ SERIAL_MULTI \
++ CONSOLE_ARG \
++ ESERIAL0 \
++ "nc=setenv stdout nc;setenv stdin nc;\0" \
++ "ethaddr=00:0a:35:00:22:01\0" \
++ "autoload=no\0" \
++ "sdbootdev=0\0" \
++ "clobstart=0x81000000\0" \
++ "netstart=0x81000000\0" \
++ "dtbnetstart=0x82800000\0" \
++ "loadaddr=0x81000000\0" \
++ "bootsize=0x80000\0" \
++ "bootstart=0x60b00000\0" \
++ "boot_img=u-boot-s.bin\0" \
++ "load_boot=tftpboot ${clobstart} ${boot_img}\0" \
++ "update_boot=setenv img boot; setenv psize ${bootsize}; setenv installcmd \"install_boot\"; run load_boot test_img; setenv img; setenv psize; setenv installcmd\0" \
++ "install_boot=protect off ${bootstart} +${bootsize} && erase ${bootstart} +${bootsize} && " "cp.b ${clobstart} ${bootstart} ${filesize}\0" \
++ "bootenvsize=0x20000\0" \
++ "bootenvstart=0x60b80000\0" \
++ "eraseenv=protect off ${bootenvstart} +${bootenvsize} && erase ${bootenvstart} +${bootenvsize}\0" \
++ "kernelsize=0xc00000\0" \
++ "kernelstart=0x60ba0000\0" \
++ "kernel_img=image.ub\0" \
++ "load_kernel=tftpboot ${clobstart} ${kernel_img}\0" \
++ "update_kernel=setenv img kernel; setenv psize ${kernelsize}; setenv installcmd \"install_kernel\"; run load_kernel test_crc; setenv img; setenv psize; setenv installcmd\0" \
++ "install_kernel=protect off ${kernelstart} +${kernelsize} && erase ${kernelstart} +${kernelsize} && " "cp.b ${clobstart} ${kernelstart} ${filesize}\0" \
++ "cp_kernel2ram=cp.b ${kernelstart} ${netstart} ${kernelsize}\0" \
++ "fpgasize=0xb00000\0" \
++ "fpgastart=0x60000000\0" \
++ "fpga_img=system.bit.bin\0" \
++ "load_fpga=tftpboot ${clobstart} ${fpga_img}\0" \
++ "update_fpga=setenv img fpga; setenv psize ${fpgasize}; setenv installcmd \"install_fpga\"; run load_fpga test_img; setenv img; setenv psize; setenv installcmd\0" \
++ "install_fpga=protect off ${fpgastart} +${fpgasize} && erase ${fpgastart} +${fpgasize} && " "cp.b ${clobstart} ${fpgastart} ${filesize}\0" \
++ "fault=echo ${img} image size is greater than allocated place - partition ${img} is NOT UPDATED\0" \
++ "test_crc=if imi ${clobstart}; then run test_img; else echo ${img} Bad CRC - ${img} is NOT UPDATED; fi\0" \
++ "test_img=setenv var \"if test ${filesize} -gt ${psize}\\; then run fault\\; else run ${installcmd}\\; fi\"; run var; setenv var\0" \
++ "netboot=tftpboot ${netstart} ${kernel_img} && bootm\0" \
++ "default_bootcmd=run cp_kernel2ram && bootm ${netstart}\0" \
++""
++/* BOOTCOMMAND */
++#define CONFIG_BOOTCOMMAND "run default_bootcmd"
+
+-#endif /* __CONFIG_H */
++#endif
+--
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2018.1.bb b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2018.1.bb
new file mode 100644
index 0000000..fb2c618
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2018.1.bb
@@ -0,0 +1,27 @@
+UBOOT_VERSION = "v2018.01"
+XILINX_RELEASE_VERSION = "v2018.1"
+
+UBRANCH ?= "master"
+
+SRCREV ?= "949e5cb9a736bac32ea8886e3953da55bdd30754"
+
+include u-boot-xlnx.inc
+include u-boot-spl-zynq-init.inc
+
+SRC_URI_append_kc705-microblazeel = " file://microblaze-kc705-Convert-microblaze-generic-to-k.patch"
+
+LICENSE = "GPLv2+"
+LIC_FILES_CHKSUM = "file://README;beginline=1;endline=6;md5=157ab8408beab40cd8ce1dc69f702a6c"
+
+# u-boot-xlnx has support for these
+HAS_PLATFORM_INIT ?= " \
+ zynq_microzed_config \
+ zynq_zed_config \
+ zynq_zc702_config \
+ zynq_zc706_config \
+ zynq_zybo_config \
+ xilinx_zynqmp_zcu102_rev1_0_config \
+ xilinx_zynqmp_zcu106_revA_config \
+ xilinx_zynqmp_zcu104_revC_config \
+ "
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-uenv.bb b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-uenv.bb
new file mode 100644
index 0000000..f6c2a00
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-uenv.bb
@@ -0,0 +1,116 @@
+SUMMARY = "U-Boot uEnv.txt SD boot environment generation for Zynq targets"
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
+
+INHIBIT_DEFAULT_DEPS = "1"
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE_zynq = ".*"
+COMPATIBLE_MACHINE_zynqmp = ".*"
+
+inherit deploy
+
+def bootfiles_bitstream(d):
+ expectedfiles = [("bitstream", True)]
+ expectedexts = [(".bit", True), (".bin", False)]
+ # search for bitstream paths, use the renamed file. First matching is used
+ for f in (d.getVar("IMAGE_BOOT_FILES") or "").split():
+ sf, rf = f, f
+ if ';' in f:
+ sf, rf = f.split(';')
+
+ # skip boot.bin and u-boot.bin, it is not a bitstream
+ skip = ["boot.bin", "u-boot.bin"]
+ if sf in skip or rf in skip:
+ continue
+
+ for e, t in expectedfiles:
+ if sf == e or rf == e:
+ return rf, t
+ for e, t in expectedexts:
+ if sf.endswith(e) or rf.endswith(e):
+ return rf, t
+ return "", False
+
+def bootfiles_dtb_filepath(d):
+ if d.getVar("IMAGE_BOOT_FILES"):
+ dtbs = d.getVar("IMAGE_BOOT_FILES").split(" ")
+ # IMAGE_BOOT_FILES has extra renaming info in the format '<source>;<target>'
+ dtbs = [f.split(";")[0] for f in dtbs]
+ dtbs = [f for f in dtbs if f.endswith(".dtb")]
+ if len(dtbs) != 0:
+ return dtbs[0]
+ return ""
+
+def uboot_boot_cmd(d):
+ if d.getVar("KERNEL_IMAGETYPE") in ["uImage", "fitImage"]:
+ return "bootm"
+ if d.getVar("KERNEL_IMAGETYPE") in ["zImage"]:
+ return "bootz"
+ if d.getVar("KERNEL_IMAGETYPE") in ["Image"]:
+ return "booti"
+ raise bb.parse.SkipRecipe("Unsupport kernel image type")
+
+def uenv_populate(d):
+ # populate the environment values
+ env = {}
+
+ env["machine_name"] = d.getVar("MACHINE")
+
+ env["kernel_image"] = d.getVar("KERNEL_IMAGETYPE")
+ env["kernel_load_address"] = d.getVar("KERNEL_LOAD_ADDRESS")
+
+ env["devicetree_image"] = bootfiles_dtb_filepath(d)
+ env["devicetree_load_address"] = d.getVar("DEVICETREE_LOAD_ADDRESS")
+
+ env["bootargs"] = d.getVar("KERNEL_BOOTARGS")
+
+ env["loadkernel"] = "fatload mmc 0 ${kernel_load_address} ${kernel_image}"
+ env["loaddtb"] = "fatload mmc 0 ${devicetree_load_address} ${devicetree_image}"
+ env["bootkernel"] = "run loadkernel && run loaddtb && " + uboot_boot_cmd(d) + " ${kernel_load_address} - ${devicetree_load_address}"
+
+ # default uenvcmd does not load bitstream
+ env["uenvcmd"] = "run bootkernel"
+
+ bitstream, bitstreamtype = bootfiles_bitstream(d)
+ if bitstream:
+ env["bitstream_image"] = bitstream
+ env["bitstream_load_address"] = "0x100000"
+
+ # if bitstream is "bit" format use loadb, otherwise use load
+ env["bitstream_type"] = "loadb" if bitstreamtype else "load"
+
+ # load bitstream first with loadfpa
+ env["loadfpga"] = "fatload mmc 0 ${bitstream_load_address} ${bitstream_image} && fpga ${bitstream_type} 0 ${bitstream_load_address} ${filesize}"
+ env["uenvcmd"] = "run loadfpga && run bootkernel"
+
+ return env
+
+# bootargs, default to booting with the rootfs device being partition 2 of the first mmc device
+KERNEL_BOOTARGS_zynq = "earlyprintk console=ttyPS0,115200 root=/dev/mmcblk0p2 rw rootwait"
+KERNEL_BOOTARGS_zynqmp = "earlycon clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait"
+
+KERNEL_LOAD_ADDRESS_zynq = "0x2080000"
+KERNEL_LOAD_ADDRESS_zynqmp = "0x80000"
+DEVICETREE_LOAD_ADDRESS_zynq = "0x2000000"
+DEVICETREE_LOAD_ADDRESS_zynqmp = "0x4000000"
+
+python do_compile() {
+ env = uenv_populate(d)
+ with open(d.expand("${WORKDIR}/uEnv.txt"), "w") as f:
+ for k, v in env.items():
+ f.write("{0}={1}\n".format(k, v))
+}
+
+FILES_${PN} += "/boot/uEnv.txt"
+
+do_install() {
+ install -Dm 0644 ${WORKDIR}/uEnv.txt ${D}/boot/uEnv.txt
+}
+
+do_deploy() {
+ install -Dm 0644 ${WORKDIR}/uEnv.txt ${DEPLOYDIR}/uEnv.txt
+}
+addtask do_deploy after do_compile before do_build
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot_%.bbappend
new file mode 100644
index 0000000..b852236
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot_%.bbappend
@@ -0,0 +1,11 @@
+include u-boot-spl-zynq-init.inc
+
+# u-boot 2016.11 has support for these
+HAS_PLATFORM_INIT ??= " \
+ zynq_microzed_config \
+ zynq_zed_config \
+ zynq_zc702_config \
+ zynq_zc706_config \
+ zynq_zybo_config \
+ "
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-core/newlib/libgloss_3.0.0.bb b/meta-xilinx/meta-xilinx-bsp/recipes-core/newlib/libgloss_3.0.0.bb
new file mode 100644
index 0000000..cff4a26
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-core/newlib/libgloss_3.0.0.bb
@@ -0,0 +1,27 @@
+
+require newlib.inc
+
+DEPENDS += "newlib"
+
+do_configure() {
+ ${S}/libgloss/configure ${EXTRA_OECONF}
+}
+
+do_install_prepend() {
+ # install doesn't create this itself, avoid install error
+ install -d ${D}${prefix}/${TARGET_SYS}/lib
+}
+
+do_install_append() {
+ # Move libs to default directories so they can be picked up later
+ mv -v ${D}${prefix}/${TARGET_SYS}/lib ${D}${libdir}
+
+ # Remove original directory
+ rmdir ${D}${prefix}/${TARGET_SYS}
+}
+
+# Split packages correctly
+FILES_${PN} += "${libdir}/*.ld ${libdir}/*.specs"
+
+INHIBIT_PACKAGE_STRIP = "1"
+INHIBIT_PACKAGE_DEBUG_SPLIT = "1"
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-core/newlib/newlib.inc b/meta-xilinx/meta-xilinx-bsp/recipes-core/newlib/newlib.inc
new file mode 100644
index 0000000..37ad6be
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-core/newlib/newlib.inc
@@ -0,0 +1,58 @@
+SUMMARY = "Newlib is a C library intended for use on embedded systems"
+HOMEPAGE = "https://sourceware.org/newlib/"
+DESCRIPTION = "It is a conglomeration of several library parts, all under free software licenses that make them easily usable on embedded products."
+SECTION = "libs"
+
+LICENSE = "GPLv2 & LGPLv3 & GPLv3 & LGPLv2"
+LIC_FILES_CHKSUM = " \
+ file://COPYING;md5=59530bdf33659b29e73d4adb9f9f6552 \
+ file://COPYING3.LIB;md5=6a6a8e020838b23406c81b19c1d46df6 \
+ file://COPYING3;md5=d32239bcb673463ab874e80d47fae504 \
+ file://COPYING.LIBGLOSS;md5=73f5c98779aea7dba4a6c94a74ab0ae2 \
+ file://COPYING.LIB;md5=2d5025d4aa3495befef8f17206a5b0a1 \
+ file://COPYING.NEWLIB;md5=956a4b1487f7677cdcceeee8f05a21f0 \
+ file://newlib/libc/posix/COPYRIGHT;md5=103468ff1982be840fdf4ee9f8b51bbf \
+ file://newlib/libc/sys/linux/linuxthreads/LICENSE;md5=73640207fbc79b198c7ffd4ad4d97aa0 \
+ "
+
+SRC_URI = "ftp://sourceware.org/pub/newlib/newlib-${PV}.tar.gz"
+SRC_URI[md5sum] = "81ec873108b8593c586f91ca65963952"
+SRC_URI[sha256sum] = "c8566335ee74e5fcaeb8595b4ebd0400c4b043d6acb3263ecb1314f8f5501332"
+
+INHIBIT_DEFAULT_DEPS = "1"
+DEPENDS = "virtual/${TARGET_PREFIX}gcc-initial"
+
+PATH_prepend = "${STAGING_BINDIR_TOOLCHAIN}.${STAGINGCC}:"
+STAGINGCC = "${MLPREFIX}gcc-cross-initial-${TARGET_ARCH}"
+
+S = "${WORKDIR}/newlib-${PV}"
+B = "${WORKDIR}/build"
+
+# Disable use of a link hash style
+TARGET_LINK_HASH_STYLE_microblaze = ""
+
+# disable stdlib
+TARGET_CC_ARCH_append = " -nostdlib"
+
+EXTRA_OECONF = " \
+ --build=${BUILD_SYS} \
+ --target=${TARGET_SYS} \
+ --host=${HOST_SYS} \
+ --prefix=${prefix} \
+ --exec-prefix=${exec_prefix} \
+ --bindir=${bindir} \
+ --libdir=${libdir} \
+ --includedir=${includedir} \
+ --enable-languages=c \
+ --with-newlib \
+ --with-gnu-as \
+ --with-gnu-ld \
+ --disable-multilib \
+ "
+
+do_configure[cleandirs] = "${B}"
+
+do_install() {
+ oe_runmake install DESTDIR='${D}'
+}
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-core/newlib/newlib_3.0.0.bb b/meta-xilinx/meta-xilinx-bsp/recipes-core/newlib/newlib_3.0.0.bb
new file mode 100644
index 0000000..3d31350
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-core/newlib/newlib_3.0.0.bb
@@ -0,0 +1,19 @@
+require newlib.inc
+
+do_configure_prepend_microblaze() {
+ # hack for microblaze, which needs xilinx.ld to literally do any linking (its hard coded in its LINK_SPEC)
+ export CC="${CC} -L${S}/libgloss/microblaze"
+}
+
+do_configure() {
+ ${S}/configure ${EXTRA_OECONF}
+}
+
+do_install_append() {
+ # Move include files and libs to default directories so they can be picked up later
+ mv -v ${D}${prefix}/${TARGET_SYS}/lib ${D}${libdir}
+ mv -v ${D}${prefix}/${TARGET_SYS}/include ${D}${includedir}
+
+ # Remove original directory
+ rmdir ${D}${prefix}/${TARGET_SYS}
+}
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/memfd.patch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/memfd.patch
new file mode 100644
index 0000000..62e8d38
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/memfd.patch
@@ -0,0 +1,57 @@
+Upstream-Status: Backport
+Signed-off-by: Ross Burton <ross.burton@intel.com>
+
+From 75e5b70e6b5dcc4f2219992d7cffa462aa406af0 Mon Sep 17 00:00:00 2001
+From: Paolo Bonzini <pbonzini@redhat.com>
+Date: Tue, 28 Nov 2017 11:51:27 +0100
+Subject: [PATCH] memfd: fix configure test
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Recent glibc added memfd_create in sys/mman.h. This conflicts with
+the definition in util/memfd.c:
+
+ /builddir/build/BUILD/qemu-2.11.0-rc1/util/memfd.c:40:12: error: static declaration of memfd_create follows non-static declaration
+
+Fix the configure test, and remove the sys/memfd.h inclusion since the
+file actually does not exist---it is a typo in the memfd_create(2) man
+page.
+
+Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
+Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
+---
+ configure | 2 +-
+ util/memfd.c | 4 +---
+ 2 files changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/configure b/configure
+index 9c8aa5a98b..99ccc1725a 100755
+--- a/configure
++++ b/configure
+@@ -3923,7 +3923,7 @@ fi
+ # check if memfd is supported
+ memfd=no
+ cat > $TMPC << EOF
+-#include <sys/memfd.h>
++#include <sys/mman.h>
+
+ int main(void)
+ {
+diff --git a/util/memfd.c b/util/memfd.c
+index 4571d1aba8..412e94a405 100644
+--- a/util/memfd.c
++++ b/util/memfd.c
+@@ -31,9 +31,7 @@
+
+ #include "qemu/memfd.h"
+
+-#ifdef CONFIG_MEMFD
+-#include <sys/memfd.h>
+-#elif defined CONFIG_LINUX
++#if defined CONFIG_LINUX && !defined CONFIG_MEMFD
+ #include <sys/syscall.h>
+ #include <asm/unistd.h>
+
+--
+2.11.0
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/qemu-system-aarch64-multiarch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/qemu-system-aarch64-multiarch
new file mode 100644
index 0000000..15124c1
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/qemu-system-aarch64-multiarch
@@ -0,0 +1,32 @@
+#!/bin/bash
+
+BINPATH=$(dirname $0)
+MACHINE_PATH=$(mktemp -d)
+
+APU_ARGS=
+PMU_ARGS=
+
+while [ ! -z "$1" ]; do
+ if [ "$1" = "-pmu-args" ]; then
+ PMU_ARGS+=" $2"
+ shift
+ else
+ APU_ARGS+=" $1"
+ fi
+ shift
+done
+
+PMU_ROM=$(last=; for i in $PMU_ARGS; do if [ "$last" = "-kernel" ]; then echo "$i"; break; fi; last=$i; done)
+if [ ! -e $PMU_ROM ]; then
+ echo "------"
+ echo "Error: Missing PMU ROM - $PMU_ROM"
+ echo " See 'meta-xilinx/README.qemu.md' for more information on accquiring the PMU ROM."
+ echo "------"
+ exit 255
+fi
+
+# start the PMU instance
+$BINPATH/qemu-system-microblazeel $PMU_ARGS -machine-path $MACHINE_PATH &
+# start the APU instance
+$BINPATH/qemu-system-aarch64 $APU_ARGS -machine-path $MACHINE_PATH
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees.inc b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees.inc
new file mode 100644
index 0000000..d4044ed
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees.inc
@@ -0,0 +1,37 @@
+SUMMARY = "Xilinx's hardware device trees required for QEMU"
+HOMEPAGE = "https://github.com/xilinx/qemu-devicetrees/"
+LICENSE = "BSD"
+DEPENDS += "dtc-native"
+
+inherit deploy
+
+LIC_FILES_CHKSUM = "file://Makefile;beginline=1;endline=27;md5=7348b6cbcae69912cb1dee68d6c68d99"
+
+PV = "xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}"
+
+BRANCH ?= ""
+REPO ?= "git://github.com/Xilinx/qemu-devicetrees.git;protocol=https"
+
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
+
+S = "${WORKDIR}/git"
+
+# Don't need to do anything
+do_install() {
+ :
+}
+
+do_deploy() {
+ # single-arch dtbs
+ for DTS_FILE in ${S}/LATEST/SINGLE_ARCH/*.dtb; do
+ install -Dm 0644 $DTS_FILE ${DEPLOYDIR}/qemu-hw-devicetrees/$(basename $DTS_FILE .dtb).dtb
+ done
+
+ # multi-arch dtbs
+ for DTS_FILE in ${S}/LATEST/MULTI_ARCH/*.dtb; do
+ install -Dm 0644 $DTS_FILE ${DEPLOYDIR}/qemu-hw-devicetrees/multiarch/$(basename $DTS_FILE .dtb).dtb
+ done
+}
+
+addtask deploy after do_install
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2018.1.bb b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2018.1.bb
new file mode 100644
index 0000000..a73b9e5
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2018.1.bb
@@ -0,0 +1,6 @@
+require qemu-devicetrees.inc
+
+XILINX_RELEASE_VERSION = "v2018.1"
+
+BRANCH ?= "master"
+SRCREV ?= "d5017f8119b6493d8b2fcdfd5caa4e8b16580877"
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-helper-native_1.0.bb b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-helper-native_1.0.bb
new file mode 100644
index 0000000..55b35b5
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-helper-native_1.0.bb
@@ -0,0 +1,28 @@
+
+python () {
+ if d.getVar("PREFERRED_PROVIDER_qemu-helper-native") != d.getVar("PN"):
+ raise bb.parse.SkipRecipe("Set qemu-helper-native provider to use this recipe")
+}
+
+def get_filespath_extra(d, subpath):
+ metaroot = next((p for p in d.getVar('BBPATH').split(':') if os.path.basename(p) == 'meta'), None)
+ if metaroot:
+ return os.path.join(metaroot, subpath) + ":"
+ return ""
+
+# TODO: improve this, since it is very hacky that this recipe need to build tunctl.
+# include the existing qemu-helper-native
+require recipes-devtools/qemu/qemu-helper-native_1.0.bb
+# get the path to tunctl.c
+FILESEXTRAPATHS_prepend := "${@get_filespath_extra(d, 'recipes-devtools/qemu/qemu-helper')}"
+
+# provide it, to replace the existing
+PROVIDES += "qemu-helper-native"
+
+# replace qemu with qemu-xilinx
+DEPENDS_remove = "qemu-native"
+DEPENDS_append = " \
+ qemu-xilinx-native \
+ qemu-xilinx-multiarch-helper-native \
+ "
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-multiarch-helper-native_1.0.bb b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-multiarch-helper-native_1.0.bb
new file mode 100644
index 0000000..a9b11c6
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-multiarch-helper-native_1.0.bb
@@ -0,0 +1,20 @@
+SUMMARY = "Helper scripts for executing a multi-arch instance of Xilinx QEMU"
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
+RDEPENDS_${PN} = "qemu-xilinx-native"
+
+inherit native
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+
+SRC_URI = "file://qemu-system-aarch64-multiarch"
+
+do_configure[noexec] = "1"
+do_compile[noexec] = "1"
+
+SYSROOT_DIRS += "${bindir}/qemu-xilinx"
+
+do_install() {
+ install -Dm 0755 ${WORKDIR}/qemu-system-aarch64-multiarch ${D}${bindir}/qemu-xilinx/qemu-system-aarch64-multiarch
+}
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx.inc
new file mode 100644
index 0000000..b6c5dee
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx.inc
@@ -0,0 +1,51 @@
+QEMU_TARGETS = "aarch64 arm microblaze microblazeel"
+
+require recipes-devtools/qemu/qemu.inc
+
+SUMMARY = "Xilinx's fork of a fast open source processor emulator"
+HOMEPAGE = "https://github.com/xilinx/qemu/"
+
+LIC_FILES_CHKSUM = " \
+ file://COPYING;md5=441c28d2cf86e15a37fa47e15a72fbac \
+ file://COPYING.LIB;endline=24;md5=c04def7ae38850e7d3ef548588159913 \
+ "
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+
+PV = "${XILINX_QEMU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}"
+BRANCH ?= ""
+REPO ?= "git://github.com/Xilinx/qemu.git;protocol=https"
+
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG} \
+ file://memfd.patch \
+ "
+
+S = "${WORKDIR}/git"
+
+# Disable KVM completely
+PACKAGECONFIG_remove = "kvm"
+
+# Enable libgcrypt
+PACKAGECONFIG_append = " gcrypt"
+
+DISABLE_STATIC_pn-${PN} = ""
+
+PTEST_ENABLED = ""
+
+# append a suffix dir, to allow multiple versions of QEMU to be installed
+EXTRA_OECONF_append = " \
+ --bindir=${bindir}/qemu-xilinx \
+ --libexecdir=${libexecdir}/qemu-xilinx \
+ "
+
+do_configure_prepend() {
+ # rewrite usage of 'libgcrypt-config' with 'pkg-config libgcrypt'
+ sed -r -i 's/libgcrypt-config(\s*--)/pkg-config libgcrypt\1/g' ${S}/configure
+}
+
+do_install_append() {
+ # Prevent QA warnings about installed ${localstatedir}/run
+ if [ -d ${D}${localstatedir}/run ]; then rmdir ${D}${localstatedir}/run; fi
+}
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2018.1.bb b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2018.1.bb
new file mode 100644
index 0000000..1d6697c
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2018.1.bb
@@ -0,0 +1,6 @@
+require qemu-xilinx.inc
+
+XILINX_RELEASE_VERSION = "v2018.1"
+XILINX_QEMU_VERSION ?= "v2.11.0"
+BRANCH ?= "master"
+SRCREV ?= "1d5516986ea296d91a599ac23252e302a4003914"
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/egl.pc b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/egl.pc
new file mode 100644
index 0000000..f9935f2
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/egl.pc
@@ -0,0 +1,12 @@
+prefix=/usr
+exec_prefix=${prefix}
+libdir=/usr/lib
+includedir=/usr/include
+
+Name: egl
+Description: MALI EGL library
+Requires.private:
+Version: r8p0
+Libs: -L${libdir} -lEGL
+Libs.private: -lm -lpthread -ldl
+Cflags: -I${includedir}
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/glesv1.pc b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/glesv1.pc
new file mode 100644
index 0000000..4895400
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/glesv1.pc
@@ -0,0 +1,12 @@
+prefix=/usr
+exec_prefix=${prefix}
+libdir=/usr/lib
+includedir=/usr/include
+
+Name: glesv1
+Description: MALI OpenGL ES 1.1 library
+Requires.private:
+Version: r8p0
+Libs: -L${libdir} -lGLESv1_CM
+Libs.private: -lm -lpthread -ldl
+Cflags: -I${includedir}
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/glesv1_cm.pc b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/glesv1_cm.pc
new file mode 100644
index 0000000..888af87
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/glesv1_cm.pc
@@ -0,0 +1,12 @@
+prefix=/usr
+exec_prefix=${prefix}
+libdir=/usr/lib
+includedir=/usr/include
+
+Name: gles_cm
+Description: Mali OpenGL ES 1.1 CM library
+Requires.private:
+Version: r8p0
+Libs: -L${libdir} -lGLESv1_CM
+Libs.private: -lm -lpthread -ldl
+Cflags: -I${includedir}
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/glesv2.pc b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/glesv2.pc
new file mode 100644
index 0000000..5047c39
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/files/glesv2.pc
@@ -0,0 +1,12 @@
+prefix=/usr
+exec_prefix=${prefix}
+libdir=/usr/lib
+includedir=/usr/include
+
+Name: glesv2
+Description: MALI OpenGL ES 2.0 library
+Requires.private:
+Version: r8p0
+Libs: -L${libdir} -lGLESv2
+Libs.private: -lm -lpthread -ldl
+Cflags: -I${includedir}
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/libmali-xlnx.bb b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/libmali-xlnx.bb
new file mode 100644
index 0000000..3e675d9
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/libmali-xlnx.bb
@@ -0,0 +1,108 @@
+DESCRIPTION = "libGLES for ZynqMP with Mali 400"
+
+LICENSE = "Proprietary"
+LICENSE_FLAGS = "xilinx"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/Proprietary;md5=0557f9d92cf58f2ccdd50f62f8ac0b28"
+
+inherit distro_features_check
+inherit xilinx-fetch-restricted
+
+ANY_OF_DISTRO_FEATURES = "fbdev x11"
+
+PROVIDES += "virtual/libgles1 virtual/libgles2 virtual/egl"
+
+FILESEXTRAPATHS_append := " \
+ ${THISDIR}/files: \
+ ${THISDIR}/r8p0-00rel0: "
+
+
+# Fetch the MALI 400 binaries from here
+# https://www.xilinx.com/member/forms/download/mali-driver-license.html?filename=mali-400-userspace.tar
+
+PV = "r8p0-01rel0"
+SRC_URI = " \
+ https://www.xilinx.com/member/forms/download/mali-driver-license.html?filename=mali-400-userspace.tar;downloadfilename=mali-400-userspace.tar \
+ file://egl.pc \
+ file://glesv1_cm.pc \
+ file://glesv1.pc \
+ file://glesv2.pc \
+ "
+
+SRC_URI[md5sum] = "e75b147c8b4ee96616e24572cdc9c21f"
+SRC_URI[sha256sum] = "7b179ec2df54ee05a886cca1535c0bdc6cba77a646e22742adedc79bfc2b3017"
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE_zynqmpeg = "zynqmpeg"
+COMPATIBLE_MACHINE_zynqmpev = "zynqmpev"
+
+PACKAGE_ARCH = "${SOC_FAMILY}${SOC_VARIANT}"
+
+
+S = "${WORKDIR}/mali-400"
+
+X11RDEPENDS = "libxdamage libxext libx11 libdrm libxfixes"
+X11DEPENDS = "libxdamage libxext virtual/libx11 libdrm libxfixes"
+
+RDEPENDS_${PN} = " \
+ kernel-module-mali \
+ ${@bb.utils.contains('DISTRO_FEATURES', 'x11', '${X11RDEPENDS}', '', d)} \
+ "
+
+DEPENDS = "\
+ ${@bb.utils.contains('DISTRO_FEATURES', 'x11', '${X11DEPENDS}', '', d)} \
+ "
+
+EGL_TYPE = "${@bb.utils.contains('DISTRO_FEATURES', 'x11', 'x11', \
+ bb.utils.contains('DISTRO_FEATURES', 'fbdev', 'fbdev', '', d), d)}"
+
+do_compile() {
+ # Extract the MALI binaries into workdir
+ tar -xf ${WORKDIR}/mali/rel-v2018.1/r8p0-01rel0.tar -C ${S}
+}
+
+do_install() {
+ #Identify the ARCH type
+ ${TARGET_PREFIX}gcc --version > ARCH_PLATFORM
+ if grep -q aarch64 "ARCH_PLATFORM"; then
+ ARCH_PLATFORM_DIR=aarch64-linux-gnu
+ else
+ ARCH_PLATFORM_DIR=arm-linux-gnueabihf
+ fi
+
+ # install headers
+ install -d -m 0655 ${D}${includedir}/EGL
+ install -m 0644 ${S}/${PV}/${ARCH_PLATFORM_DIR}/${EGL_TYPE}/usr/include/EGL/*.h ${D}${includedir}/EGL/
+ install -d -m 0655 ${D}${includedir}/GLES
+ install -m 0644 ${S}/${PV}/${ARCH_PLATFORM_DIR}/${EGL_TYPE}/usr/include/GLES/*.h ${D}${includedir}/GLES/
+ install -d -m 0655 ${D}${includedir}/GLES2
+ install -m 0644 ${S}/${PV}/${ARCH_PLATFORM_DIR}/${EGL_TYPE}/usr/include/GLES2/*.h ${D}${includedir}/GLES2/
+ install -d -m 0655 ${D}${includedir}/KHR
+ install -m 0644 ${S}/${PV}/${ARCH_PLATFORM_DIR}/${EGL_TYPE}/usr/include/KHR/*.h ${D}${includedir}/KHR/
+
+ install -d ${D}${libdir}/pkgconfig
+ install -m 0644 ${WORKDIR}/egl.pc ${D}${libdir}/pkgconfig/egl.pc
+ install -m 0644 ${WORKDIR}/glesv2.pc ${D}${libdir}/pkgconfig/glesv2.pc
+ install -m 0644 ${WORKDIR}/glesv1.pc ${D}${libdir}/pkgconfig/glesv1.pc
+ install -m 0644 ${WORKDIR}/glesv1_cm.pc ${D}${libdir}/pkgconfig/glesv1_cm.pc
+
+ install -d ${D}${libdir}
+ cp -a --no-preserve=ownership ${S}/${PV}/${ARCH_PLATFORM_DIR}/${EGL_TYPE}/usr/lib/*.so* ${D}${libdir}
+
+ if ${@bb.utils.contains('DISTRO_FEATURES', 'x11', 'false', 'true', d)}; then
+ sed -i -e 's/^#if defined(MESA_EGL_NO_X11_HEADERS)$/#if (1)/' ${D}${includedir}/EGL/eglplatform.h
+ fi
+}
+
+
+# Inhibit warnings about files being stripped
+INHIBIT_PACKAGE_DEBUG_SPLIT = "1"
+INHIBIT_PACKAGE_STRIP = "1"
+INHIBIT_SYSROOT_STRIP = "1"
+
+RREPLACES_${PN} = "libegl libgles1 libglesv1-cm1 libgles2 libglesv2-2"
+RPROVIDES_${PN} = "libegl libgles1 libglesv1-cm1 libgles2 libglesv2-2"
+RCONFLICTS_${PN} = "libegl libgles1 libglesv1-cm1 libgles2 libglesv2-2"
+
+# These libraries shouldn't get installed in world builds unless something
+# explicitly depends upon them.
+EXCLUDE_FROM_WORLD = "1"
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali.bb b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali.bb
new file mode 100644
index 0000000..327f8f0
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali.bb
@@ -0,0 +1,49 @@
+SUMMARY = "A Mali 400 Linux Kernel module"
+SECTION = "kernel/modules"
+
+LICENSE = "GPLv2"
+LIC_FILES_CHKSUM = " \
+ file://linux/license/gpl/mali_kernel_license.h;md5=436192a2c5cfd47df0ad1987dffc4ae6 \
+ "
+
+PV = "r8p0-01rel0"
+
+SRC_URI = " \
+ https://developer.arm.com/-/media/Files/downloads/mali-drivers/kernel/mali-utgard-gpu/DX910-SW-99002-${PV}.tgz \
+ file://0001-Change-Makefile-to-be-compatible-with-Yocto.patch \
+ file://0002-staging-mali-r8p0-01rel0-Add-the-ZYNQ-ZYNQMP-platfor.patch \
+ file://0003-staging-mali-r8p0-01rel0-Remove-unused-trace-macros.patch \
+ file://0004-staging-mali-r8p0-01rel0-Don-t-include-mali_read_phy.patch \
+ file://0005-linux-mali_kernel_linux.c-Handle-clock-when-probed-a.patch \
+ file://0006-arm.c-global-variable-dma_ops-is-removed-from-the-ke.patch \
+ file://0007-Replace-__GFP_REPEAT-by-__GFP_RETRY_MAYFAIL.patch \
+ file://0008-mali_internal_sync-Rename-wait_queue_t-with-wait_que.patch \
+ file://0009-mali_memory_swap_alloc.c-Rename-global_page_state-wi.patch \
+ file://0010-common-mali_pm.c-Add-PM-runtime-barrier-after-removi.patch \
+ file://0011-linux-mali_kernel_linux.c-Enable-disable-clock-for-r.patch\
+ "
+SRC_URI[md5sum] = "8f04ae86957fd56197ad5a9d017b84ff"
+SRC_URI[sha256sum] = "bfd14fa3f75a71d4ba313534e651ca1c58dc354e882c0b39867e335882a06350"
+
+inherit module
+
+do_make_scripts[depends] += "virtual/kernel:do_unpack"
+
+S = "${WORKDIR}/DX910-SW-99002-${PV}/driver/src/devicedrv/mali"
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE_zynqmpeg = "zynqmpeg"
+COMPATIBLE_MACHINE_zynqmpev = "zynqmpev"
+
+PACKAGE_ARCH = "${SOC_FAMILY}${SOC_VARIANT}"
+
+EXTRA_OEMAKE = 'KDIR="${STAGING_KERNEL_DIR}" \
+ ARCH="${ARCH}" \
+ BUILD=release \
+ MALI_PLATFORM="arm" \
+ USING_DT=1 \
+ MALI_SHARED_INTERRUPTS=1 \
+ CROSS_COMPILE="${TARGET_PREFIX}" \
+ O=${STAGING_KERNEL_BUILDDIR} \
+ MALI_QUIET=1 \
+ '
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0001-Change-Makefile-to-be-compatible-with-Yocto.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0001-Change-Makefile-to-be-compatible-with-Yocto.patch
new file mode 100644
index 0000000..e5eeb19
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0001-Change-Makefile-to-be-compatible-with-Yocto.patch
@@ -0,0 +1,47 @@
+From 6d283b9aa3f7fb761da4cb076b47a62275fc4caa Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Date: Tue, 21 Nov 2017 03:57:25 -0800
+Subject: [PATCH 1/9] Change Makefile to be compatible with Yocto
+
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
+Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Upstream Status: Inappropriate [Xilinx specific]
+---
+ driver/src/devicedrv/mali/Makefile | 11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/driver/src/devicedrv/mali/Makefile b/driver/src/devicedrv/mali/Makefile
+index 5a259fe..a6dd94c 100644
+--- Makefile
++++ b/Makefile
+@@ -89,7 +89,11 @@ endif
+ # Define host system directory
+ KDIR-$(shell uname -m):=/lib/modules/$(shell uname -r)/build
+
+-include $(KDIR)/.config
++ifeq ($(O),)
++ include $(KDIR)/.config
++else
++ include $(O)/.config
++endif
+
+ ifeq ($(ARCH), arm)
+ # when compiling for ARM we're cross compiling
+@@ -204,9 +208,12 @@ EXTRA_DEFINES += -DMALI_MEM_SWAP_TRACKING=1
+ endif
+
+ all: $(UMP_SYMVERS_FILE)
+- $(MAKE) ARCH=$(ARCH) -C $(KDIR) M=$(CURDIR) modules
++ $(MAKE) ARCH=$(ARCH) -C $(KDIR) M=$(CURDIR) O=$(O) modules
+ @rm $(FILES_PREFIX)__malidrv_build_info.c $(FILES_PREFIX)__malidrv_build_info.o
+
++modules_install:
++ $(MAKE) ARCH=$(ARCH) -C $(KDIR) M=$(CURDIR) modules_install
++
+ clean:
+ $(MAKE) ARCH=$(ARCH) -C $(KDIR) M=$(CURDIR) clean
+
+--
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0002-staging-mali-r8p0-01rel0-Add-the-ZYNQ-ZYNQMP-platfor.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0002-staging-mali-r8p0-01rel0-Add-the-ZYNQ-ZYNQMP-platfor.patch
new file mode 100644
index 0000000..0a7b673
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0002-staging-mali-r8p0-01rel0-Add-the-ZYNQ-ZYNQMP-platfor.patch
@@ -0,0 +1,52 @@
+From f27aab2b0e4d5dea9b5a0e4648c142257940c428 Mon Sep 17 00:00:00 2001
+From: Hyun Kwon <hyun.kwon@xilinx.com>
+Date: Thu, 25 Jun 2015 17:14:42 -0700
+Subject: [PATCH 2/9] staging: mali: r8p0-01rel0: Add the ZYNQ/ZYNQMP platform
+
+Add the number of PP cores that is required for Zynq/ZynqMP configuration.
+
+Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
+Signed-off-by: Michal Simek <michal.simek@xilinx.com>
+Upstream Status: Inappropriate [Xilinx specific]
+---
+ driver/src/devicedrv/mali/platform/arm/arm.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/driver/src/devicedrv/mali/platform/arm/arm.c b/driver/src/devicedrv/mali/platform/arm/arm.c
+index 4e09aca..fac99bc 100644
+--- platform/arm/arm.c
++++ b/platform/arm/arm.c
+@@ -261,6 +261,10 @@ static struct mali_gpu_device_data mali_gpu_data = {
+ .dedicated_mem_start = 0x80000000, /* Physical start address (use 0xD0000000 for old indirect setup) */
+ .dedicated_mem_size = 0x10000000, /* 256MB */
+ #endif
++#if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_ARCH_ZYNQMP)
++ .fb_start = 0x00000000,
++ .fb_size = 0xfffff000,
++#else
+ #if defined(CONFIG_ARM64)
+ /* Some framebuffer drivers get the framebuffer dynamically, such as through GEM,
+ * in which the memory resource can't be predicted in advance.
+@@ -271,6 +275,7 @@ static struct mali_gpu_device_data mali_gpu_data = {
+ .fb_start = 0xe0000000,
+ .fb_size = 0x01000000,
+ #endif
++#endif /* !defined(CONFIG_ARCH_ZYNQ) && !defined(CONFIG_ARCH_ZYNQMP) */
+ .control_interval = 1000, /* 1000ms */
+ .utilization_callback = mali_gpu_utilization_callback,
+ .get_clock_info = NULL,
+@@ -505,6 +510,11 @@ int mali_platform_device_init(struct platform_device *device)
+ mali_write_phys(0xC0010020, 0xA); /* Enable direct memory mapping for FPGA */
+ }
+ }
++#elif defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_ARCH_ZYNQMP)
++
++ MALI_DEBUG_PRINT(4, ("Registering Zynq/ZynqMP Mali-400 device\n"));
++ num_pp_cores = 2;
++
+ #endif
+
+ /* After kernel 3.15 device tree will default set dev
+--
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0003-staging-mali-r8p0-01rel0-Remove-unused-trace-macros.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0003-staging-mali-r8p0-01rel0-Remove-unused-trace-macros.patch
new file mode 100644
index 0000000..98aa6ac
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0003-staging-mali-r8p0-01rel0-Remove-unused-trace-macros.patch
@@ -0,0 +1,35 @@
+From d6e44bbf8d1377f78481f611dec237e8d24baf74 Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Date: Tue, 21 Nov 2017 04:00:27 -0800
+Subject: [PATCH 3/9] staging: mali: r8p0-01rel0: Remove unused trace macros
+
+TRACE_SYSTEM_STRING is not need in each trace file anymore.
+
+Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
+Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Upstream Status: Pending
+---
+ driver/src/devicedrv/mali/linux/mali_linux_trace.h | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/driver/src/devicedrv/mali/linux/mali_linux_trace.h b/driver/src/devicedrv/mali/linux/mali_linux_trace.h
+index 7f0b19d..33cb1ca 100644
+--- linux/mali_linux_trace.h
++++ b/linux/mali_linux_trace.h
+@@ -13,13 +13,11 @@
+
+ #include <linux/types.h>
+
+-#include <linux/stringify.h>
+ #include <linux/tracepoint.h>
+
+ #undef TRACE_SYSTEM
+ #define TRACE_SYSTEM mali
+ #ifndef TRACEPOINTS_ENABLED
+-#define TRACE_SYSTEM_STRING __stringfy(TRACE_SYSTEM)
+ #endif
+ #define TRACE_INCLUDE_PATH .
+ #define TRACE_INCLUDE_FILE mali_linux_trace
+--
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0004-staging-mali-r8p0-01rel0-Don-t-include-mali_read_phy.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0004-staging-mali-r8p0-01rel0-Don-t-include-mali_read_phy.patch
new file mode 100644
index 0000000..c5c4967
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0004-staging-mali-r8p0-01rel0-Don-t-include-mali_read_phy.patch
@@ -0,0 +1,47 @@
+From 2f5e8944357f43fbde4cb642c6ee4a699c88efb5 Mon Sep 17 00:00:00 2001
+From: Hyun Kwon <hyun.kwon@xilinx.com>
+Date: Wed, 29 Jun 2016 09:14:37 -0700
+Subject: [PATCH 4/9] staging: mali: r8p0-01rel0: Don't include
+ mali_read_phys() for zynq/zynqmp
+
+mali_read_phys() is not used with CONFIG_ARCH_ZYNQ and CONFIG_ARCH_ZYNQMP.
+
+Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
+Upstream Status: Inappropriate [Xilinx specific]
+---
+ driver/src/devicedrv/mali/platform/arm/arm.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/driver/src/devicedrv/mali/platform/arm/arm.c b/driver/src/devicedrv/mali/platform/arm/arm.c
+index fac99bc..62f9be6 100644
+--- platform/arm/arm.c
++++ b/platform/arm/arm.c
+@@ -38,7 +38,9 @@
+ static int mali_core_scaling_enable = 0;
+
+ void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
++#if !(defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_ARCH_ZYNQMP))
+ static u32 mali_read_phys(u32 phys_addr);
++#endif
+ #if defined(CONFIG_ARCH_REALVIEW)
+ static void mali_write_phys(u32 phys_addr, u32 value);
+ #endif
+@@ -578,6 +580,7 @@ int mali_platform_device_deinit(struct platform_device *device)
+
+ #endif /* CONFIG_MALI_DT */
+
++#if !(defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_ARCH_ZYNQMP))
+ static u32 mali_read_phys(u32 phys_addr)
+ {
+ u32 phys_addr_page = phys_addr & 0xFFFFE000;
+@@ -592,6 +595,7 @@ static u32 mali_read_phys(u32 phys_addr)
+
+ return ret;
+ }
++#endif
+
+ #if defined(CONFIG_ARCH_REALVIEW)
+ static void mali_write_phys(u32 phys_addr, u32 value)
+--
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0005-linux-mali_kernel_linux.c-Handle-clock-when-probed-a.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0005-linux-mali_kernel_linux.c-Handle-clock-when-probed-a.patch
new file mode 100644
index 0000000..3d78460
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0005-linux-mali_kernel_linux.c-Handle-clock-when-probed-a.patch
@@ -0,0 +1,90 @@
+From e67e20ec6ff0c9720d87844270421453c738066a Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Date: Thu, 16 Feb 2017 12:15:58 -0800
+Subject: [PATCH 5/9] linux/mali_kernel_linux.c: Handle clock when probed and
+ removed
+
+This patch will handle the clock through clock
+specifier for GPU PP0 and PP1.
+
+Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Upstream Status: Inappropriate [Xilinx specific]
+---
+ .../src/devicedrv/mali/linux/mali_kernel_linux.c | 40 +++++++++++++++++++++-
+ 1 file changed, 39 insertions(+), 1 deletion(-)
+
+diff --git a/driver/src/devicedrv/mali/linux/mali_kernel_linux.c b/driver/src/devicedrv/mali/linux/mali_kernel_linux.c
+index d7893a3..f15fb56 100644
+--- linux/mali_kernel_linux.c
++++ b/linux/mali_kernel_linux.c
+@@ -45,6 +45,14 @@
+ #if defined(CONFIG_MALI400_INTERNAL_PROFILING)
+ #include "mali_profiling_internal.h"
+ #endif
++
++#if defined(CONFIG_ARCH_ZYNQMP)
++/* Initialize variables for clocks */
++struct clk *clk_gpu;
++struct clk *clk_gpu_pp0;
++struct clk *clk_gpu_pp1;
++#endif
++
+ #if defined(CONFIG_MALI400_PROFILING) && defined(CONFIG_MALI_DVFS)
+ #include "mali_osk_profiling.h"
+ #include "mali_dvfs_policy.h"
+@@ -580,7 +588,23 @@ static int mali_probe(struct platform_device *pdev)
+ }
+ #endif
+
+-
++#if defined(CONFIG_ARCH_ZYNQMP)
++ /* Initialize clocks for GPU and PP */
++ clk_gpu = devm_clk_get(&pdev->dev, "gpu");
++ if (IS_ERR(clk_gpu))
++ return PTR_ERR(clk_gpu);
++ clk_prepare_enable(clk_gpu);
++
++ clk_gpu_pp0 = devm_clk_get(&pdev->dev, "gpu_pp0");
++ if (IS_ERR(clk_gpu_pp0))
++ return PTR_ERR(clk_gpu_pp0);
++ clk_prepare_enable(clk_gpu_pp0);
++
++ clk_gpu_pp1 = devm_clk_get(&pdev->dev, "gpu_pp1");
++ if (IS_ERR(clk_gpu_pp1))
++ return PTR_ERR(clk_gpu_pp1);
++ clk_prepare_enable(clk_gpu_pp1);
++#endif
+ if (_MALI_OSK_ERR_OK == _mali_osk_wq_init()) {
+ /* Initialize the Mali GPU HW specified by pdev */
+ if (_MALI_OSK_ERR_OK == mali_initialize_subsystems()) {
+@@ -608,6 +632,12 @@ static int mali_probe(struct platform_device *pdev)
+ _mali_osk_wq_term();
+ }
+
++#if defined(CONFIG_ARCH_ZYNQMP)
++ clk_disable_unprepare(clk_gpu);
++ clk_disable_unprepare(clk_gpu_pp0);
++ clk_disable_unprepare(clk_gpu_pp1);
++#endif
++
+ #ifdef CONFIG_MALI_DEVFREQ
+ mali_devfreq_term(mdev);
+ devfreq_init_failed:
+@@ -673,6 +703,14 @@ static int mali_remove(struct platform_device *pdev)
+ mali_platform_device_deinit(mali_platform_device);
+ #endif
+ mali_platform_device = NULL;
++
++#if defined(CONFIG_ARCH_ZYNQMP)
++ /* Remove clock */
++ clk_disable_unprepare(clk_gpu);
++ clk_disable_unprepare(clk_gpu_pp0);
++ clk_disable_unprepare(clk_gpu_pp1);
++#endif
++
+ return 0;
+ }
+
+--
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0006-arm.c-global-variable-dma_ops-is-removed-from-the-ke.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0006-arm.c-global-variable-dma_ops-is-removed-from-the-ke.patch
new file mode 100644
index 0000000..3e1745f
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0006-arm.c-global-variable-dma_ops-is-removed-from-the-ke.patch
@@ -0,0 +1,35 @@
+From ed7242238151c12029c566d1974058c579d8ae3d Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Date: Wed, 25 Jan 2017 10:00:33 -0800
+Subject: [PATCH 6/9] arm.c: global variable dma_ops is removed from the kernel
+ 4.7
+
+Refer kernel commit 1dccb598df549d892b6450c261da54cdd7af44b4, the global
+dma_ops variable and the special-casing for ACPI is removed , and just
+returns the dma ops that got set for the device, or the dummy_dma_ops
+if none were present.
+
+Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Upstream Status: Pending
+---
+ driver/src/devicedrv/mali/platform/arm/arm.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/driver/src/devicedrv/mali/platform/arm/arm.c b/driver/src/devicedrv/mali/platform/arm/arm.c
+index 62f9be6..57ca989 100644
+--- platform/arm/arm.c
++++ b/platform/arm/arm.c
+@@ -529,8 +529,9 @@ int mali_platform_device_init(struct platform_device *device)
+ */
+ if (!device->dev.dma_mask)
+ device->dev.dma_mask = &device->dev.coherent_dma_mask;
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+ device->dev.archdata.dma_ops = dma_ops;
+-
++#endif
+ err = platform_device_add_data(device, &mali_gpu_data, sizeof(mali_gpu_data));
+
+ if (0 == err) {
+--
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0007-Replace-__GFP_REPEAT-by-__GFP_RETRY_MAYFAIL.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0007-Replace-__GFP_REPEAT-by-__GFP_RETRY_MAYFAIL.patch
new file mode 100644
index 0000000..6e5f544
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0007-Replace-__GFP_REPEAT-by-__GFP_RETRY_MAYFAIL.patch
@@ -0,0 +1,54 @@
+From a8190cd3b346633016d1c0096ef73e0e1ceef438 Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Date: Tue, 5 Dec 2017 09:25:15 -0800
+Subject: [PATCH 7/9] Replace __GFP_REPEAT by __GFP_RETRY_MAYFAIL
+
+Refer kernel patch dcda9b04713c3f6ff0875652924844fae28286ea
+which replaces with a useful semantic
+
+Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Upstream-Status: Pending
+---
+ driver/src/devicedrv/mali/linux/mali_memory_os_alloc.c | 4 ++++
+ driver/src/devicedrv/mali/linux/mali_osk_notification.c | 7 ++++++-
+ 2 files changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/driver/src/devicedrv/mali/linux/mali_memory_os_alloc.c b/driver/src/devicedrv/mali/linux/mali_memory_os_alloc.c
+index 5fe1270..1602371 100644
+--- linux/mali_memory_os_alloc.c
++++ b/linux/mali_memory_os_alloc.c
+@@ -202,7 +202,11 @@ int mali_mem_os_alloc_pages(mali_mem_os_mem *os_mem, u32 size)
+ /* Allocate new pages, if needed. */
+ for (i = 0; i < remaining; i++) {
+ dma_addr_t dma_addr;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++ gfp_t flags = __GFP_ZERO | __GFP_RETRY_MAYFAIL | __GFP_NOWARN | __GFP_COLD;
++#else
+ gfp_t flags = __GFP_ZERO | __GFP_REPEAT | __GFP_NOWARN | __GFP_COLD;
++#endif
+ int err;
+
+ #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_LPAE)
+diff --git a/driver/src/devicedrv/mali/linux/mali_osk_notification.c b/driver/src/devicedrv/mali/linux/mali_osk_notification.c
+index b22fe68..d0c302a 100644
+--- linux/mali_osk_notification.c
++++ b/linux/mali_osk_notification.c
+@@ -55,9 +55,14 @@ _mali_osk_notification_t *_mali_osk_notification_create(u32 type, u32 size)
+ {
+ /* OPT Recycling of notification objects */
+ _mali_osk_notification_wrapper_t *notification;
+-
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++ notification = (_mali_osk_notification_wrapper_t *)kmalloc(sizeof(_mali_osk_notification_wrapper_t) + size,
++ GFP_KERNEL | __GFP_HIGH | __GFP_RETRY_MAYFAIL);
++#else
+ notification = (_mali_osk_notification_wrapper_t *)kmalloc(sizeof(_mali_osk_notification_wrapper_t) + size,
+ GFP_KERNEL | __GFP_HIGH | __GFP_REPEAT);
++#endif
++
+ if (NULL == notification) {
+ MALI_DEBUG_PRINT(1, ("Failed to create a notification object\n"));
+ return NULL;
+--
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0008-mali_internal_sync-Rename-wait_queue_t-with-wait_que.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0008-mali_internal_sync-Rename-wait_queue_t-with-wait_que.patch
new file mode 100644
index 0000000..592fea0
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0008-mali_internal_sync-Rename-wait_queue_t-with-wait_que.patch
@@ -0,0 +1,108 @@
+From 717d7899f6d8048c6b88b3c52e8a9c8afbddbb65 Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Date: Tue, 5 Dec 2017 09:48:42 -0800
+Subject: [PATCH 8/9] mali_internal_sync: Rename wait_queue_t with
+ wait_queue_entry_t
+
+Refer kernel patch ac6424b981bce1c4bc55675c6ce11bfe1bbfa64f
+and 2055da which replaces the struct name
+
+Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Upstream-Status: Pending
+---
+ .../src/devicedrv/mali/linux/mali_internal_sync.c | 27 ++++++++++++++++++++--
+ .../src/devicedrv/mali/linux/mali_internal_sync.h | 4 ++++
+ 2 files changed, 29 insertions(+), 2 deletions(-)
+
+diff --git a/driver/src/devicedrv/mali/linux/mali_internal_sync.c b/driver/src/devicedrv/mali/linux/mali_internal_sync.c
+index 1f2574e..957a056 100644
+--- linux/mali_internal_sync.c
++++ b/linux/mali_internal_sync.c
+@@ -121,8 +121,13 @@ static void mali_internal_sync_fence_add_fence(struct mali_internal_sync_fence *
+ }
+ #endif
+
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 13, 0)
++static int mali_internal_sync_fence_wake_up_wq(wait_queue_entry_t *curr, unsigned mode,
++ int wake_flags, void *key)
++#else
+ static int mali_internal_sync_fence_wake_up_wq(wait_queue_t *curr, unsigned mode,
+ int wake_flags, void *key)
++#endif
+ {
+ struct mali_internal_sync_fence_waiter *wait;
+ MALI_IGNORE(mode);
+@@ -130,8 +135,12 @@ static int mali_internal_sync_fence_wake_up_wq(wait_queue_t *curr, unsigned mode
+ MALI_IGNORE(key);
+
+ wait = container_of(curr, struct mali_internal_sync_fence_waiter, work);
+- list_del_init(&wait->work.task_list);
+
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 13, 0)
++ list_del_init(&wait->work.entry);
++#else
++ list_del_init(&wait->work.task_list);
++#endif
+ wait->callback(wait->work.private, wait);
+ return 1;
+ }
+@@ -498,7 +507,11 @@ void mali_internal_sync_fence_waiter_init(struct mali_internal_sync_fence_waiter
+ MALI_DEBUG_ASSERT_POINTER(waiter);
+ MALI_DEBUG_ASSERT_POINTER(callback);
+
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 13, 0)
++ INIT_LIST_HEAD(&waiter->work.entry);
++#else
+ INIT_LIST_HEAD(&waiter->work.task_list);
++#endif
+ waiter->callback = callback;
+ }
+
+@@ -560,8 +573,13 @@ int mali_internal_sync_fence_wait_async(struct mali_internal_sync_fence *sync_fe
+ spin_lock_irqsave(&sync_fence->wq.lock, flags);
+ err = sync_fence->fence->ops->signaled(sync_fence->fence);
+
+- if (0 == err)
++ if (0 == err){
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 13, 0)
++ __add_wait_queue_entry_tail(&sync_fence->wq, &waiter->work);
++#else
+ __add_wait_queue_tail(&sync_fence->wq, &waiter->work);
++#endif
++ }
+ spin_unlock_irqrestore(&sync_fence->wq.lock, flags);
+
+ return err;
+@@ -578,8 +596,13 @@ int mali_internal_sync_fence_cancel_async(struct mali_internal_sync_fence *sync_
+ MALI_DEBUG_ASSERT_POINTER(waiter);
+
+ spin_lock_irqsave(&sync_fence->wq.lock, flags);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 13, 0)
++ if (!list_empty(&waiter->work.entry))
++ list_del_init(&waiter->work.entry);
++#else
+ if (!list_empty(&waiter->work.task_list))
+ list_del_init(&waiter->work.task_list);
++#endif
+ else
+ ret = -ENOENT;
+ spin_unlock_irqrestore(&sync_fence->wq.lock, flags);
+diff --git a/driver/src/devicedrv/mali/linux/mali_internal_sync.h b/driver/src/devicedrv/mali/linux/mali_internal_sync.h
+index a5655c7..70f29f9 100644
+--- linux/mali_internal_sync.h
++++ b/linux/mali_internal_sync.h
+@@ -112,7 +112,11 @@ typedef void (*mali_internal_sync_callback_t)(struct mali_internal_sync_fence *s
+ struct mali_internal_sync_fence_waiter *waiter);
+
+ struct mali_internal_sync_fence_waiter {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 13, 0)
++ wait_queue_entry_t work;
++#else
+ wait_queue_t work;
++#endif
+ mali_internal_sync_callback_t callback;
+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0)
+ #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 10, 0)
+--
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0009-mali_memory_swap_alloc.c-Rename-global_page_state-wi.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0009-mali_memory_swap_alloc.c-Rename-global_page_state-wi.patch
new file mode 100644
index 0000000..3445512
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0009-mali_memory_swap_alloc.c-Rename-global_page_state-wi.patch
@@ -0,0 +1,48 @@
+From 478de18bf513ecad419d25981e7b66c78126752c Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Date: Tue, 5 Dec 2017 09:58:36 -0800
+Subject: [PATCH 9/9] mali_memory_swap_alloc.c: Rename global_page_state with
+ global_zone_page_state
+
+Refer Kernel commit c41f012ade0b95b0a6e25c7150673e0554736165
+Which simply renames without any functional changes
+
+Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Upstream-Status: Pending
+---
+ driver/src/devicedrv/mali/linux/mali_memory_swap_alloc.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/driver/src/devicedrv/mali/linux/mali_memory_swap_alloc.c b/driver/src/devicedrv/mali/linux/mali_memory_swap_alloc.c
+index a54faca..e122b4c 100644
+--- linux/mali_memory_swap_alloc.c
++++ b/linux/mali_memory_swap_alloc.c
+@@ -248,7 +248,11 @@ static void mali_mem_swap_swapped_bkend_pool_shrink(_mali_mem_swap_pool_shrink_t
+ }
+
+ /* Get system free pages number. */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++ system_free_size = global_zone_page_state(NR_FREE_PAGES) * PAGE_SIZE;
++#else
+ system_free_size = global_page_state(NR_FREE_PAGES) * PAGE_SIZE;
++#endif
+ last_gpu_utilization = _mali_ukk_utilization_gp_pp();
+
+ if ((last_gpu_utilization < gpu_utilization_threshold_value)
+@@ -575,8 +579,12 @@ int mali_mem_swap_alloc_pages(mali_mem_swap *swap_mem, u32 size, u32 *bkend_idx)
+
+ list_add_tail(&m_page->list, &swap_mem->pages);
+ }
+-
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++ system_free_size = global_zone_page_state(NR_FREE_PAGES) * PAGE_SIZE;
++#else
+ system_free_size = global_page_state(NR_FREE_PAGES) * PAGE_SIZE;
++#endif
++
+
+ if ((system_free_size < mali_mem_swap_out_threshold_value)
+ && (mem_backend_swapped_pool_size > (mali_mem_swap_out_threshold_value >> 2))
+--
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0010-common-mali_pm.c-Add-PM-runtime-barrier-after-removi.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0010-common-mali_pm.c-Add-PM-runtime-barrier-after-removi.patch
new file mode 100644
index 0000000..98a86c8
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0010-common-mali_pm.c-Add-PM-runtime-barrier-after-removi.patch
@@ -0,0 +1,31 @@
+From 58e2c55176f1a146781430b2a570c8ce5f80d426 Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Date: Mon, 28 Aug 2017 09:40:37 -0700
+Subject: [PATCH] common/mali_pm.c: Add PM runtime barrier after removing
+ suspend
+
+Runtime PM suspend "put" results in addition of PM suspend
+API in work queue. This barrier API will remove it from
+the work queue.
+
+Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Upstream-Status: Pending
+---
+ driver/src/devicedrv/mali/common/mali_pm.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/driver/src/devicedrv/mali/common/mali_pm.c b/driver/src/devicedrv/mali/common/mali_pm.c
+index 858c689..62a1e5f 100644
+--- common/mali_pm.c
++++ b/common/mali_pm.c
+@@ -301,6 +301,7 @@ void mali_pm_init_end(void)
+ }
+
+ _mali_osk_pm_dev_ref_put();
++ _mali_osk_pm_dev_barrier();
+ }
+
+ void mali_pm_update_sync(void)
+--
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0011-linux-mali_kernel_linux.c-Enable-disable-clock-for-r.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0011-linux-mali_kernel_linux.c-Enable-disable-clock-for-r.patch
new file mode 100644
index 0000000..38ab404
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0011-linux-mali_kernel_linux.c-Enable-disable-clock-for-r.patch
@@ -0,0 +1,153 @@
+From aeff13ad9e9ef73172a9325f669aefd3c0403dbb Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Date: Wed, 21 Feb 2018 16:52:15 -0800
+Subject: [PATCH] linux/mali_kernel_linux.c: Enable/disable clock for runtime
+ resume/suspend
+
+Enable/Disable the clock for GP,PP0 and PP1 during runtime
+resume/suspend.
+
+Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Reviewed-by: Hyun Kwon <hyunk@xilinx.com>
+Upstream Status: Inappropriate [Xilinx specific]
+---
+ .../src/devicedrv/mali/linux/mali_kernel_linux.c | 65 ++++++++++++++++++----
+ 1 file changed, 54 insertions(+), 11 deletions(-)
+
+diff --git a/driver/src/devicedrv/mali/linux/mali_kernel_linux.c b/driver/src/devicedrv/mali/linux/mali_kernel_linux.c
+index f15fb56..e61f33b 100644
+--- linux/mali_kernel_linux.c
++++ b/linux/mali_kernel_linux.c
+@@ -51,6 +51,7 @@
+ struct clk *clk_gpu;
+ struct clk *clk_gpu_pp0;
+ struct clk *clk_gpu_pp1;
++mali_bool clk_enabled;
+ #endif
+
+ #if defined(CONFIG_MALI400_PROFILING) && defined(CONFIG_MALI_DVFS)
+@@ -281,6 +282,46 @@ struct file_operations mali_fops = {
+ .mmap = mali_mmap
+ };
+
++static int mali_enable_clk(void)
++{
++#if defined(CONFIG_ARCH_ZYNQMP)
++ int err = 0;
++
++ if (clk_enabled)
++ return 0;
++
++ clk_enabled = MALI_TRUE;
++ err = clk_prepare_enable(clk_gpu);
++ if (err) {
++ MALI_PRINT_ERROR(("Could not enable clock for GP\n\r"));
++ return err;
++ }
++ err = clk_prepare_enable(clk_gpu_pp0);
++ if (err) {
++ MALI_PRINT_ERROR(("Could not enable clock for PP0\n\r"));
++ return err;
++ }
++ err = clk_prepare_enable(clk_gpu_pp1);
++ if (err) {
++ MALI_PRINT_ERROR(("Could not enable clock for PP1\n\r"));
++ return err;
++ }
++#endif
++ return 0;
++}
++
++static void mali_disable_clk(void)
++{
++#if defined(CONFIG_ARCH_ZYNQMP)
++ if (clk_enabled) {
++ clk_enabled = MALI_FALSE;
++ clk_disable_unprepare(clk_gpu);
++ clk_disable_unprepare(clk_gpu_pp0);
++ clk_disable_unprepare(clk_gpu_pp1);
++ }
++#endif
++}
++
+ #if MALI_ENABLE_CPU_CYCLES
+ void mali_init_cpu_time_counters(int reset, int enable_divide_by_64)
+ {
+@@ -593,18 +634,19 @@ static int mali_probe(struct platform_device *pdev)
+ clk_gpu = devm_clk_get(&pdev->dev, "gpu");
+ if (IS_ERR(clk_gpu))
+ return PTR_ERR(clk_gpu);
+- clk_prepare_enable(clk_gpu);
+
+ clk_gpu_pp0 = devm_clk_get(&pdev->dev, "gpu_pp0");
+ if (IS_ERR(clk_gpu_pp0))
+ return PTR_ERR(clk_gpu_pp0);
+- clk_prepare_enable(clk_gpu_pp0);
+
+ clk_gpu_pp1 = devm_clk_get(&pdev->dev, "gpu_pp1");
+ if (IS_ERR(clk_gpu_pp1))
+ return PTR_ERR(clk_gpu_pp1);
+- clk_prepare_enable(clk_gpu_pp1);
+ #endif
++
++ err = mali_enable_clk();
++ if (err)
++ return err;
+ if (_MALI_OSK_ERR_OK == _mali_osk_wq_init()) {
+ /* Initialize the Mali GPU HW specified by pdev */
+ if (_MALI_OSK_ERR_OK == mali_initialize_subsystems()) {
+@@ -632,11 +674,6 @@ static int mali_probe(struct platform_device *pdev)
+ _mali_osk_wq_term();
+ }
+
+-#if defined(CONFIG_ARCH_ZYNQMP)
+- clk_disable_unprepare(clk_gpu);
+- clk_disable_unprepare(clk_gpu_pp0);
+- clk_disable_unprepare(clk_gpu_pp1);
+-#endif
+
+ #ifdef CONFIG_MALI_DEVFREQ
+ mali_devfreq_term(mdev);
+@@ -644,6 +681,7 @@ devfreq_init_failed:
+ mali_pm_metrics_term(mdev);
+ pm_metrics_init_failed:
+ clk_disable_unprepare(mdev->clock);
++ mali_disable_clk();
+ clock_prepare_failed:
+ clk_put(mdev->clock);
+ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) && defined(CONFIG_OF) \
+@@ -706,9 +744,7 @@ static int mali_remove(struct platform_device *pdev)
+
+ #if defined(CONFIG_ARCH_ZYNQMP)
+ /* Remove clock */
+- clk_disable_unprepare(clk_gpu);
+- clk_disable_unprepare(clk_gpu_pp0);
+- clk_disable_unprepare(clk_gpu_pp1);
++ mali_disable_clk();
+ #endif
+
+ return 0;
+@@ -816,6 +852,8 @@ static int mali_driver_runtime_suspend(struct device *dev)
+ devfreq_suspend_device(mdev->devfreq);
+ #endif
+
++ mali_disable_clk();
++
+ return 0;
+ } else {
+ return -EBUSY;
+@@ -824,6 +862,11 @@ static int mali_driver_runtime_suspend(struct device *dev)
+
+ static int mali_driver_runtime_resume(struct device *dev)
+ {
++ int err ;
++
++ err = mali_enable_clk();
++ if (err)
++ return err;
+ #ifdef CONFIG_MALI_DEVFREQ
+ struct mali_device *mdev = dev_get_drvdata(dev);
+ if (!mdev)
+--
+2.7.4
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc/0001-src-drmmode_xilinx-Add-the-dumb-gem-support-for-Xili.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc/0001-src-drmmode_xilinx-Add-the-dumb-gem-support-for-Xili.patch
new file mode 100644
index 0000000..bf2169e
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc/0001-src-drmmode_xilinx-Add-the-dumb-gem-support-for-Xili.patch
@@ -0,0 +1,141 @@
+From 630a8ea035fe2f075f6ea7f4bad0928f5b541c80 Mon Sep 17 00:00:00 2001
+From: Hyun Kwon <hyun.kwon@xilinx.com>
+Date: Wed, 21 Jan 2015 11:53:19 -0800
+Subject: [PATCH] src: drmmode_xilinx: Add the dumb gem support for Xilinx
+
+Add the dumb gem support for Xilinx
+
+Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
+Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
+Upstream-Status: Pending
+---
+ src/Makefile.am | 3 +-
+ src/armsoc_driver.c | 1 +
+ src/drmmode_driver.h | 1 +
+ src/drmmode_xilinx/drmmode_xilinx.c | 76 +++++++++++++++++++++++++++++++++++++
+ 4 files changed, 80 insertions(+), 1 deletion(-)
+ create mode 100644 src/drmmode_xilinx/drmmode_xilinx.c
+
+diff --git a/src/Makefile.am b/src/Makefile.am
+index 3b2601927c..db5f110fb2 100644
+--- a/src/Makefile.am
++++ b/src/Makefile.am
+@@ -43,7 +43,8 @@ armsoc_drv_ladir = @moduledir@/drivers
+ DRMMODE_SRCS = drmmode_exynos/drmmode_exynos.c \
+ drmmode_pl111/drmmode_pl111.c \
+ drmmode_kirin/drmmode_kirin.c \
+- drmmode_sti/drmmode_sti.c
++ drmmode_sti/drmmode_sti.c \
++ drmmode_xilinx/drmmode_xilinx.c
+
+
+ armsoc_drv_la_SOURCES = \
+diff --git a/src/armsoc_driver.c b/src/armsoc_driver.c
+index 83e74a7ed1..3ace3c7be5 100644
+--- a/src/armsoc_driver.c
++++ b/src/armsoc_driver.c
+@@ -737,6 +737,7 @@ static struct drmmode_interface *get_drmmode_implementation(int drm_fd)
+ &pl111_interface,
+ &kirin_interface,
+ &sti_interface,
++ &xilinx_interface,
+ };
+ int i;
+
+diff --git a/src/drmmode_driver.h b/src/drmmode_driver.h
+index 879fc60ddc..18245d591a 100644
+--- a/src/drmmode_driver.h
++++ b/src/drmmode_driver.h
+@@ -106,6 +106,7 @@ extern struct drmmode_interface exynos_interface;
+ extern struct drmmode_interface pl111_interface;
+ extern struct drmmode_interface kirin_interface;
+ extern struct drmmode_interface sti_interface;
++extern struct drmmode_interface xilinx_interface;
+
+
+ #endif
+diff --git a/src/drmmode_xilinx/drmmode_xilinx.c b/src/drmmode_xilinx/drmmode_xilinx.c
+new file mode 100644
+index 0000000000..f4faceb0b4
+--- /dev/null
++++ b/src/drmmode_xilinx/drmmode_xilinx.c
+@@ -0,0 +1,76 @@
++/*
++ * Xilinx X11 ARMSOC driver
++ *
++ * Author: Hyun Woo Kwon <hyun.kwon@xilinx.com>
++ *
++ * Copyright (C) 2014 Xilinx, Inc.
++ *
++ * Based on drmmode_exynos.c
++ *
++ * Copyright © 2013 ARM Limited.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
++ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
++ * SOFTWARE.
++ *
++ */
++
++#include <stdlib.h>
++
++#include <drm.h>
++#include <xf86drm.h>
++
++#include "../drmmode_driver.h"
++
++static int create_custom_gem(int fd, struct armsoc_create_gem *create_gem)
++{
++ struct drm_mode_create_dumb arg;
++ int ret;
++
++ memset(&arg, 0, sizeof(arg));
++ arg.height = create_gem->height;
++ arg.width = create_gem->width;
++ arg.bpp = create_gem->bpp;
++
++ ret = drmIoctl(fd, DRM_IOCTL_MODE_CREATE_DUMB, &arg);
++ if (ret)
++ return ret;
++
++ create_gem->height = arg.height;
++ create_gem->width = arg.width;
++ create_gem->bpp = arg.bpp;
++ create_gem->handle = arg.handle;
++ create_gem->pitch = arg.pitch;
++ create_gem->size = arg.size;
++
++ return 0;
++}
++
++struct drmmode_interface xilinx_interface = {
++ "xlnx" /* name of drm driver */,
++ 1 /* use_page_flip_events */,
++ 1 /* use_early_display */,
++ 0 /* cursor width */,
++ 0 /* cursor_height */,
++ 0 /* cursor padding */,
++ HWCURSOR_API_NONE /* cursor_api */,
++ NULL /* init_plane_for_cursor */,
++ 0 /* vblank_query_supported */,
++ create_custom_gem /* create_custom_gem */,
++};
++
+--
+2.11.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc_git.bb b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc_git.bb
new file mode 100644
index 0000000..7a671fe
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc_git.bb
@@ -0,0 +1,23 @@
+require recipes-graphics/xorg-driver/xorg-driver-video.inc
+
+SUMMARY = "X.Org X server -- Xilinx ARM SOC display driver"
+DESCRIPTION = "Xilinx ARM SOC display driver "
+
+LICENSE = "MIT-X & GPLv2+"
+LIC_FILES_CHKSUM = "file://COPYING;md5=10ce5de3b111315ea652a5f74ec0c602"
+
+DEPENDS += "virtual/libx11 libdrm xf86driproto"
+RDEPENDS_${PN} += "xserver-xorg-module-exa"
+
+PV = "1.4.1+git${SRCPV}"
+
+SRCREV = "8bbdb2ae3bb8ef649999a8da33ddbe11a04763b8"
+SRC_URI = " \
+ git://anongit.freedesktop.org/xorg/driver/xf86-video-armsoc \
+ file://0001-src-drmmode_xilinx-Add-the-dumb-gem-support-for-Xili.patch \
+ "
+
+S = "${WORKDIR}/git"
+
+EXTRA_OECONF = " --enable-maintainer-mode"
+CFLAGS += " -I${STAGING_INCDIR}/xorg "
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-xserver/xserver-xf86-config/zynqmp/xorg.conf b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-xserver/xserver-xf86-config/zynqmp/xorg.conf
new file mode 100644
index 0000000..9ef3946
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-xserver/xserver-xf86-config/zynqmp/xorg.conf
@@ -0,0 +1,27 @@
+Section "InputDevice"
+ Identifier "System Mouse"
+ Driver "mouse"
+ Option "Device" "/dev/input/mouse0"
+EndSection
+
+Section "InputDevice"
+ Identifier "System Keyboard"
+ Driver "kbd"
+ Option "Device" "/dev/input/event0"
+EndSection
+
+Section "Device"
+ Identifier "ZynqMP"
+ Driver "armsoc"
+ Option "DRI2" "true"
+ Option "DRI2_PAGE_FLIP" "false"
+ Option "DRI2_WAIT_VSYNC" "true"
+ Option "SWcursorLCD" "false"
+ Option "DEBUG" "false"
+EndSection
+
+Section "Screen"
+ Identifier "DefaultScreen"
+ Device "ZynqMP"
+ DefaultDepth 16
+EndSection
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-xserver/xserver-xf86-config_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-xserver/xserver-xf86-config_%.bbappend
new file mode 100644
index 0000000..72d991c
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-xserver/xserver-xf86-config_%.bbappend
@@ -0,0 +1 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-microblaze.inc b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-microblaze.inc
new file mode 100644
index 0000000..e23a50e
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-microblaze.inc
@@ -0,0 +1,5 @@
+# MicroBlaze is a uImage target, but its not called 'uImage' instead it is called 'linux.bin.ub'
+python () {
+ if d.getVar('KERNEL_IMAGETYPE', True).endswith('.ub'):
+ d.setVar('DEPENDS', "%s u-boot-mkimage-native" % d.getVar('DEPENDS', True))
+}
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx-dev.bb b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx-dev.bb
new file mode 100644
index 0000000..acb9938
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx-dev.bb
@@ -0,0 +1,18 @@
+# This recipe tracks the 'bleeding edge' linux-xlnx repository.
+# Since this tree is frequently updated, AUTOREV is used to track its contents.
+#
+# To enable this recipe, set PREFERRED_PROVIDER_virtual/kernel = "linux-xlnx-dev"
+
+KBRANCH ?= "master"
+
+# Use the SRCREV for the last tagged revision of linux-xlnx.
+SRCREV ?= '${@oe.utils.conditional("PREFERRED_PROVIDER_virtual/kernel", "linux-xlnx-dev", "${AUTOREV}", "84fb0cc65aae5970471cbc54b0c89009b9b904af", d)}'
+
+# skip version sanity, because the version moves with AUTOREV
+KERNEL_VERSION_SANITY_SKIP = "1"
+
+LINUX_VERSION ?= "4.9+"
+LINUX_VERSION_EXTENSION ?= "-xilinx-dev"
+
+include linux-xlnx.inc
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx.inc b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx.inc
new file mode 100644
index 0000000..7b4f9ac
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx.inc
@@ -0,0 +1,45 @@
+# This version extension should match CONFIG_LOCALVERSION in defconfig
+XILINX_RELEASE_VERSION ?= ""
+LINUX_VERSION_EXTENSION ?= "-xilinx-${XILINX_RELEASE_VERSION}"
+PV = "${LINUX_VERSION}${LINUX_VERSION_EXTENSION}+git${SRCPV}"
+
+# Sources, by default allow for the use of SRCREV pointing to orphaned tags/commits
+KBRANCH ?= ""
+SRCBRANCHARG = "${@['nobranch=1', 'branch=${KBRANCH}'][d.getVar('KBRANCH', True) != '']}"
+
+FILESOVERRIDES_append = ":${XILINX_RELEASE_VERSION}"
+KERNELURI ?= "git://github.com/Xilinx/linux-xlnx.git;protocol=https"
+SRC_URI = "${KERNELURI};${SRCBRANCHARG}"
+
+SRCREV_machine ?= "${SRCREV}"
+
+require recipes-kernel/linux/linux-yocto.inc
+require linux-microblaze.inc
+
+DESCRIPTION = "Xilinx Kernel"
+
+# Force the use of the KBUILD_DEFCONFIG even if some other defconfig was generated in the ${WORKDIR}
+do_kernel_metadata_prepend () {
+ [ -n "${KBUILD_DEFCONFIG}" ] && [ -e ${WORKDIR}/defconfig ] && rm ${WORKDIR}/defconfig
+}
+
+# Default to be only compatible with specific machines or soc families
+COMPATIBLE_MACHINE ?= "^$"
+COMPATIBLE_MACHINE_zynq = ".*"
+COMPATIBLE_MACHINE_zynqmp = ".*"
+COMPATIBLE_MACHINE_microblaze = ".*"
+
+# Use DEFCONFIGs for configuring linux-xlnx kernels
+KCONFIG_MODE ?= "alldefconfig"
+KBUILD_DEFCONFIG_zynqmp = "xilinx_zynqmp_defconfig"
+KBUILD_DEFCONFIG_zynq = "xilinx_zynq_defconfig"
+KBUILD_DEFCONFIG_microblaze = "mmu_defconfig"
+
+# Add meta-xilinx kmeta, used for MicroBlaze BSP fragments
+FILESEXTRAPATHS_prepend := "${THISDIR}:"
+SRC_URI_append = " file://xilinx-kmeta;type=kmeta;name=xilinx-kmeta;destsuffix=xilinx-kmeta"
+
+# MicroBlaze BSP fragments
+KERNEL_FEATURES_append_kc705-microblazeel = " bsp/kc705-microblazeel/kc705-microblazeel.scc"
+
+KERNEL_FEATURES_zynqmp += "${@bb.utils.contains('DISTRO_FEATURES', 'xen', ' bsp/xilinx/xen.scc', '', d)}"
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2018.1.bb b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2018.1.bb
new file mode 100644
index 0000000..c3a8f76
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2018.1.bb
@@ -0,0 +1,7 @@
+LINUX_VERSION = "4.14"
+XILINX_RELEASE_VERSION = "v2018.1"
+KBRANCH ?= "xlnx_rebase_v4.14"
+SRCREV ?= "4ac76ffacb54712b0361e51d0b7156e53d062e3c"
+
+include linux-xlnx.inc
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto-dev.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto-dev.bbappend
new file mode 100644
index 0000000..05c3995
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto-dev.bbappend
@@ -0,0 +1 @@
+require linux-yocto-xilinx.inc
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto-tiny_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto-tiny_%.bbappend
new file mode 100644
index 0000000..05c3995
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto-tiny_%.bbappend
@@ -0,0 +1 @@
+require linux-yocto-xilinx.inc
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto-xilinx.inc b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto-xilinx.inc
new file mode 100644
index 0000000..9209300
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto-xilinx.inc
@@ -0,0 +1,25 @@
+require linux-microblaze.inc
+
+# Add meta-xilinx kmeta
+FILESEXTRAPATHS_prepend := "${THISDIR}:"
+SRC_URI_append = " file://xilinx-kmeta;type=kmeta;name=xilinx-kmeta;destsuffix=xilinx-kmeta"
+
+# Zynq default generic KMACHINE
+COMPATIBLE_MACHINE_zynq = "zynq"
+KMACHINE_zynq = "zynq"
+
+# ZynqMP default generic KMACHINE
+COMPATIBLE_MACHINE_zynqmp = "zynqmp"
+KMACHINE_zynqmp = "zynqmp"
+
+# MicroBlaze KMACHINEs
+KMACHINE_ml605-qemu-microblazeel = "qemumicroblazeel"
+KMACHINE_s3adsp1800-qemu-microblazeeb = "qemumicroblazeeb"
+
+# MicroBlaze default generic KMACHINE
+KMACHINE_microblaze = "microblaze"
+COMPATIBLE_MACHINE_microblaze = "microblaze"
+
+# Default kernel config fragements for specific machines
+KERNEL_FEATURES_append_kc705-microblazeel = " bsp/kc705-microblazeel/kc705-microblazeel.scc"
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto_%.bbappend
new file mode 100644
index 0000000..05c3995
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-yocto_%.bbappend
@@ -0,0 +1 @@
+require linux-yocto-xilinx.inc
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/kc705-microblazeel/kc705-microblazeel.cfg b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/kc705-microblazeel/kc705-microblazeel.cfg
new file mode 100644
index 0000000..bf7f316
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/kc705-microblazeel/kc705-microblazeel.cfg
@@ -0,0 +1,17 @@
+CONFIG_XILINX_MICROBLAZE0_FAMILY="kintex7"
+
+# CPU ISA Config
+CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
+CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR=1
+CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
+CONFIG_XILINX_MICROBLAZE0_USE_DIV=1
+CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=2
+CONFIG_XILINX_MICROBLAZE0_USE_FPU=0
+CONFIG_XILINX_MICROBLAZE0_HW_VER="10.0"
+
+# Memory Base Address
+CONFIG_KERNEL_BASE_ADDR=0x80000000
+
+CONFIG_XILINX_AXI_EMAC=y
+CONFIG_XILINX_PHY=y
+CONFIG_BLK_DEV_INITRD=y
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/kc705-microblazeel/kc705-microblazeel.scc b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/kc705-microblazeel/kc705-microblazeel.scc
new file mode 100644
index 0000000..aaf7c2a
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/kc705-microblazeel/kc705-microblazeel.scc
@@ -0,0 +1,4 @@
+define KFEATURE_DESCRIPTION "Kernel Config for kc705-microblazeel specific setup"
+define KFEATURE_COMPATIBILITY board
+
+kconf hardware kc705-microblazeel.cfg
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/microblaze-standard.scc b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/microblaze-standard.scc
new file mode 100644
index 0000000..170489d
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/microblaze-standard.scc
@@ -0,0 +1,14 @@
+define KMACHINE microblaze
+define KTYPE standard
+define KARCH microblaze
+
+include ktypes/standard/standard.scc
+
+include bsp/xilinx/soc/microblaze.scc
+
+# Common board drivers
+include bsp/xilinx/board-common.scc
+
+# default policy for standard kernels
+include features/latencytop/latencytop.scc
+include features/profiling/profiling.scc
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/microblaze-tiny.scc b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/microblaze-tiny.scc
new file mode 100644
index 0000000..979fb86
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/microblaze-tiny.scc
@@ -0,0 +1,11 @@
+define KMACHINE microblaze
+define KTYPE tiny
+define KARCH microblaze
+
+include ktypes/tiny/tiny.scc
+
+include bsp/xilinx/soc/microblaze.scc
+
+# Common board drivers
+include bsp/xilinx/board-common.scc
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-drm.cfg b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-drm.cfg
new file mode 100644
index 0000000..0f66c8b
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-drm.cfg
@@ -0,0 +1,14 @@
+# CMA
+CONFIG_CMA=y
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=128
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+CONFIG_CMA_ALIGNMENT=8
+
+# DRM
+CONFIG_DRM=y
+CONFIG_DRM_XILINX=y
+
+# frame buffer console
+CONFIG_FRAMEBUFFER_CONSOLE=y
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-drm.scc b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-drm.scc
new file mode 100644
index 0000000..56c80c3
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-drm.scc
@@ -0,0 +1,4 @@
+define KFEATURE_DESCRIPTION "Enable Xilinx DRM support"
+define KFEATURE_COMPATIBILITY board
+
+kconfig hardware drivers-drm.cfg
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-softip-pcie.cfg b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-softip-pcie.cfg
new file mode 100644
index 0000000..df88fce
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-softip-pcie.cfg
@@ -0,0 +1,7 @@
+
+# PCIe
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_XILINX=y
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-softip-pcie.scc b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-softip-pcie.scc
new file mode 100644
index 0000000..e60047a
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-softip-pcie.scc
@@ -0,0 +1,5 @@
+define KFEATURE_DESCRIPTION "Xilinx AXI PCIe Host Bridge"
+define KFEATURE_COMPATIBILITY board
+
+kconfig hardware drivers-softip-pcie.cfg
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-xlnx-softip.cfg b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-xlnx-softip.cfg
new file mode 100644
index 0000000..5c2529a
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-xlnx-softip.cfg
@@ -0,0 +1,19 @@
+# Xilinx DMA engines
+CONFIG_XILINX_DMA_ENGINES=y
+
+# Xilinx Traffic Generator
+CONFIG_XILINX_TRAFGEN=y
+
+# Xilinx Perfmon UIO driver
+CONFIG_UIO_XILINX_APM=y
+
+# Interrupt controller
+CONFIG_XILINX_INTC=y
+
+# Xilinx PHY
+CONFIG_XILINX_PHY=y
+
+# JESD204B PHY
+CONFIG_XILINX_JESD204B=y
+CONFIG_XILINX_JESD204B_PHY=y
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-xlnx-zynq.cfg b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-xlnx-zynq.cfg
new file mode 100644
index 0000000..9b70ac4
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-xlnx-zynq.cfg
@@ -0,0 +1,16 @@
+# Devcfg
+CONFIG_XILINX_DEVCFG=y
+
+# Ethernet
+CONFIG_XILINX_PS_EMAC=y
+
+# SPI
+CONFIG_SPI_ZYNQ_QSPI=y
+
+# NAND
+CONFIG_MTD_NAND_PL353=y
+CONFIG_MTD_NAND_PL35X=y
+
+# FPGA
+CONFIG_XILINX_PR_DECOUPLER=y
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-xlnx-zynqmp.cfg b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-xlnx-zynqmp.cfg
new file mode 100644
index 0000000..4cbb205
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-xlnx-zynqmp.cfg
@@ -0,0 +1,67 @@
+CONFIG_SOC_XILINX_ZYNQMP=y
+
+# PMU Firmware API
+CONFIG_ZYNQMP_PM_API_DEBUGFS=y
+
+# DMA
+CONFIG_DMADEVICES=y
+CONFIG_XILINX_DMA_ENGINES=y
+CONFIG_XILINX_DPDMA=y
+
+# NAND
+CONFIG_MTD=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ARASAN=y
+
+# PCIe
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIE_XILINX_NWL=y
+
+# CONFIG_ARM_MALI is not set
+
+CONFIG_PHY_XILINX_ZYNQMP=y
+
+# EDAC
+CONFIG_EDAC=y
+CONFIG_EDAC_MM_EDAC=y
+CONFIG_EDAC_CORTEX_ARM64=y
+CONFIG_EDAC_SYNOPSYS=y
+CONFIG_EDAC_ZYNQMP_OCM=y
+
+# Sound
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_DRIVERS=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_XILINX_DP=y
+
+# Ethernet
+CONFIG_MACB_EXT_BD=y
+
+# FPGA
+CONFIG_FPGA=y
+CONFIG_FPGA_MGR_ZYNQMP_FPGA=y
+CONFIG_FPGA_REGION=y
+CONFIG_FPGA_BRIDGE=y
+CONFIG_XILINX_PR_DECOUPLER=y
+
+# AMS
+CONFIG_XILINX_AMS=y
+
+# NVMEM
+CONFIG_NVMEM=y
+CONFIG_NVMEM_ZYNQMP=y
+
+# Fabric Clock
+CONFIG_STAGING=y
+CONFIG_XILINX_FCLK=y
+
+# Clock controllers
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_ZYNQMP=y
+
+# Reset controller
+CONFIG_RESET_CONTROLLER=y
+CONFIG_ZYNQMP_RESET_CONTROLLER=y
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-zynqmp.cfg b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-zynqmp.cfg
new file mode 100644
index 0000000..dc69a65
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/drivers-zynqmp.cfg
@@ -0,0 +1,68 @@
+
+# Bus
+CONFIG_ARM_CCI400_PMU=y
+
+# IOMMU
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_ARM_SMMU=y
+
+# Serial
+CONFIG_TTY=y
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+
+# Watchdog
+CONFIG_WATCHDOG=y
+CONFIG_CADENCE_WATCHDOG=y
+
+# RTC
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_ZYNQMP=y
+
+# Ethernet
+CONFIG_NET_CADENCE=y
+CONFIG_MACB=y
+
+# GPIO
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_ZYNQ=y
+
+# I2C
+CONFIG_I2C=y
+CONFIG_I2C_CADENCE=y
+
+# SPI
+CONFIG_SPI=y
+CONFIG_SPI_CADENCE=y
+CONFIG_SPI_ZYNQMP_GQSPI=y
+
+# CAN
+CONFIG_CAN=y
+CONFIG_CAN_DEV=y
+CONFIG_CAN_XILINXCAN=y
+
+# SATA
+CONFIG_ATA=y
+CONFIG_ATA_SFF=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_AHCI_CEVA=y
+
+# MMC/SD
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+
+# USB
+CONFIG_USB=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+
+# DMA
+CONFIG_DMA_ENGINE=y
+CONFIG_XILINX_ZYNQMP_DMA=y
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/zynqmp.cfg b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/zynqmp.cfg
new file mode 100644
index 0000000..072a3fe
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/zynqmp.cfg
@@ -0,0 +1,26 @@
+
+# Arch Feature Selections
+CONFIG_ARM64=y
+CONFIG_64BIT=y
+CONFIG_ARCH_ZYNQMP=y
+
+# SMP
+CONFIG_SMP=y
+
+# ARM 32-Bit compatiblity
+CONFIG_COMPAT=y
+# CONFIG_COMPAT_BRK is not set
+
+# CPU Frequency
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPU_IDLE=y
+CONFIG_ARM_CPUIDLE=y
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/zynqmp.scc b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/zynqmp.scc
new file mode 100644
index 0000000..8fcb8e6
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/soc/zynqmp.scc
@@ -0,0 +1,10 @@
+define KFEATURE_DESCRIPTION "Xilinx Zynq UltraScale+ MPSoC"
+define KFEATURE_COMPATIBILITY board
+
+include features/net/net.scc
+include cfg/timer/no_hz.scc
+
+kconf hardware zynqmp.cfg
+kconf hardware drivers-zynqmp.cfg
+include bsp/xilinx/soc/drivers-softip.scc
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/xen.cfg b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/xen.cfg
new file mode 100644
index 0000000..50d5e46
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/xen.cfg
@@ -0,0 +1,45 @@
+CONFIG_HYPERVISOR_GUEST=y
+CONFIG_PARAVIRT=y
+CONFIG_XEN=y
+CONFIG_XEN_DOM0=y
+CONFIG_XEN_PVHVM=y
+CONFIG_XEN_SAVE_RESTORE=y
+# CONFIG_XEN_DEBUG_FS is not set
+CONFIG_MMU_NOTIFIER=y
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_PCI_XEN=y
+CONFIG_XEN_PCIDEV_FRONTEND=y
+CONFIG_SYS_HYPERVISOR=y
+CONFIG_XEN_BLKDEV_FRONTEND=y
+CONFIG_XEN_BLKDEV_BACKEND=m
+CONFIG_XEN_SCSI_FRONTEND=m
+CONFIG_XEN_NETDEV_FRONTEND=y
+CONFIG_XEN_NETDEV_BACKEND=m
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
+CONFIG_HVC_IRQ=y
+CONFIG_HVC_XEN=y
+CONFIG_HVC_XEN_FRONTEND=y
+CONFIG_XEN_WDT=m
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_XEN_FBDEV_FRONTEND=y
+CONFIG_XEN_BALLOON=y
+CONFIG_XEN_SCRUB_PAGES=y
+CONFIG_XEN_DEV_EVTCHN=y
+CONFIG_XEN_BACKEND=y
+CONFIG_XENFS=y
+CONFIG_XEN_COMPAT_XENFS=y
+CONFIG_XEN_SYS_HYPERVISOR=y
+CONFIG_XEN_XENBUS_FRONTEND=y
+CONFIG_XEN_GNTDEV=m
+CONFIG_XEN_GRANT_DEV_ALLOC=m
+CONFIG_SWIOTLB_XEN=y
+CONFIG_XEN_PCIDEV_BACKEND=m
+CONFIG_XEN_PRIVCMD=y
+CONFIG_XEN_ACPI_PROCESSOR=m
+CONFIG_XEN_MCE_LOG=y
+CONFIG_XEN_HAVE_PVMMU=y
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/xen.scc b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/xen.scc
new file mode 100644
index 0000000..b588e5d
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/xen.scc
@@ -0,0 +1,4 @@
+define KFEATURE_DESCRIPTION "Xen Kernel Support"
+define KFEATURE_COMPATIBILITY arch
+
+kconf non-hardware xen.cfg
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/zynqmp-standard.scc b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/zynqmp-standard.scc
new file mode 100644
index 0000000..1c9a4f3
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/zynqmp-standard.scc
@@ -0,0 +1,15 @@
+define KMACHINE zynqmp
+define KTYPE standard
+define KARCH arm64
+
+include ktypes/standard/standard.scc
+
+include bsp/xilinx/soc/zynqmp.scc
+include bsp/xilinx/board-common.scc
+
+include features/input/input.scc
+include cfg/usb-mass-storage.scc
+
+# default policy for standard kernels
+#include features/latencytop/latencytop.scc
+#include features/profiling/profiling.scc
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/zynqmp-tiny.scc b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/zynqmp-tiny.scc
new file mode 100644
index 0000000..6cdfc72
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/xilinx/zynqmp-tiny.scc
@@ -0,0 +1,9 @@
+define KMACHINE zynqmp
+define KTYPE tiny
+define KARCH arm64
+
+include ktypes/tiny/tiny.scc
+
+include bsp/xilinx/soc/zynqmp.scc
+include bsp/xilinx/board-common.scc
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.cfg b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.cfg
new file mode 100644
index 0000000..37eaa4c
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.cfg
@@ -0,0 +1,19 @@
+# Keyboard GPIO support
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
+
+# Sound support for Zybo linux_bd project
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_ADI=y
+CONFIG_SND_SOC_ADI_AXI_I2S=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_SOC_SSM2602_I2C=y
+
+# Drivers for Digilent DRM encoder
+# DRM encoder
+CONFIG_DRM_DIGILENT_ENCODER=y
+# Common Clock Framework
+CONFIG_COMMON_CLK_DGLNT_DYNCLK=y
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.scc b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.scc
new file mode 100644
index 0000000..f3e6e8b
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/bsp/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.scc
@@ -0,0 +1,7 @@
+define KFEATURE_DESCRIPTION "Kernel Config for ZYBO Linux-BD Design"
+define KFEATURE_COMPATIBILITY board
+
+kconf hardware zybo-linux-bd-zynq7.cfg
+
+include bsp/xilinx/soc/drivers-drm.scc
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/features/uio/uio.cfg b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/features/uio/uio.cfg
new file mode 100644
index 0000000..048ffe4
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/features/uio/uio.cfg
@@ -0,0 +1,4 @@
+CONFIG_UIO=y
+CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_UIO_DMEM_GENIRQ=y
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/features/uio/uio.scc b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/features/uio/uio.scc
new file mode 100644
index 0000000..9697949
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/features/uio/uio.scc
@@ -0,0 +1,5 @@
+define KFEATURE_DESCRIPTION "Enable UIO Support"
+define KFEATURE_COMPATIBILITY board
+
+kconfig hardware uio.cfg
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/features/v4l2/v4l2-xilinx.cfg b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/features/v4l2/v4l2-xilinx.cfg
new file mode 100644
index 0000000..49a5d6f
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/features/v4l2/v4l2-xilinx.cfg
@@ -0,0 +1,23 @@
+# Media support
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+
+# V4L
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+
+# Xilinx Video drivers
+CONFIG_VIDEO_XILINX=y
+CONFIG_VIDEO_XILINX_CFA=y
+CONFIG_VIDEO_XILINX_CRESAMPLE=y
+CONFIG_VIDEO_XILINX_HLS=y
+CONFIG_VIDEO_XILINX_REMAPPER=y
+CONFIG_VIDEO_XILINX_RGB2YUV=y
+CONFIG_VIDEO_XILINX_SCALER=y
+CONFIG_VIDEO_XILINX_SWITCH=y
+CONFIG_VIDEO_XILINX_TPG=y
+CONFIG_VIDEO_XILINX_VTC=y
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/features/v4l2/v4l2-xilinx.scc b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/features/v4l2/v4l2-xilinx.scc
new file mode 100644
index 0000000..6d6ba6a
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/xilinx-kmeta/features/v4l2/v4l2-xilinx.scc
@@ -0,0 +1,4 @@
+define KFEATURE_DESCRIPTION "Enable Xilinx V4L2 support"
+define KFEATURE_COMPATIBILITY board
+
+kconfig hardware v4l2-xilinx.cfg
\ No newline at end of file
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend
new file mode 100644
index 0000000..795c671
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend
@@ -0,0 +1,15 @@
+FILESEXTRAPATHS_append_microblaze := "${THISDIR}/binutils-2.30:"
+SRC_URI_append_microblaze = " \
+ file://0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch \
+ file://0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch \
+ file://0003-Disable-the-warning-message-for-eh_frame_hdr.patch \
+ file://0004-Fix-relaxation-of-assembler-resolved-references.patch \
+ file://0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch \
+ file://0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch \
+ file://0007-Add-MicroBlaze-address-extension-instructions.patch \
+ file://0008-Add-new-MicroBlaze-bit-field-instructions.patch \
+ file://0009-Fixing-MicroBlaze-IMM-bug.patch \
+ file://0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch \
+ file://0011-Fixing-MicroBlaze-constant-range-check-issue.patch \
+ file://0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch \
+ "
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
new file mode 100644
index 0000000..878bb32
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
@@ -0,0 +1,65 @@
+From 91f39b692c48336117c092e4afd80899c97779e6 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Mon, 28 Aug 2017 19:53:52 -0700
+Subject: [PATCH] MicroBlaze Add wdc.ext.clear and wdc.ext.flush insns
+
+Added two new instructions, wdc.ext.clear and wdc.ext.flush,
+to enable MicroBlaze to flush an external cache, which is
+used with the new coherency support for multiprocessing.
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+
+---
+ opcodes/microblaze-opc.h | 5 ++++-
+ opcodes/microblaze-opcm.h | 4 ++--
+ 2 files changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index ede8af8..773dc81 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -91,6 +91,7 @@
+ #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
+ #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
+ #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
++#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
+
+ /* New Mask for msrset, msrclr insns. */
+@@ -101,7 +102,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+
+-#define MAX_OPCODES 289
++#define MAX_OPCODES 291
+
+ struct op_code_struct
+ {
+@@ -174,7 +175,9 @@ struct op_code_struct
+ {"wic", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
+ {"wdc", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
+ {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
++ {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
+ {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
++ {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
+ {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
+ {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
+ {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 92f3f19..7338f6a 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -33,8 +33,8 @@ enum microblaze_instr
+ /* 'or/and/xor' are C++ keywords. */
+ microblaze_or, microblaze_and, microblaze_xor,
+ andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+- wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
+- brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
++ wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
++ brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+ bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+ imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+ brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch
new file mode 100644
index 0000000..edeecfd
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch
@@ -0,0 +1,64 @@
+From 8b733a61ab54ba4cedb234020562502d20eebcbb Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Date: Mon, 28 Aug 2017 19:53:53 -0700
+Subject: [PATCH] MicroBlaze add mlittle-endian and mbig-endian flags
+
+Added support in gas for mlittle-endian and mbig-endian flags
+as options.
+
+Updated show usage for MicroBlaze specific assembler options
+to include new entries.
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+
+---
+ gas/config/tc-microblaze.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 0194cd9..42dd7ae 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -37,6 +37,8 @@
+
+ #define OPTION_EB (OPTION_MD_BASE + 0)
+ #define OPTION_EL (OPTION_MD_BASE + 1)
++#define OPTION_LITTLE (OPTION_MD_BASE + 2)
++#define OPTION_BIG (OPTION_MD_BASE + 3)
+
+ void microblaze_generate_symbol (char *sym);
+ static bfd_boolean check_spl_reg (unsigned *);
+@@ -1837,6 +1839,8 @@ struct option md_longopts[] =
+ {
+ {"EB", no_argument, NULL, OPTION_EB},
+ {"EL", no_argument, NULL, OPTION_EL},
++ {"mlittle-endian", no_argument, NULL, OPTION_LITTLE},
++ {"mbig-endian", no_argument, NULL, OPTION_BIG},
+ { NULL, no_argument, NULL, 0}
+ };
+
+@@ -2471,9 +2475,11 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
+ switch (c)
+ {
+ case OPTION_EB:
++ case OPTION_BIG:
+ target_big_endian = 1;
+ break;
+ case OPTION_EL:
++ case OPTION_LITTLE:
+ target_big_endian = 0;
+ break;
+ default:
+@@ -2488,6 +2494,9 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
+ /* fprintf(stream, _("\
+ MicroBlaze options:\n\
+ -noSmall Data in the comm and data sections do not go into the small data section\n")); */
++ fprintf (stream, _(" MicroBlaze specific assembler options:\n"));
++ fprintf (stream, " -%-23s%s\n", "mbig-endian", N_("assemble for a big endian cpu"));
++ fprintf (stream, " -%-23s%s\n", "mlittle-endian", N_("assemble for a little endian cpu"));
+ }
+
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0003-Disable-the-warning-message-for-eh_frame_hdr.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
new file mode 100644
index 0000000..2b30c46
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
@@ -0,0 +1,34 @@
+From dac72d809be9faf9380b181df0c19a2c6d744c54 Mon Sep 17 00:00:00 2001
+From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
+Date: Mon, 28 Aug 2017 19:53:54 -0700
+Subject: [PATCH] Disable the warning message for eh_frame_hdr
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Inappropriate [workaround]
+
+---
+ bfd/elf-eh-frame.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c
+index 95697c4..704121d 100644
+--- a/bfd/elf-eh-frame.c
++++ b/bfd/elf-eh-frame.c
+@@ -1042,10 +1042,13 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info,
+ goto success;
+
+ free_no_table:
+- (*info->callbacks->einfo)
++ /* FIXME: Remove the microblaze specifics when relaxing gets fixed. */
++ if (bfd_get_arch(abfd) != bfd_arch_microblaze) {
+ /* xgettext:c-format */
+- (_("%P: error in %B(%A); no .eh_frame_hdr table will be created.\n"),
+- abfd, sec);
++ (*info->callbacks->einfo)
++ (_("%P: error in %B(%A); no .eh_frame_hdr table will be created.\n"),
++ abfd, sec);
++ }
+ hdr_info->u.dwarf.table = FALSE;
+ if (sec_info)
+ free (sec_info);
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0004-Fix-relaxation-of-assembler-resolved-references.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0004-Fix-relaxation-of-assembler-resolved-references.patch
new file mode 100644
index 0000000..b543c54
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0004-Fix-relaxation-of-assembler-resolved-references.patch
@@ -0,0 +1,81 @@
+From 927ef228dfedf229dc915b273a308ab2c7bf9e19 Mon Sep 17 00:00:00 2001
+From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
+Date: Mon, 28 Aug 2017 19:53:55 -0700
+Subject: [PATCH] Fix relaxation of assembler resolved references
+
+03/2018
+Rebased for binutils 2.30
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>
+
+Upstream-Status: Pending
+
+---
+ bfd/elf32-microblaze.c | 39 +++++++++++++++++++++++++++++++++++++++
+ gas/config/tc-microblaze.c | 1 +
+ 2 files changed, 40 insertions(+)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index f1808bc..a1d810c 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -1887,6 +1887,45 @@ microblaze_elf_relax_section (bfd *abfd,
+ irelscanend = irelocs + o->reloc_count;
+ for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+ {
++ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
++ {
++ unsigned int val;
++
++ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
++
++ /* This was a PC-relative instruction that was completely resolved. */
++ if (ocontents == NULL)
++ {
++ if (elf_section_data (o)->this_hdr.contents != NULL)
++ ocontents = elf_section_data (o)->this_hdr.contents;
++ else
++ {
++ /* We always cache the section contents.
++ Perhaps, if info->keep_memory is FALSE, we
++ should free them, if we are permitted to. */
++
++ if (o->rawsize == 0)
++ o->rawsize = o->size;
++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++ if (ocontents == NULL)
++ goto error_return;
++ if (!bfd_get_section_contents (abfd, o, ocontents,
++ (file_ptr) 0,
++ o->rawsize))
++ goto error_return;
++ elf_section_data (o)->this_hdr.contents = ocontents;
++ }
++ }
++
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend
++ + isym->st_value, sec);
++ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
++ irelscan->r_addend);
++ }
++ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
++ fprintf(stderr, "Unhandled NONE 64\n");
++ }
+ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+ {
+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 42dd7ae..50dbfc7 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -2183,6 +2183,7 @@ md_apply_fix (fixS * fixP,
+ else
+ fixP->fx_r_type = BFD_RELOC_NONE;
+ fixP->fx_addsy = section_symbol (absolute_section);
++ fixP->fx_done = 0;
+ }
+ return;
+ }
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch
new file mode 100644
index 0000000..3817234
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch
@@ -0,0 +1,242 @@
+From 5bf68bc39976903929f730b6eed18686c3563c05 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Date: Mon, 28 Aug 2017 19:53:56 -0700
+Subject: [PATCH] Fixup MicroBlaze debug_loc sections after linker relaxation
+
+Fixup debug_loc sections after linker relaxation Adds a new reloctype
+R_MICROBLAZE_32_NONE, used for passing reloc info from the assembler to
+the linker when the linker manages to fully resolve a local symbol
+reference.
+
+This is a workaround for design flaws in the assembler to
+linker interface with regards to linker relaxation.
+
+03/2018
+Rebased for binutils 2.30
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>
+
+Upstream-Status: Pending
+
+---
+ bfd/bfd-in2.h | 9 +++++++--
+ bfd/elf32-microblaze.c | 45 ++++++++++++++++++++++++++++++++++++++-------
+ bfd/libbfd.h | 1 +
+ bfd/reloc.c | 6 ++++++
+ binutils/readelf.c | 4 ++++
+ gas/config/tc-microblaze.c | 5 ++++-
+ include/elf/microblaze.h | 1 +
+ 7 files changed, 61 insertions(+), 10 deletions(-)
+
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 4228603..1906195 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -5826,10 +5826,15 @@ value relative to the read-write small data area anchor */
+ expressions of the form "Symbol Op Symbol" */
+ BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
+
+-/* This is a 64 bit reloc that stores the 32 bit pc relative
++/* This is a 32 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction). No relocation is
+ done here - only used for relaxing */
+- BFD_RELOC_MICROBLAZE_64_NONE,
++ BFD_RELOC_MICROBLAZE_32_NONE,
++
++/* This is a 64 bit reloc that stores the 32 bit pc relative
++ * +value in two words (with an imm instruction). No relocation is
++ * +done here - only used for relaxing */
++ BFD_RELOC_MICROBLAZE_64_NONE,
+
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction). The relocation is
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index a1d810c..fc0d3e1 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -176,6 +176,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+ 0x0000ffff, /* Dest Mask. */
+ FALSE), /* PC relative offset? */
+
++ HOWTO (R_MICROBLAZE_32_NONE, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 32, /* Bitsize. */
++ TRUE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_bitfield, /* Complain on overflow. */
++ NULL, /* Special Function. */
++ "R_MICROBLAZE_32_NONE",/* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
+ /* This reloc does nothing. Used for relaxation. */
+ HOWTO (R_MICROBLAZE_64_NONE, /* Type. */
+ 0, /* Rightshift. */
+@@ -532,6 +546,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+ case BFD_RELOC_NONE:
+ microblaze_reloc = R_MICROBLAZE_NONE;
+ break;
++ case BFD_RELOC_MICROBLAZE_32_NONE:
++ microblaze_reloc = R_MICROBLAZE_32_NONE;
++ break;
+ case BFD_RELOC_MICROBLAZE_64_NONE:
+ microblaze_reloc = R_MICROBLAZE_64_NONE;
+ break;
+@@ -1832,14 +1849,23 @@ microblaze_elf_relax_section (bfd *abfd,
+ }
+ break;
+ case R_MICROBLAZE_NONE:
++ case R_MICROBLAZE_32_NONE:
+ {
+ /* This was a PC-relative instruction that was
+ completely resolved. */
+ int sfix, efix;
++ unsigned int val;
+ bfd_vma target_address;
+ target_address = irel->r_addend + irel->r_offset;
+ sfix = calc_fixup (irel->r_offset, 0, sec);
+ efix = calc_fixup (target_address, 0, sec);
++
++ /* Validate the in-band val. */
++ val = bfd_get_32 (abfd, contents + irel->r_offset);
++ if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++ }
++
+ irel->r_addend -= (efix - sfix);
+ /* Should use HOWTO. */
+ microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
+@@ -1887,12 +1913,16 @@ microblaze_elf_relax_section (bfd *abfd,
+ irelscanend = irelocs + o->reloc_count;
+ for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+ {
+- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
++ if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
+ {
+ unsigned int val;
+
+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+
++ /* hax: We only do the following fixup for debug location lists. */
++ if (strcmp(".debug_loc", o->name))
++ continue;
++
+ /* This was a PC-relative instruction that was completely resolved. */
+ if (ocontents == NULL)
+ {
+@@ -1917,15 +1947,16 @@ microblaze_elf_relax_section (bfd *abfd,
+ }
+ }
+
+- irelscan->r_addend -= calc_fixup (irelscan->r_addend
+- + isym->st_value, sec);
+ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++
++ if (val != irelscan->r_addend) {
++ fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
++ }
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
++
+ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
+ irelscan->r_addend);
+ }
+- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
+- fprintf(stderr, "Unhandled NONE 64\n");
+- }
+ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+ {
+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+@@ -1985,7 +2016,7 @@ microblaze_elf_relax_section (bfd *abfd,
+ elf_section_data (o)->this_hdr.contents = ocontents;
+ }
+ }
+- irelscan->r_addend -= calc_fixup (irel->r_addend
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend
+ + isym->st_value,
+ 0,
+ sec);
+diff --git a/bfd/libbfd.h b/bfd/libbfd.h
+index 2f5f16e..854bb0c 100644
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -2853,6 +2853,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+ "BFD_RELOC_MICROBLAZE_32_ROSDA",
+ "BFD_RELOC_MICROBLAZE_32_RWSDA",
+ "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
++ "BFD_RELOC_MICROBLAZE_32_NONE",
+ "BFD_RELOC_MICROBLAZE_64_NONE",
+ "BFD_RELOC_MICROBLAZE_64_GOTPC",
+ "BFD_RELOC_MICROBLAZE_64_GOT",
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index a1353a2..4b57de7 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6903,6 +6903,12 @@ ENUMDOC
+ This is a 32 bit reloc for the microblaze to handle
+ expressions of the form "Symbol Op Symbol"
+ ENUM
++ BFD_RELOC_MICROBLAZE_32_NONE
++ENUMDOC
++ This is a 32 bit reloc that stores the 32 bit pc relative
++ value in two words (with an imm instruction). No relocation is
++ done here - only used for relaxing
++ENUM
+ BFD_RELOC_MICROBLAZE_64_NONE
+ ENUMDOC
+ This is a 64 bit reloc that stores the 32 bit pc relative
+diff --git a/binutils/readelf.c b/binutils/readelf.c
+index fed0387..92f655d 100644
+--- a/binutils/readelf.c
++++ b/binutils/readelf.c
+@@ -12774,6 +12774,10 @@ is_none_reloc (Filedata * filedata, unsigned int reloc_type)
+ || reloc_type == 32 /* R_AVR_DIFF32. */);
+ case EM_METAG:
+ return reloc_type == 3; /* R_METAG_NONE. */
++ case EM_MICROBLAZE:
++ return reloc_type == 30 /* R_MICROBLAZE_32_NONE. */
++ || reloc_type == 0 /* R_MICROBLAZE_NONE. */
++ || reloc_type == 9; /* R_MICROBLAZE_64_NONE. */
+ case EM_NDS32:
+ return (reloc_type == 0 /* R_XTENSA_NONE. */
+ || reloc_type == 204 /* R_NDS32_DIFF8. */
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 50dbfc7..d66e949 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -2179,7 +2179,9 @@ md_apply_fix (fixS * fixP,
+ /* This fixup has been resolved. Create a reloc in case the linker
+ moves code around due to relaxing. */
+ if (fixP->fx_r_type == BFD_RELOC_64_PCREL)
+- fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
++ fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
++ else if (fixP->fx_r_type == BFD_RELOC_32)
++ fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
+ else
+ fixP->fx_r_type = BFD_RELOC_NONE;
+ fixP->fx_addsy = section_symbol (absolute_section);
+@@ -2401,6 +2403,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+ switch (fixp->fx_r_type)
+ {
+ case BFD_RELOC_NONE:
++ case BFD_RELOC_MICROBLAZE_32_NONE:
+ case BFD_RELOC_MICROBLAZE_64_NONE:
+ case BFD_RELOC_32:
+ case BFD_RELOC_MICROBLAZE_32_LO:
+diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
+index ae98099..c8cc57b 100644
+--- a/include/elf/microblaze.h
++++ b/include/elf/microblaze.h
+@@ -58,6 +58,7 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
+ RELOC_NUMBER (R_MICROBLAZE_TLSDTPREL64, 27) /* TLS Offset Within TLS Block */
+ RELOC_NUMBER (R_MICROBLAZE_TLSGOTTPREL32, 28) /* TLS Offset From Thread Pointer */
+ RELOC_NUMBER (R_MICROBLAZE_TLSTPREL32, 29) /* TLS Offset From Thread Pointer */
++ RELOC_NUMBER (R_MICROBLAZE_32_NONE, 30)
+
+ END_RELOC_NUMBERS (R_MICROBLAZE_max)
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch
new file mode 100644
index 0000000..a671cf8
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch
@@ -0,0 +1,35 @@
+From 0cad227ce495a975b32c10a8b6b0970c45024dd6 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Date: Mon, 28 Aug 2017 19:53:58 -0700
+Subject: [PATCH] Fix bug in MicroBlaze TLSTPREL Relocation
+
+Fixed the problem related to the fixup/relocations TLSTPREL.
+When the fixup is applied the addend is not added at the correct offset
+of the instruction. The offset is hard coded considering its big endian
+and it fails for Little endian. This patch allows support for both
+big & little-endian compilers
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+
+---
+ bfd/elf32-microblaze.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index fc0d3e1..a94799f 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -1402,9 +1402,9 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ relocation += addend;
+ relocation -= dtprel_base(info);
+ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
+- contents + offset + 2);
++ contents + offset + endian);
+ bfd_put_16 (input_bfd, relocation & 0xffff,
+- contents + offset + 2 + INST_WORD_SIZE);
++ contents + offset + endian + INST_WORD_SIZE);
+ break;
+ case (int) R_MICROBLAZE_64_PCREL :
+ case (int) R_MICROBLAZE_64:
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0007-Add-MicroBlaze-address-extension-instructions.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0007-Add-MicroBlaze-address-extension-instructions.patch
new file mode 100644
index 0000000..9672c51
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0007-Add-MicroBlaze-address-extension-instructions.patch
@@ -0,0 +1,104 @@
+From 3895968b5c55321d203cadb7630a2baee8699e17 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Date: Mon, 28 Aug 2017 19:53:59 -0700
+Subject: [PATCH] Add MicroBlaze address extension instructions
+
+This patch adds the support of new instructions which are required
+for supporting Address extension feature.
+
+2016-01-18 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+
+ * microblaze-opc.h (op_code_struct): Added new instructions
+ * microblaze-opcm.h (microblaze_instr): Added new instructions
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+
+---
+ opcodes/microblaze-opc.h | 13 ++++++++++++-
+ opcodes/microblaze-opcm.h | 10 +++++-----
+ 2 files changed, 17 insertions(+), 6 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 773dc81..4e69f76 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -102,7 +102,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+
+-#define MAX_OPCODES 291
++#define MAX_OPCODES 299
+
+ struct op_code_struct
+ {
+@@ -178,8 +178,11 @@ struct op_code_struct
+ {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
+ {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
+ {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
++ {"wdc.clear.ea", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E6, OPCODE_MASK_H34B, wdcclearea, special_inst },
+ {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
++ {"mtse", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9500C000, OPCODE_MASK_H13S, mtse,special_inst },
+ {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
++ {"mfse", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94088000, OPCODE_MASK_H23S, mfse, special_inst },
+ {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
+ {"brd", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
+ {"brld", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
+@@ -229,18 +232,24 @@ struct op_code_struct
+ {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
+ {"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
+ {"lbur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst },
++ {"lbuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000080, OPCODE_MASK_H4, lbuea, memory_load_inst },
+ {"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
+ {"lhur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst },
++ {"lhuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000080, OPCODE_MASK_H4, lhuea, memory_load_inst },
+ {"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
+ {"lwr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst },
+ {"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
++ {"lwea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000080, OPCODE_MASK_H4, lwea, memory_load_inst },
+ {"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
+ {"sbr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst },
++ {"sbea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000080, OPCODE_MASK_H4, sbea, memory_store_inst },
+ {"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
+ {"shr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst },
++ {"shea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000080, OPCODE_MASK_H4, shea, memory_store_inst },
+ {"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
+ {"swr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst },
+ {"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
++ {"swea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000080, OPCODE_MASK_H4, swea, memory_store_inst },
+ {"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
+ {"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
+ {"lwi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
+@@ -405,6 +414,8 @@ struct op_code_struct
+ {"clz", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34, clz, special_inst },
+ {"mbar", INST_TYPE_IMM5, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN, mbar, special_inst },
+ {"sleep", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 16. */
++ {"hibernate", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB9020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 8. */
++ {"suspend", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 24. */
+ {"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst },
+ {"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst },
+ {"", 0, 0, 0, 0, 0, 0, 0, 0},
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 7338f6a..c75f10a 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -33,13 +33,13 @@ enum microblaze_instr
+ /* 'or/and/xor' are C++ keywords. */
+ microblaze_or, microblaze_and, microblaze_xor,
+ andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+- wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
+- brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+- bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
++ wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, wdcclearea, mts, mtse,
++ mfs, mfse, mbar, br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd,
++ bne, bned, blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+ imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+ brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+- bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
+- shr, sw, swr, swx, lbui, lhui, lwi,
++ bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
++ sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi,
+ sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
+ fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
+ fint, fsqrt,
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0008-Add-new-MicroBlaze-bit-field-instructions.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0008-Add-new-MicroBlaze-bit-field-instructions.patch
new file mode 100644
index 0000000..0bc0117
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0008-Add-new-MicroBlaze-bit-field-instructions.patch
@@ -0,0 +1,232 @@
+From 5c4dacaae2ba93569c1d37cda9859c57d6649dc0 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Date: Mon, 28 Aug 2017 19:54:01 -0700
+Subject: [PATCH] Add new MicroBlaze bit-field instructions
+
+This patches adds new bsefi and bsifi instructions. BSEFI- The
+instruction shall extract a bit field from a register and place it
+right-adjusted in the destination register. The other bits in the
+destination register shall be set to zero BSIFI- The instruction shall
+insert a right-adjusted bit field from a register at another position in
+the destination register. The rest of the bits in the destination
+register shall be unchanged
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gas/config/tc-microblaze.c | 71 +++++++++++++++++++++++++++++++++++++++++++++-
+ opcodes/microblaze-dis.c | 16 +++++++++++
+ opcodes/microblaze-opc.h | 12 +++++++-
+ opcodes/microblaze-opcm.h | 6 +++-
+ 4 files changed, 102 insertions(+), 3 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index e135547e62..34cb80fac2 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -909,7 +909,7 @@ md_assemble (char * str)
+ unsigned reg2;
+ unsigned reg3;
+ unsigned isize;
+- unsigned int immed, temp;
++ unsigned int immed, immed2, temp;
+ expressionS exp;
+ char name[20];
+
+@@ -1164,7 +1164,76 @@ md_assemble (char * str)
+ inst |= (reg2 << RA_LOW) & RA_MASK;
+ inst |= (immed << IMM_LOW) & IMM5_MASK;
+ break;
++ case INST_TYPE_RD_R1_IMM5_IMM5:
++ if (strcmp (op_end, ""))
++ op_end = parse_reg (op_end + 1, ®1); /* Get rd. */
++ else
++ {
++ as_fatal (_("Error in statement syntax"));
++ reg1 = 0;
++ }
++ if (strcmp (op_end, ""))
++ op_end = parse_reg (op_end + 1, ®2); /* Get r1. */
++ else
++ {
++ as_fatal (_("Error in statement syntax"));
++ reg2 = 0;
++ }
++
++ /* Check for spl registers. */
++ if (check_spl_reg (®1))
++ as_fatal (_("Cannot use special register with this instruction"));
++ if (check_spl_reg (®2))
++ as_fatal (_("Cannot use special register with this instruction"));
+
++ /* Width immediate value. */
++ if (strcmp (op_end, ""))
++ op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH);
++ else
++ as_fatal (_("Error in statement syntax"));
++ if (exp.X_op != O_constant)
++ {
++ as_warn (_("Symbol used as immediate width value for bit field instruction"));
++ immed = 1;
++ }
++ else
++ immed = exp.X_add_number;
++ if (opcode->instr == bsefi && immed > 31)
++ as_fatal (_("Width value must be less than 32"));
++
++ /* Shift immediate value. */
++ if (strcmp (op_end, ""))
++ op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM);
++ else
++ as_fatal (_("Error in statement syntax"));
++ if (exp.X_op != O_constant)
++ {
++ as_warn (_("Symbol used as immediate shift value for bit field instruction"));
++ immed2 = 0;
++ }
++ else
++ {
++ output = frag_more (isize);
++ immed2 = exp.X_add_number;
++ }
++ if (immed2 != (immed2 % 32))
++ {
++ as_warn (_("Shift value greater than 32. using <value %% 32>"));
++ immed2 = immed2 % 32;
++ }
++
++ /* Check combined value. */
++ if (immed + immed2 > 32)
++ as_fatal (_("Width value + shift value must not be greater than 32"));
++
++ inst |= (reg1 << RD_LOW) & RD_MASK;
++ inst |= (reg2 << RA_LOW) & RA_MASK;
++ if (opcode->instr == bsefi)
++ inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */
++ else
++ inst |= ((immed + immed2 - 1) & IMM5_MASK) << IMM_WIDTH_LOW; /* bsifi */
++ inst |= (immed2 << IMM_LOW) & IMM5_MASK;
++ break;
+ case INST_TYPE_R1_R2:
+ if (strcmp (op_end, ""))
+ op_end = parse_reg (op_end + 1, ®1); /* Get r1. */
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index 6a174b0eb9..80a47ad2fc 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -73,6 +73,18 @@ get_field_imm5_mbar (long instr)
+ return(strdup(tmpstr));
+ }
+
++static char *
++get_field_imm5width (long instr)
++{
++ char tmpstr[25];
++
++ if (instr & 0x00004000)
++ sprintf (tmpstr, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
++ else
++ sprintf (tmpstr, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
++ return (strdup (tmpstr));
++}
++
+ static char *
+ get_field_rfsl (long instr)
+ {
+@@ -396,6 +408,10 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+ /* For mbar 16 or sleep insn. */
+ case INST_TYPE_NONE:
+ break;
++ /* For bit field insns. */
++ case INST_TYPE_RD_R1_IMM5_IMM5:
++ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (inst),get_field_r1(inst),get_field_imm5width (inst), get_field_imm5 (inst));
++ break;
+ /* For tuqula instruction */
+ case INST_TYPE_RD:
+ print_func (stream, "\t%s", get_field_rd (inst));
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index a64f8362da..afb34989d9 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -59,6 +59,9 @@
+ /* For mbar. */
+ #define INST_TYPE_IMM5 20
+
++/* For bsefi and bsifi */
++#define INST_TYPE_RD_R1_IMM5_IMM5 21
++
+ #define INST_TYPE_NONE 25
+
+
+@@ -89,7 +92,9 @@
+ #define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */
+ #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */
+ #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
++#define OPCODE_MASK_H3B 0xFC00C600 /* High 6 bits and bits 16, 17, 21, 22. */
+ #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
++#define OPCODE_MASK_H32B 0xFC00C000 /* High 6 bits and bit 16, 17. */
+ #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
+ #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
+@@ -102,7 +107,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+
+-#define MAX_OPCODES 299
++#define MAX_OPCODES 301
+
+ struct op_code_struct
+ {
+@@ -159,6 +164,8 @@ struct op_code_struct
+ {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
+ {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
+ {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
++ {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
++ {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
+ {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
+ {"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
+ {"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
+@@ -438,5 +445,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM5 ((int) 0x00000000)
+ #define MAX_IMM5 ((int) 0x0000001f)
+
++#define MIN_IMM_WIDTH ((int) 0x00000001)
++#define MAX_IMM_WIDTH ((int) 0x00000020)
++
+ #endif /* MICROBLAZE_OPC */
+
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 21a3dc8d76..dd6be7f65c 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -29,7 +29,7 @@ enum microblaze_instr
+ addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
+ mulh, mulhu, mulhsu,swapb,swaph,
+ idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
+- ncget, ncput, muli, bslli, bsrai, bsrli, mului,
++ ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului,
+ /* 'or/and/xor' are C++ keywords. */
+ microblaze_or, microblaze_and, microblaze_xor,
+ andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+@@ -129,6 +129,7 @@ enum microblaze_instr_type
+ #define RB_LOW 11 /* Low bit for RB. */
+ #define IMM_LOW 0 /* Low bit for immediate. */
+ #define IMM_MBAR 21 /* low bit for mbar instruction. */
++#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */
+
+ #define RD_MASK 0x03E00000
+ #define RA_MASK 0x001F0000
+@@ -141,6 +142,9 @@ enum microblaze_instr_type
+ /* Imm mask for mbar. */
+ #define IMM5_MBAR_MASK 0x03E00000
+
++/* Imm mask for extract/insert width. */
++#define IMM5_WIDTH_MASK 0x000007C0
++
+ /* FSL imm mask for get, put instructions. */
+ #define RFSL_MASK 0x000000F
+
+--
+2.15.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0009-Fixing-MicroBlaze-IMM-bug.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0009-Fixing-MicroBlaze-IMM-bug.patch
new file mode 100644
index 0000000..bb7e91c
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0009-Fixing-MicroBlaze-IMM-bug.patch
@@ -0,0 +1,29 @@
+From f649406ccaea992f3931e0d9ca9fbd6efb0c553b Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Date: Mon, 28 Aug 2017 19:54:02 -0700
+Subject: [PATCH] Fixing MicroBlaze IMM bug
+
+Fixing the imm bug. with relax option imm -1 is also getting removed this is corrected now.
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+
+---
+ bfd/elf32-microblaze.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index a94799f..74b00d2 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -1789,8 +1789,7 @@ microblaze_elf_relax_section (bfd *abfd,
+ else
+ symval += irel->r_addend;
+
+- if ((symval & 0xffff8000) == 0
+- || (symval & 0xffff8000) == 0xffff8000)
++ if ((symval & 0xffff8000) == 0)
+ {
+ /* We can delete this instruction. */
+ sec->relax[sec->relax_count].addr = irel->r_offset;
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch
new file mode 100644
index 0000000..077343e
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch
@@ -0,0 +1,34 @@
+From e1bacaa7c1aa387f167afff74876c5acdffc39d9 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 15 Nov 2017 17:45:35 -0800
+Subject: [PATCH] Fixed bug in GCC so that it will support .long 0U and .long
+ 0u
+
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+
+---
+ gas/expr.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/gas/expr.c b/gas/expr.c
+index 3e28af6..0b7cc76 100644
+--- a/gas/expr.c
++++ b/gas/expr.c
+@@ -810,6 +810,15 @@ operand (expressionS *expressionP, enum expr_mode mode)
+ break;
+ }
+ }
++ if ((*input_line_pointer == 'U') || (*input_line_pointer == 'u'))
++ {
++ input_line_pointer--;
++
++ integer_constant ((NUMBERS_WITH_SUFFIX || flag_m68k_mri)
++ ? 0 : 10,
++ expressionP);
++ break;
++ }
+ c = *input_line_pointer;
+ switch (c)
+ {
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0011-Fixing-MicroBlaze-constant-range-check-issue.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0011-Fixing-MicroBlaze-constant-range-check-issue.patch
new file mode 100644
index 0000000..244a7ad
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0011-Fixing-MicroBlaze-constant-range-check-issue.patch
@@ -0,0 +1,28 @@
+From 9393a3e346d2ccbb86761117260c1dd89070a507 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Date: Wed, 15 Nov 2017 17:45:34 -0800
+Subject: [PATCH] Fixing MicroBlaze constant range check issue
+
+Sample error: not in range ffffffff80000000..7fffffff, not ffffffff70000000
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+
+---
+ gas/config/tc-microblaze.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 21a5a0c..c614556 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -749,7 +749,7 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max)
+ if ((e->X_add_number >> 31) == 1)
+ e->X_add_number |= -((addressT) (1U << 31));
+
+- if (e->X_add_number < min || e->X_add_number > max)
++ if ((int)e->X_add_number < min || (int)e->X_add_number > max)
+ {
+ as_fatal (_("operand must be absolute in range %lx..%lx, not %lx"),
+ (long) min, (long) max, (long) e->X_add_number);
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch
new file mode 100644
index 0000000..e340c50
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.30/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch
@@ -0,0 +1,36 @@
+From 732b5a44a0a032da5ebb775b5df2ee2a36af988f Mon Sep 17 00:00:00 2001
+From: Nathan Rossi <nathan@nathanrossi.com>
+Date: Sun, 5 Nov 2017 22:17:39 +1000
+Subject: [PATCH] MicroBlaze fix mask for barrel shift instructions
+
+As of v10.0 the bsi (bslli/bsrai/bsrli/bsefi/bsifi) instructions have
+bits 16 and 17 defined as 'Insert' and 'Extract' respectively to support
+bit field insert/extract operations. For the bslli/bsrai/bsrli
+instructions these bits must be 0, as such update the opcode mask so
+that the bslli/bsrai/bsrli instructions do not also match the bsefi and
+bsifi instructions.
+
+Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
+Upstream-Status: Pending
+
+---
+ opcodes/microblaze-opc.h | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 4bc400a..9482d81 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -161,9 +161,9 @@ struct op_code_struct
+ {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
+ {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
+ {"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
+- {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
+- {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
+- {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
++ {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst },
++ {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst },
++ {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst },
+ {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
+ {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
+ {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0001-Revert.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0001-Revert.patch
new file mode 100644
index 0000000..93af651
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0001-Revert.patch
@@ -0,0 +1,42 @@
+From 12cd383fbef719cc1a84cc80ff171073409a8557 Mon Sep 17 00:00:00 2001
+From: eager <eager@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Sat, 27 May 2017 18:29:40 +0000
+Subject: [PATCH] Revert: 2016-01-21 Ajit Agarwal
+ <ajitkum@xilinx.com>
+
+ See https://gcc.gnu.org/ml/gcc/2017-05/msg00221.html.
+
+ * config/microblaze/microblaze.h
+ (FIXED_REGISTERS): Update in macro.
+ (CALL_USED_REGISTERS): Update in macro.
+
+git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@248540 138bc75d-0d04-0410-961f-82ee72b054a4
+Upstream-Status: Backport [from post gcc-7]
+---
+ gcc/config/microblaze/microblaze.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 66e4ef5c3d..2c9ece1d6c 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -269,14 +269,14 @@ extern enum pipeline_type microblaze_pipe;
+ #define FIXED_REGISTERS \
+ { \
+ 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
+- 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
++ 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 1, 1, 1, 1 \
+ }
+
+ #define CALL_USED_REGISTERS \
+ { \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+- 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
++ 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 1, 1, 1, 1 \
+ }
+ #define GP_REG_FIRST 0
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch
new file mode 100644
index 0000000..03ea8b1
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch
@@ -0,0 +1,66 @@
+From 2d90c10cf4d95999f68f474305828c7dfc51af18 Mon Sep 17 00:00:00 2001
+From: Nathan Rossi <nathan@nathanrossi.com>
+Date: Thu, 12 Nov 2015 16:09:31 +1000
+Subject: [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3' insn definitions
+
+Change adddi3 to handle DI immediates as the second operand, this
+requires modification to the output template however reduces the need to
+specify seperate templates for 16-bit positive/negative immediate
+operands. The use of 32-bit immediates for the addi and addic
+instructions is handled by the assembler, which will emit the imm
+instructions when required. This conveniently handles the optimizable
+cases where the immediate constant value does not need the higher half
+words of the operands upper/lower words.
+
+Change the constraints of the subdi3 instruction definition such that it
+does not match the second operand as an immediate value. This is because
+there is no definition to handle this case nor is it possible to
+implement purely with instructions as microblaze does not provide an
+instruction to perform a forward arithmetic subtraction (it only
+provides reverse 'rD = IMM - rA').
+
+Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
+Upstream-Status: Unsubmitted
+---
+ gcc/config/microblaze/microblaze.md | 13 ++++++-------
+ 1 file changed, 6 insertions(+), 7 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index b3a0011fd7..8a372d7ebb 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -483,17 +483,16 @@
+ ;; Adding 2 DI operands in register or reg/imm
+
+ (define_insn "adddi3"
+- [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+- (plus:DI (match_operand:DI 1 "register_operand" "%d,d,d")
+- (match_operand:DI 2 "arith_operand32" "d,P,N")))]
++ [(set (match_operand:DI 0 "register_operand" "=d,d")
++ (plus:DI (match_operand:DI 1 "register_operand" "%d,d")
++ (match_operand:DI 2 "arith_operand" "d,i")))]
+ ""
+ "@
+ add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2
+- addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0
+- addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0\;addi\t%M0,%M0,-1"
++ addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2"
+ [(set_attr "type" "darith")
+ (set_attr "mode" "DI")
+- (set_attr "length" "8,8,12")])
++ (set_attr "length" "8,8")])
+
+ ;;----------------------------------------------------------------
+ ;; Subtraction
+@@ -530,7 +529,7 @@
+ (define_insn "subdi3"
+ [(set (match_operand:DI 0 "register_operand" "=&d")
+ (minus:DI (match_operand:DI 1 "register_operand" "d")
+- (match_operand:DI 2 "arith_operand32" "d")))]
++ (match_operand:DI 2 "register_operand" "d")))]
+ ""
+ "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1"
+ [(set_attr "type" "darith")
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-PR-target-83013.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-PR-target-83013.patch
new file mode 100644
index 0000000..42bfd3c
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-PR-target-83013.patch
@@ -0,0 +1,32 @@
+From f17cdebf4e0defaefce927176ddeb9717de073d2 Mon Sep 17 00:00:00 2001
+From: law <law@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Mon, 15 Jan 2018 06:02:19 +0000
+Subject: [PATCH] PR target/83013
+
+ * config/microblaze/microblaze.c (microblaze_asm_output_ident):
+ Use .pushsection/.popsection.
+
+git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@256681 138bc75d-0d04-0410-961f-82ee72b054a4
+Upstream-Status: Backport [backport from trunk pre-release v8]
+---
+ gcc/config/microblaze/microblaze.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index d0f86fd460..a98aca1235 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -3371,7 +3371,9 @@ microblaze_asm_output_ident (const char *string)
+ else
+ section_asm_op = READONLY_DATA_SECTION_ASM_OP;
+
+- buf = ACONCAT ((section_asm_op, "\n\t.ascii \"", string, "\\0\"\n", NULL));
++ buf = ACONCAT (("\t.pushsection", section_asm_op,
++ "\n\t.ascii \"", string, "\\0\"\n",
++ "\t.popsection\n", NULL));
+ symtab->finalize_toplevel_asm (build_string (strlen (buf), buf));
+ }
+
+--
+2.15.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch
new file mode 100644
index 0000000..c0a427e
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch
@@ -0,0 +1,36 @@
+From ab2cb6320138c173b20fee8ce6e8d4afa4696384 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:16 -0700
+Subject: [PATCH] dejagnu static testing on qemu, suppress warnings
+
+For dejagnu static testing on qemu, suppress warnings about multiple
+definitions from the test function and libc in line with method used by
+powerpc. Dynamic linking and using a qemu binary which understands
+sysroot resolves all test failures with builtins
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
+index ba16b09c41..ada149912b 100644
+--- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
++++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
+@@ -48,6 +48,10 @@ if { [istarget *-*-eabi*]
+ lappend additional_flags "-Wl,--allow-multiple-definition"
+ }
+
++if [istarget "microblaze*-*-linux*"] {
++ lappend additional_flags "-Wl,-zmuldefs"
++}
++
+ foreach src [lsort [find $srcdir/$subdir *.c]] {
+ if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} {
+ c-torture-execute [list $src \
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch
new file mode 100644
index 0000000..b428d12
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch
@@ -0,0 +1,118 @@
+From 7f0a129701ce9809d79ea4618f3293062bd24bbf Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:18 -0700
+Subject: [PATCH] Testsuite - explicitly add -fivopts for tests that depend on
+ it
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C | 2 +-
+ gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/loop-2.c | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/loop-4.c | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/loop-5.c | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/pr19590.c | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c | 2 +-
+ 8 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
+index 438db88204..ede883eb28 100644
+--- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
++++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target { i?86-*-* x86_64-*-* } } } */
+-/* { dg-options "-O2 -fdump-tree-ivopts-details" } */
++/* { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" } */
+
+ void test (int *b, int *e, int stride)
+ {
+diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
+index eb72581390..02f3ea4a7d 100644
+--- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
++++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
+@@ -1,5 +1,5 @@
+ // { dg-do compile }
+-// { dg-options "-O2 -fdump-tree-ivopts-details" }
++// { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" }
+
+ class MinimalVec3
+ {
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
+index bda2516735..22c8a5dcff 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
+@@ -1,7 +1,7 @@
+ /* A test for strength reduction and induction variable elimination. */
+
+ /* { dg-do compile } */
+-/* { dg-options "-O1 -fdump-tree-optimized" } */
++/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
+ /* { dg-require-effective-target size32plus } */
+
+ /* Size of this structure should be sufficiently weird so that no memory
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
+index f0770abdbb..65d74c8e62 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
+@@ -1,7 +1,7 @@
+ /* A test for strength reduction and induction variable elimination. */
+
+ /* { dg-do compile } */
+-/* { dg-options "-O1 -fdump-tree-optimized" } */
++/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
+ /* { dg-require-effective-target size32plus } */
+
+ /* Size of this structure should be sufficiently weird so that no memory
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
+index 5f42857fe1..9bc86ee0d2 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
+@@ -1,7 +1,7 @@
+ /* A test for induction variable merging. */
+
+ /* { dg-do compile } */
+-/* { dg-options "-O1 -fdump-tree-optimized" } */
++/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
+
+ void foo(long);
+
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
+index 3c8ee06016..db192a657f 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -Wunsafe-loop-optimizations" } */
++/* { dg-options "-O2 -fivopts -Wunsafe-loop-optimizations" } */
+ extern void g(void);
+
+ void
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
+index 2c6cfc6f83..648e6e67e8 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fdump-tree-ivopts" } */
++/* { dg-options "-O2 -fivopts -fdump-tree-ivopts" } */
+
+ void vnum_test8(int *data)
+ {
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
+index e911bfcd52..5d3e7e0801 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-Os -fdump-tree-optimized" } */
++/* { dg-options "-Os -fivopts -fdump-tree-optimized" } */
+
+ /* Slightly changed testcase from PR middle-end/40815. */
+ void bar(char*, char*, int);
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0006-Add-MicroBlaze-to-target-supports-for-atomic-builtin.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0006-Add-MicroBlaze-to-target-supports-for-atomic-builtin.patch
new file mode 100644
index 0000000..6fad8bf
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0006-Add-MicroBlaze-to-target-supports-for-atomic-builtin.patch
@@ -0,0 +1,37 @@
+From 8bcdd551f7fe585126ea3173ece976fbc646c34a Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:20 -0700
+Subject: [PATCH] Add MicroBlaze to target-supports for atomic builtin tests
+
+MicroBlaze added to supported targets for atomic builtin tests.
+
+Changelog/testsuite
+
+2014-02-14 David Holsgrove <david.holsgrove@xilinx.com>
+
+ * gcc/testsuite/lib/target-supports.exp: Add microblaze to
+ check_effective_target_sync_int_long.
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/testsuite/lib/target-supports.exp | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
+index 342af270ab..b0f510e596 100644
+--- a/gcc/testsuite/lib/target-supports.exp
++++ b/gcc/testsuite/lib/target-supports.exp
+@@ -6715,6 +6715,7 @@ proc check_effective_target_sync_int_long { } {
+ && [check_effective_target_arm_acq_rel])
+ || [istarget bfin*-*linux*]
+ || [istarget hppa*-*linux*]
++ || [istarget microblaze*-*linux*]
+ || [istarget s390*-*-*]
+ || [istarget powerpc*-*-*]
+ || [istarget crisv32-*-*] || [istarget cris-*-*]
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0007-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0007-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch
new file mode 100644
index 0000000..069329f
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0007-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch
@@ -0,0 +1,46 @@
+From 4622988b62335af6ef17d58bf10940419fd0f99f Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:21 -0700
+Subject: [PATCH] Update MicroBlaze strings test for new scan-assembly output
+ resulting in use of $LC label
+
+ChangeLog/testsuite
+
+2014-02-14 David Holsgrove <david.holsgrove@xilinx.com>
+
+ * gcc/testsuite/gcc.target/microblaze/others/strings1.c: Update
+ to include $LC label.
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/testsuite/gcc.target/microblaze/others/strings1.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/testsuite/gcc.target/microblaze/others/strings1.c b/gcc/testsuite/gcc.target/microblaze/others/strings1.c
+index 7a63faf79f..0403b7bdca 100644
+--- a/gcc/testsuite/gcc.target/microblaze/others/strings1.c
++++ b/gcc/testsuite/gcc.target/microblaze/others/strings1.c
+@@ -1,13 +1,15 @@
+ /* { dg-options "-O3" } */
+
++/* { dg-final { scan-assembler "\.rodata*" } } */
++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),\\\$LC.*" } } */
++/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),*" } } */
++
+ #include <string.h>
+
+-/* { dg-final { scan-assembler "\.rodata*" } } */
+ extern void somefunc (char *);
+ int testfunc ()
+ {
+ char string2[80];
+-/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,.LC*" } } */
+ strcpy (string2, "hello");
+ somefunc (string2);
+ }
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0008-Allow-MicroBlaze-.weakext-pattern-in-testsuite.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0008-Allow-MicroBlaze-.weakext-pattern-in-testsuite.patch
new file mode 100644
index 0000000..dbfeb52
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0008-Allow-MicroBlaze-.weakext-pattern-in-testsuite.patch
@@ -0,0 +1,68 @@
+From 037809e91bfed9c501ecd5272ff6d3ce96edf76c Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:22 -0700
+Subject: [PATCH] Allow MicroBlaze .weakext pattern in testsuite
+
+Allow MicroBlaze .weakext pattern in regex match Extend regex pattern to
+include optional ext at the end of .weak to match the MicroBlaze weak
+label .weakext
+
+ChangeLog/testsuite
+
+2014-02-14 David Holsgrove <david.holsgrove@xilinx.com>
+
+ * gcc/testsuite/g++.dg/abi/rtti3.C: Extend scan-assembler
+ pattern to take optional ext after .weak.
+ * gcc/testsuite/g++.dg/abi/thunk4.C: Likewise.
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/testsuite/g++.dg/abi/rtti3.C | 4 ++--
+ gcc/testsuite/g++.dg/abi/thunk3.C | 2 +-
+ gcc/testsuite/g++.dg/abi/thunk4.C | 2 +-
+ 3 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/gcc/testsuite/g++.dg/abi/rtti3.C b/gcc/testsuite/g++.dg/abi/rtti3.C
+index 0316bcb5de..5a39a0811f 100644
+--- a/gcc/testsuite/g++.dg/abi/rtti3.C
++++ b/gcc/testsuite/g++.dg/abi/rtti3.C
+@@ -3,8 +3,8 @@
+
+ // { dg-require-weak "" }
+ // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } { "*" } { "" } }
+-// { dg-final { scan-assembler ".weak\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* hppa*-*-hpux* } } } } }
+-// { dg-final { scan-assembler-not ".weak\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } }
++// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* } } } } }
++// { dg-final { scan-assembler-not ".weak(ext)?\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } }
+ // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZTSPP1A" { target { *-*-darwin* } } } }
+ // { dg-final { scan-assembler-not ".weak_definition\[ \t\]_?_ZTIPP1A" { target { *-*-darwin* } } } }
+
+diff --git a/gcc/testsuite/g++.dg/abi/thunk3.C b/gcc/testsuite/g++.dg/abi/thunk3.C
+index f2347f79ec..dcec8a771a 100644
+--- a/gcc/testsuite/g++.dg/abi/thunk3.C
++++ b/gcc/testsuite/g++.dg/abi/thunk3.C
+@@ -1,5 +1,5 @@
+ // { dg-require-weak "" }
+-// { dg-final { scan-assembler-not ".weak\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
++// { dg-final { scan-assembler-not ".weak(ext)?\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
+ // { dg-final { scan-assembler-not ".weak_definition\[\t \]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } }
+
+ struct Base
+diff --git a/gcc/testsuite/g++.dg/abi/thunk4.C b/gcc/testsuite/g++.dg/abi/thunk4.C
+index fa5fbd4327..79cb311cab 100644
+--- a/gcc/testsuite/g++.dg/abi/thunk4.C
++++ b/gcc/testsuite/g++.dg/abi/thunk4.C
+@@ -1,6 +1,6 @@
+ // { dg-require-weak "" }
+ // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } { "*" } { "" } }
+-// { dg-final { scan-assembler ".weak\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
++// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
+ // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } }
+
+ struct Base
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0009-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0009-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch
new file mode 100644
index 0000000..6b9dd99
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0009-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch
@@ -0,0 +1,32 @@
+From 23a04c06c2a689fed151eeb94c45ea9b512036ae Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:23 -0700
+Subject: [PATCH] Add MicroBlaze to check_profiling_available Testsuite
+
+Add MicroBlaze to check_profiling_available Testsuite, add
+microblaze*-*-* target in check_profiling_available inline with other
+archs setting profiling_available_saved to 0
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/testsuite/lib/target-supports.exp | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
+index b0f510e596..fffb690e49 100644
+--- a/gcc/testsuite/lib/target-supports.exp
++++ b/gcc/testsuite/lib/target-supports.exp
+@@ -625,6 +625,7 @@ proc check_profiling_available { test_what } {
+ || [istarget m68k-*-elf]
+ || [istarget m68k-*-uclinux*]
+ || [istarget mips*-*-elf*]
++ || [istarget microblaze*-*-*]
+ || [istarget mmix-*-*]
+ || [istarget mn10300-*-elf*]
+ || [istarget moxie-*-elf*]
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0010-Fix-atomic-side-effects.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0010-Fix-atomic-side-effects.patch
new file mode 100644
index 0000000..c21ca81
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0010-Fix-atomic-side-effects.patch
@@ -0,0 +1,69 @@
+From c1e8a1419e8f5d18e7135fb4fe3bf21941125008 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:24 -0700
+Subject: [PATCH] Fix atomic side effects.
+
+In atomic_compare_and_swapsi, add side effects to prevent incorrect
+assumptions during optimization. Previously, the outputs were considered
+unused; this generated assembly code with undefined side effects after
+invocation of the atomic.
+
+Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.md | 3 +++
+ gcc/config/microblaze/sync.md | 21 +++++++++++++--------
+ 2 files changed, 16 insertions(+), 8 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 8a372d7ebb..59d629b559 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -41,6 +41,9 @@
+ (UNSPEC_CMP 104) ;; signed compare
+ (UNSPEC_CMPU 105) ;; unsigned compare
+ (UNSPEC_TLS 106) ;; jump table
++ (UNSPECV_CAS_BOOL 201) ;; compare and swap (bool)
++ (UNSPECV_CAS_VAL 202) ;; compare and swap (val)
++ (UNSPECV_CAS_MEM 203) ;; compare and swap (mem)
+ ])
+
+ (define_c_enum "unspec" [
+diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
+index 8125bd8d63..edf4bdd811 100644
+--- a/gcc/config/microblaze/sync.md
++++ b/gcc/config/microblaze/sync.md
+@@ -18,14 +18,19 @@
+ ;; <http://www.gnu.org/licenses/>.
+
+ (define_insn "atomic_compare_and_swapsi"
+- [(match_operand:SI 0 "register_operand" "=&d") ;; bool output
+- (match_operand:SI 1 "register_operand" "=&d") ;; val output
+- (match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory
+- (match_operand:SI 3 "register_operand" "d") ;; expected value
+- (match_operand:SI 4 "register_operand" "d") ;; desired value
+- (match_operand:SI 5 "const_int_operand" "") ;; is_weak
+- (match_operand:SI 6 "const_int_operand" "") ;; mod_s
+- (match_operand:SI 7 "const_int_operand" "") ;; mod_f
++ [(set (match_operand:SI 0 "register_operand" "=&d") ;; bool output
++ (unspec_volatile:SI
++ [(match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory
++ (match_operand:SI 3 "register_operand" "d") ;; expected value
++ (match_operand:SI 4 "register_operand" "d")] ;; desired value
++ UNSPECV_CAS_BOOL))
++ (set (match_operand:SI 1 "register_operand" "=&d") ;; val output
++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_VAL))
++ (set (match_dup 2)
++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_MEM))
++ (match_operand:SI 5 "const_int_operand" "") ;; is_weak
++ (match_operand:SI 6 "const_int_operand" "") ;; mod_s
++ (match_operand:SI 7 "const_int_operand" "") ;; mod_f
+ (clobber (match_scratch:SI 8 "=&d"))]
+ ""
+ {
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0011-Fix-atomic-boolean-return-value.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0011-Fix-atomic-boolean-return-value.patch
new file mode 100644
index 0000000..f4bc16e
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0011-Fix-atomic-boolean-return-value.patch
@@ -0,0 +1,44 @@
+From a5957bdf7acfde0a65eeba90bae11f5619bf96af Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:25 -0700
+Subject: [PATCH] Fix atomic boolean return value.
+
+In atomic_compare_and_swapsi, fix boolean return value. Previously, it
+contained zero if successful and non-zero if unsuccessful.
+
+Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/sync.md | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
+index edf4bdd811..aadb414728 100644
+--- a/gcc/config/microblaze/sync.md
++++ b/gcc/config/microblaze/sync.md
+@@ -34,15 +34,16 @@
+ (clobber (match_scratch:SI 8 "=&d"))]
+ ""
+ {
+- output_asm_insn ("addc \tr0,r0,r0", operands);
++ output_asm_insn ("add \t%0,r0,r0", operands);
+ output_asm_insn ("lwx \t%1,%y2,r0", operands);
+ output_asm_insn ("addic\t%8,r0,0", operands);
+ output_asm_insn ("bnei \t%8,.-8", operands);
+- output_asm_insn ("cmp \t%0,%1,%3", operands);
+- output_asm_insn ("bnei \t%0,.+16", operands);
++ output_asm_insn ("cmp \t%8,%1,%3", operands);
++ output_asm_insn ("bnei \t%8,.+20", operands);
+ output_asm_insn ("swx \t%4,%y2,r0", operands);
+ output_asm_insn ("addic\t%8,r0,0", operands);
+ output_asm_insn ("bnei \t%8,.-28", operands);
++ output_asm_insn ("addi \t%0,r0,1", operands);
+ return "";
+ }
+ )
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch
new file mode 100644
index 0000000..464f59e
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch
@@ -0,0 +1,37 @@
+From 1a9dcdb578452ecd53e0aec65fe6279233218778 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:26 -0700
+Subject: [PATCH] Fix the Microblaze crash with msmall-divides flag
+
+Fix the Microblaze crash with msmall-divides flag Compiler is crashing
+when we use msmall-divides and mxl-barrel-shift flag. This is because
+when use above flags microblaze_expand_divide function will be called
+for division operation. In microblaze_expand_divide function we are
+using sub_reg but MicroBlaze doesn't have subreg register due to this
+compiler was crashing. Changed the logic to avoid sub_reg call
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index bba6983b65..15080db539 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -3527,8 +3527,7 @@ microblaze_expand_divide (rtx operands[])
+ mem_rtx = gen_rtx_MEM (QImode,
+ gen_rtx_PLUS (Pmode, regt1, div_table_rtx));
+
+- insn = emit_insn (gen_movqi (regqi, mem_rtx));
+- insn = emit_insn (gen_movsi (operands[0], gen_rtx_SUBREG (SImode, regqi, 0)));
++ insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
+ jump = emit_jump_insn_after (gen_jump (div_end_label), insn);
+ JUMP_LABEL (jump) = div_end_label;
+ LABEL_NUSES (div_end_label) = 1;
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0013-Add-MicroBlaze-ashrsi_3_with_size_opt.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0013-Add-MicroBlaze-ashrsi_3_with_size_opt.patch
new file mode 100644
index 0000000..6005e21
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0013-Add-MicroBlaze-ashrsi_3_with_size_opt.patch
@@ -0,0 +1,53 @@
+From c32df2ec3d269d19b631a17cea2b6d19bbb98c27 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:27 -0700
+Subject: [PATCH] Add MicroBlaze ashrsi_3_with_size_opt
+
+Added ashrsi3_with_size_opt Added ashrsi3_with_size_opt pattern to
+optimize the sra instructions when the -Os optimization is used.
+lshrsi3_with_size_opt is being removed as it has conflicts with unsigned
+int variables
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 59d629b559..8c0a97e032 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -1505,6 +1505,27 @@
+ (set_attr "length" "4,4")]
+ )
+
++(define_insn "*ashrsi3_with_size_opt"
++ [(set (match_operand:SI 0 "register_operand" "=&d")
++ (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
++ (match_operand:SI 2 "immediate_operand" "I")))]
++ "(INTVAL (operands[2]) > 5 && optimize_size)"
++ {
++ operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
++
++ output_asm_insn ("ori\t%3,r0,%2", operands);
++ if (REGNO (operands[0]) != REGNO (operands[1]))
++ output_asm_insn ("addk\t%0,%1,r0", operands);
++
++ output_asm_insn ("addik\t%3,%3,-1", operands);
++ output_asm_insn ("bneid\t%3,.-4", operands);
++ return "sra\t%0,%0";
++ }
++ [(set_attr "type" "arith")
++ (set_attr "mode" "SI")
++ (set_attr "length" "20")]
++)
++
+ (define_insn "*ashrsi_inline"
+ [(set (match_operand:SI 0 "register_operand" "=&d")
+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0014-Removed-MicroBlaze-moddi3-routinue.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0014-Removed-MicroBlaze-moddi3-routinue.patch
new file mode 100644
index 0000000..b019571
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0014-Removed-MicroBlaze-moddi3-routinue.patch
@@ -0,0 +1,156 @@
+From a68e94fc57bcf60cb730894e49dde55d081397f5 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:28 -0700
+Subject: [PATCH] Removed MicroBlaze moddi3 routinue
+
+Removed moddi3 routinue Using the default moddi3 function as the
+existing implementation has many bugs
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ libgcc/config/microblaze/moddi3.S | 115 ----------------------------------
+ libgcc/config/microblaze/t-microblaze | 3 +-
+ 2 files changed, 1 insertion(+), 117 deletions(-)
+ delete mode 100644 libgcc/config/microblaze/moddi3.S
+
+diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S
+deleted file mode 100644
+index bcea079476..0000000000
+--- a/libgcc/config/microblaze/moddi3.S
++++ /dev/null
+@@ -1,115 +0,0 @@
+-###################################
+-#
+-# Copyright (C) 2009-2017 Free Software Foundation, Inc.
+-#
+-# Contributed by Michael Eager <eager@eagercon.com>.
+-#
+-# This file is free software; you can redistribute it and/or modify it
+-# under the terms of the GNU General Public License as published by the
+-# Free Software Foundation; either version 3, or (at your option) any
+-# later version.
+-#
+-# GCC is distributed in the hope that it will be useful, but WITHOUT
+-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+-# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+-# License for more details.
+-#
+-# Under Section 7 of GPL version 3, you are granted additional
+-# permissions described in the GCC Runtime Library Exception, version
+-# 3.1, as published by the Free Software Foundation.
+-#
+-# You should have received a copy of the GNU General Public License and
+-# a copy of the GCC Runtime Library Exception along with this program;
+-# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+-# <http://www.gnu.org/licenses/>.
+-#
+-# modsi3.S
+-#
+-# modulo operation for 64 bit integers.
+-#
+-#######################################
+-
+-
+- .globl __moddi3
+- .ent __moddi3
+-__moddi3:
+- .frame r1,0,r15
+-
+-#Change the stack pointer value and Save callee saved regs
+- addik r1,r1,-24
+- swi r25,r1,0
+- swi r26,r1,4
+- swi r27,r1,8 # used for sign
+- swi r28,r1,12 # used for loop count
+- swi r29,r1,16 # Used for div value High
+- swi r30,r1,20 # Used for div value Low
+-
+-#Check for Zero Value in the divisor/dividend
+- OR r9,r5,r6 # Check for the op1 being zero
+- BEQID r9,$LaResult_Is_Zero # Result is zero
+- OR r9,r7,r8 # Check for the dividend being zero
+- BEQI r9,$LaDiv_By_Zero # Div_by_Zero # Division Error
+- BGEId r5,$La1_Pos
+- XOR r27,r5,r7 # Get the sign of the result
+- RSUBI r6,r6,0 # Make dividend positive
+- RSUBIC r5,r5,0 # Make dividend positive
+-$La1_Pos:
+- BGEI r7,$La2_Pos
+- RSUBI r8,r8,0 # Make Divisor Positive
+- RSUBIC r9,r9,0 # Make Divisor Positive
+-$La2_Pos:
+- ADDIK r4,r0,0 # Clear mod low
+- ADDIK r3,r0,0 # Clear mod high
+- ADDIK r29,r0,0 # clear div high
+- ADDIK r30,r0,0 # clear div low
+- ADDIK r28,r0,64 # Initialize the loop count
+- # First part try to find the first '1' in the r5/r6
+-$LaDIV1:
+- ADD r6,r6,r6
+- ADDC r5,r5,r5 # left shift logical r5
+- BGEID r5,$LaDIV1
+- ADDIK r28,r28,-1
+-$LaDIV2:
+- ADD r6,r6,r6
+- ADDC r5,r5,r5 # left shift logical r5/r6 get the '1' into the Carry
+- ADDC r4,r4,r4 # Move that bit into the Mod register
+- ADDC r3,r3,r3 # Move carry into high mod register
+- rsub r18,r7,r3 # Compare the High Parts of Mod and Divisor
+- bnei r18,$L_High_EQ
+- rsub r18,r6,r4 # Compare Low Parts only if Mod[h] == Divisor[h]
+-$L_High_EQ:
+- rSUB r26,r8,r4 # Subtract divisor[L] from Mod[L]
+- rsubc r25,r7,r3 # Subtract divisor[H] from Mod[H]
+- BLTi r25,$LaMOD_TOO_SMALL
+- OR r3,r0,r25 # move r25 to mod [h]
+- OR r4,r0,r26 # move r26 to mod [l]
+- ADDI r30,r30,1
+- ADDC r29,r29,r0
+-$LaMOD_TOO_SMALL:
+- ADDIK r28,r28,-1
+- BEQi r28,$LaLOOP_END
+- ADD r30,r30,r30 # Shift in the '1' into div [low]
+- ADDC r29,r29,r29 # Move the carry generated into high
+- BRI $LaDIV2 # Div2
+-$LaLOOP_END:
+- BGEI r27,$LaRETURN_HERE
+- rsubi r30,r30,0
+- rsubc r29,r29,r0
+- BRI $LaRETURN_HERE
+-$LaDiv_By_Zero:
+-$LaResult_Is_Zero:
+- or r29,r0,r0 # set result to 0 [High]
+- or r30,r0,r0 # set result to 0 [Low]
+-$LaRETURN_HERE:
+-# Restore values of CSRs and that of r29 and the divisor and the dividend
+-
+- lwi r25,r1,0
+- lwi r26,r1,4
+- lwi r27,r1,8
+- lwi r28,r1,12
+- lwi r29,r1,16
+- lwi r30,r1,20
+- rtsd r15,8
+- addik r1,r1,24
+- .end __moddi3
+-
+diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
+index 96959f0292..8d954a4957 100644
+--- a/libgcc/config/microblaze/t-microblaze
++++ b/libgcc/config/microblaze/t-microblaze
+@@ -1,8 +1,7 @@
+-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _moddi3 _mulsi3 _udivsi3 _umodsi3
++LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
+
+ LIB2ADD += \
+ $(srcdir)/config/microblaze/divsi3.S \
+- $(srcdir)/config/microblaze/moddi3.S \
+ $(srcdir)/config/microblaze/modsi3.S \
+ $(srcdir)/config/microblaze/muldi3_hard.S \
+ $(srcdir)/config/microblaze/mulsi3.S \
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0015-MicroBlaze-fixed-missing-save-of-r18-in-fast_interru.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0015-MicroBlaze-fixed-missing-save-of-r18-in-fast_interru.patch
new file mode 100644
index 0000000..e75bebe
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0015-MicroBlaze-fixed-missing-save-of-r18-in-fast_interru.patch
@@ -0,0 +1,46 @@
+From 79ea36649467aea6045a49c7d016f8f9245efb8c Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:29 -0700
+Subject: [PATCH] MicroBlaze fixed missing save of r18 in fast_interrupt
+
+Fixed missing save of r18 in fast_interrupt. Register 18 is used as a
+clobber register, and must be stored when entering a fast_interrupt.
+Before this fix, register 18 was only saved if it was used directly in
+the interrupt function.
+
+However, if the fast_interrupt function called a function that used
+r18, the register would not be saved, and thus be mangled
+upon returning from the interrupt.
+
+Changelog
+
+2014-02-27 Klaus Petersen <klauspetersen@gmail.com>
+
+ * gcc/config/microblaze/microblaze.c: Check for fast_interrupt in
+ microblaze_must_save_register.
+
+Signed-off-by: Klaus Petersen <klauspetersen@gmail.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 15080db539..558796cad9 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -1943,7 +1943,7 @@ microblaze_must_save_register (int regno)
+ {
+ if (df_regs_ever_live_p (regno)
+ || regno == MB_ABI_MSR_SAVE_REG
+- || (interrupt_handler
++ || ((interrupt_handler || fast_interrupt)
+ && (regno == MB_ABI_ASM_TEMP_REGNUM
+ || regno == MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM)))
+ return 1;
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0016-MicroBlaze-use-bralid-for-profiler-calls.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0016-MicroBlaze-use-bralid-for-profiler-calls.patch
new file mode 100644
index 0000000..f5de718
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0016-MicroBlaze-use-bralid-for-profiler-calls.patch
@@ -0,0 +1,29 @@
+From 6ed57ee8219e5d09a294b329dd7c531a1868dc8a Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:31 -0700
+Subject: [PATCH] MicroBlaze use bralid for profiler calls
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index ccd77e8b4d..0dd8b853e2 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -519,7 +519,7 @@ typedef struct microblaze_args
+
+ #define FUNCTION_PROFILER(FILE, LABELNO) { \
+ { \
+- fprintf (FILE, "\tbrki\tr16,_mcount\n"); \
++ fprintf (FILE, "\tbralid\tr15,_mcount\nnop\n"); \
+ } \
+ }
+
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch
new file mode 100644
index 0000000..4041e11
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch
@@ -0,0 +1,38 @@
+From 25b161dd222311cca0e6ab46b7f3be444bd4bbe8 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:32 -0700
+Subject: [PATCH] Disable fivopts by default Turn off ivopts by default.
+ Interferes with cse.
+
+Changelog
+
+2013-03-18 Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+
+ * gcc/common/config/microblaze/microblaze-common.c
+ (microblaze_option_optimization_table): Disable fivopts by default.
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/common/config/microblaze/microblaze-common.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c
+index 4975663305..8ddc4c3cbe 100644
+--- a/gcc/common/config/microblaze/microblaze-common.c
++++ b/gcc/common/config/microblaze/microblaze-common.c
+@@ -27,6 +27,8 @@
+ /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
+ static const struct default_options microblaze_option_optimization_table[] =
+ {
++ /* Turn off ivopts by default. It messes up cse. */
++ { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 },
+ { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
+ { OPT_LEVELS_NONE, 0, NULL, 0 }
+ };
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0018-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0018-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch
new file mode 100644
index 0000000..5239d2b
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0018-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch
@@ -0,0 +1,104 @@
+From 02d8afd50a868e827ac8b6b6243c69922cd694ed Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:34 -0700
+Subject: [PATCH] Add INIT_PRIORITY support Added TARGET_ASM_CONSTRUCTOR and
+ TARGET_ASM_DESTRUCTOR macros.
+
+These macros allows users to control the order of initialization
+of objects defined at namespace scope with the init_priority
+attribute by specifying a relative priority, a constant integral
+expression currently bounded between 101 and 65535 inclusive.
+
+Lower numbers indicate a higher priority.
+
+Changelog
+
+2013-11-26 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+
+ * gcc/config/microblaze/microblaze.c: Add microblaze_asm_constructor,
+ microblaze_asm_destructor. Define TARGET_ASM_CONSTRUCTOR and
+ TARGET_ASM_DESTRUCTOR.
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.c | 53 ++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 53 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 558796cad9..c1b0172bcf 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2530,6 +2530,53 @@ print_operand_address (FILE * file, rtx addr)
+ }
+ }
+
++/* Output an element in the table of global constructors. */
++void
++microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority)
++{
++ const char *section = ".ctors";
++ char buf[16];
++
++ if (priority != DEFAULT_INIT_PRIORITY)
++ {
++ sprintf (buf, ".ctors.%.5u",
++ /* Invert the numbering so the linker puts us in the proper
++ order; constructors are run from right to left, and the
++ linker sorts in increasing order. */
++ MAX_INIT_PRIORITY - priority);
++ section = buf;
++ }
++
++ switch_to_section (get_section (section, 0, NULL));
++ assemble_align (POINTER_SIZE);
++ fputs ("\t.word\t", asm_out_file);
++ output_addr_const (asm_out_file, symbol);
++ fputs ("\n", asm_out_file);
++}
++
++/* Output an element in the table of global destructors. */
++void
++microblaze_asm_destructor (rtx symbol, int priority)
++{
++ const char *section = ".dtors";
++ char buf[16];
++ if (priority != DEFAULT_INIT_PRIORITY)
++ {
++ sprintf (buf, ".dtors.%.5u",
++ /* Invert the numbering so the linker puts us in the proper
++ order; constructors are run from right to left, and the
++ linker sorts in increasing order. */
++ MAX_INIT_PRIORITY - priority);
++ section = buf;
++ }
++
++ switch_to_section (get_section (section, 0, NULL));
++ assemble_align (POINTER_SIZE);
++ fputs ("\t.word\t", asm_out_file);
++ output_addr_const (asm_out_file, symbol);
++ fputs ("\n", asm_out_file);
++}
++
+ /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
+ is used, so that we don't emit an .extern for it in
+ microblaze_asm_file_end. */
+@@ -3775,6 +3822,12 @@ microblaze_machine_dependent_reorg (void)
+ #undef TARGET_ATTRIBUTE_TABLE
+ #define TARGET_ATTRIBUTE_TABLE microblaze_attribute_table
+
++#undef TARGET_ASM_CONSTRUCTOR
++#define TARGET_ASM_CONSTRUCTOR microblaze_asm_constructor
++
++#undef TARGET_ASM_DESTRUCTOR
++#define TARGET_ASM_DESTRUCTOR microblaze_asm_destructor
++
+ #undef TARGET_IN_SMALL_DATA_P
+ #define TARGET_IN_SMALL_DATA_P microblaze_elf_in_small_data_p
+
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0019-MicroBlaze-add-optimized-lshrsi3-When-barrel-shifter.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0019-MicroBlaze-add-optimized-lshrsi3-When-barrel-shifter.patch
new file mode 100644
index 0000000..049ce3f
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0019-MicroBlaze-add-optimized-lshrsi3-When-barrel-shifter.patch
@@ -0,0 +1,87 @@
+From 0b2061ac7706df97da3e8b3c01c6a5cfc504c16e Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:35 -0700
+Subject: [PATCH] MicroBlaze add optimized lshrsi3 When barrel shifter is not
+ present
+
+Add optimized lshrsi3 When barrel shifter is not present, the immediate
+value is greater than #5 and optimization is -OS, the compiler will
+generate shift operation using loop.
+
+Changelog
+
+2013-11-26 David Holsgrove <david.holsgrove@xilinx.com>
+
+ * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn
+
+ChangeLog/testsuite
+
+2014-02-12 David Holsgrove <david.holsgrove@xilinx.com>
+
+ * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test.
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++
+ .../gcc.target/microblaze/others/lshrsi_Os_1.c | 13 +++++++++++++
+ 2 files changed, 34 insertions(+)
+ create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 8c0a97e032..abbe97c15f 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -1615,6 +1615,27 @@
+ (set_attr "length" "4,4")]
+ )
+
++(define_insn "*lshrsi3_with_size_opt"
++ [(set (match_operand:SI 0 "register_operand" "=&d")
++ (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
++ (match_operand:SI 2 "immediate_operand" "I")))]
++ "(INTVAL (operands[2]) > 5 && optimize_size)"
++ {
++ operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
++
++ output_asm_insn ("ori\t%3,r0,%2", operands);
++ if (REGNO (operands[0]) != REGNO (operands[1]))
++ output_asm_insn ("addk\t%0,%1,r0", operands);
++
++ output_asm_insn ("addik\t%3,%3,-1", operands);
++ output_asm_insn ("bneid\t%3,.-4", operands);
++ return "srl\t%0,%0";
++ }
++ [(set_attr "type" "multi")
++ (set_attr "mode" "SI")
++ (set_attr "length" "20")]
++)
++
+ (define_insn "*lshrsi_inline"
+ [(set (match_operand:SI 0 "register_operand" "=&d")
+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
+diff --git a/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
+new file mode 100644
+index 0000000000..32a3be7c76
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
+@@ -0,0 +1,13 @@
++/* { dg-options "-Os -mno-xl-barrel-shift" } */
++
++void testfunc(void)
++{
++ unsigned volatile int z = 8192;
++ z >>= 8;
++}
++/* { dg-final { scan-assembler-not "\bsrli" } } */
++/* { dg-final { scan-assembler "\ori\tr18,r0" } } */
++/* { dg-final { scan-assembler "addk\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0" } } */
++/* { dg-final { scan-assembler "addik\tr18,r18,-1" } } */
++/* { dg-final { scan-assembler "bneid\tr18,.-4" } } */
++/* { dg-final { scan-assembler "\srl\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])" } } */
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0020-Modified-MicroBlaze-trap-instruction.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0020-Modified-MicroBlaze-trap-instruction.patch
new file mode 100644
index 0000000..00e79b9
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0020-Modified-MicroBlaze-trap-instruction.patch
@@ -0,0 +1,33 @@
+From 1b9bd76840fc1e67770a23c58bf18a24a25eb2b9 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:36 -0700
+Subject: [PATCH] Modified MicroBlaze trap instruction
+
+Modified trap instruction The instruction was wrongly written to brki
+r0,-1 it should be bri r0. Modified with the correct instruction
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.md | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index abbe97c15f..a3954a24b6 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2343,7 +2343,7 @@
+ (define_insn "trap"
+ [(trap_if (const_int 1) (const_int 0))]
+ ""
+- "brki\tr0,-1"
++ "bri\t0"
+ [(set_attr "type" "trap")]
+ )
+
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0021-Reducing-Stack-space-for-arguments-Currently-in-Micr.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0021-Reducing-Stack-space-for-arguments-Currently-in-Micr.patch
new file mode 100644
index 0000000..ead929a
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0021-Reducing-Stack-space-for-arguments-Currently-in-Micr.patch
@@ -0,0 +1,212 @@
+From f5416ee7ddc6e4853e57ed15fb2bf630de2c3b12 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:37 -0700
+Subject: [PATCH] Reducing Stack space for arguments Currently in Microblaze
+ target stack space
+
+Reducing Stack space for arguments Currently in Microblaze target stack
+space for arguments in register is being allocated even if there are no
+arguments in the function. This patch will optimize the extra 24 bytes
+that are being allocated.
+
+ChangeLog:
+2015-04-17 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+ Ajit Agarwal <ajitkum@xilinx.com>
+
+ * microblaze.c (microblaze_parm_needs_stack, microblaze_function_parms_need_stack): New
+ * microblaze.c (REG_PARM_STACK_SPACE): Modify
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze-protos.h | 1 +
+ gcc/config/microblaze/microblaze.c | 134 +++++++++++++++++++++++++++++-
+ gcc/config/microblaze/microblaze.h | 4 +-
+ 3 files changed, 136 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
+index b56e052ae4..a1408629cc 100644
+--- a/gcc/config/microblaze/microblaze-protos.h
++++ b/gcc/config/microblaze/microblaze-protos.h
+@@ -57,6 +57,7 @@ extern int symbol_mentioned_p (rtx);
+ extern int label_mentioned_p (rtx);
+ extern bool microblaze_cannot_force_const_mem (machine_mode, rtx);
+ extern void microblaze_eh_return (rtx op0);
++int microblaze_reg_parm_stack_space(tree fun);
+ #endif /* RTX_CODE */
+
+ /* Declare functions in microblaze-c.c. */
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index c1b0172bcf..f46dffff0d 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -1965,6 +1965,138 @@ microblaze_must_save_register (int regno)
+ return 0;
+ }
+
++static bool
++microblaze_parm_needs_stack (cumulative_args_t args_so_far, tree type)
++{
++ enum machine_mode mode;
++ int unsignedp;
++ rtx entry_parm;
++
++ /* Catch errors. */
++ if (type == NULL || type == error_mark_node)
++ return true;
++
++ if (TREE_CODE (type) == POINTER_TYPE)
++ return true;
++
++ /* Handle types with no storage requirement. */
++ if (TYPE_MODE (type) == VOIDmode)
++ return false;
++
++ /* Handle complex types. */
++ if (TREE_CODE (type) == COMPLEX_TYPE)
++ return (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type))
++ || microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type)));
++
++ /* Handle transparent aggregates. */
++ if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
++ && TYPE_TRANSPARENT_AGGR (type))
++ type = TREE_TYPE (first_field (type));
++
++ /* See if this arg was passed by invisible reference. */
++ if (pass_by_reference (get_cumulative_args (args_so_far),
++ TYPE_MODE (type), type, true))
++ type = build_pointer_type (type);
++
++ /* Find mode as it is passed by the ABI. */
++ unsignedp = TYPE_UNSIGNED (type);
++ mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
++
++/* If there is no incoming register, we need a stack. */
++ entry_parm = microblaze_function_arg (args_so_far, mode, type, true);
++ if (entry_parm == NULL)
++ return true;
++
++ /* Likewise if we need to pass both in registers and on the stack. */
++ if (GET_CODE (entry_parm) == PARALLEL
++ && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
++ return true;
++
++ /* Also true if we're partially in registers and partially not. */
++ if (function_arg_partial_bytes (args_so_far, mode, type, true) != 0)
++ return true;
++
++ /* Update info on where next arg arrives in registers. */
++ microblaze_function_arg_advance (args_so_far, mode, type, true);
++ return false;
++ }
++
++static bool
++microblaze_function_parms_need_stack (tree fun, bool incoming)
++{
++ tree fntype, result;
++ CUMULATIVE_ARGS args_so_far_v;
++ cumulative_args_t args_so_far;
++ int num_of_args = 0;
++
++ /* Must be a libcall, all of which only use reg parms. */
++ if (!fun)
++ return true;
++
++ fntype = fun;
++ if (!TYPE_P (fun))
++ fntype = TREE_TYPE (fun);
++
++ /* Varargs functions need the parameter save area. */
++ if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
++ return true;
++
++ INIT_CUMULATIVE_ARGS(args_so_far_v, fntype, NULL_RTX,0,0);
++ args_so_far = pack_cumulative_args (&args_so_far_v);
++
++ /* When incoming, we will have been passed the function decl.
++ * It is necessary to use the decl to handle K&R style functions,
++ * where TYPE_ARG_TYPES may not be available. */
++ if (incoming)
++ {
++ gcc_assert (DECL_P (fun));
++ result = DECL_RESULT (fun);
++ }
++ else
++ result = TREE_TYPE (fntype);
++
++ if (result && aggregate_value_p (result, fntype))
++ {
++ if (!TYPE_P (result))
++ result = build_pointer_type (result);
++ microblaze_parm_needs_stack (args_so_far, result);
++ }
++
++ if (incoming)
++ {
++ tree parm;
++ for (parm = DECL_ARGUMENTS (fun);
++ parm && parm != void_list_node;
++ parm = TREE_CHAIN (parm))
++ if (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
++ return true;
++ }
++ else
++ {
++ function_args_iterator args_iter;
++ tree arg_type;
++
++ FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
++ {
++ num_of_args++;
++ if (microblaze_parm_needs_stack (args_so_far, arg_type))
++ return true;
++ }
++ }
++
++ if (num_of_args > 3) return true;
++
++ return false;
++}
++
++int microblaze_reg_parm_stack_space(tree fun)
++{
++ if (microblaze_function_parms_need_stack (fun,false))
++ return MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD;
++ else
++ return 0;
++}
++
+ /* Return the bytes needed to compute the frame pointer from the current
+ stack pointer.
+
+@@ -3275,7 +3407,7 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+ emit_insn (gen_indirect_jump (temp2));
+
+ /* Run just enough of rest_of_compilation. This sequence was
+- "borrowed" from rs6000.c. */
++ "borrowed" from microblaze.c. */
+ insn = get_insns ();
+ shorten_branches (insn);
+ final_start_function (insn, file, 1);
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 0dd8b853e2..82e7e890be 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -467,9 +467,9 @@ extern struct microblaze_frame_info current_frame_info;
+
+ #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
+
+-#define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)
++#define REG_PARM_STACK_SPACE(FNDECL) microblaze_reg_parm_stack_space(FNDECL)
+
+-#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
++#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
+
+ #define STACK_BOUNDARY 32
+
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0022-Inline-Expansion-of-fsqrt-builtin.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0022-Inline-Expansion-of-fsqrt-builtin.patch
new file mode 100644
index 0000000..6de1702
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0022-Inline-Expansion-of-fsqrt-builtin.patch
@@ -0,0 +1,64 @@
+From cf85f09a0fade1e7827828a3dc9a526c212f3be7 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:39 -0700
+Subject: [PATCH] Inline Expansion of fsqrt builtin
+
+Inline Expansion of fsqrt builtin. The changes are made in the patch for
+the inline expansion of the fsqrt builtin with fqrt instruction. The
+sqrt math function takes double as argument and return double as
+argument. The pattern is selected while expanding the unary op through
+expand_unop which passes DFmode and the DFmode pattern was not there
+returning zero. Thus the sqrt math function is not inlined and expanded.
+The pattern with DFmode argument is added. Also the source and
+destination argument is not same the DF through two different
+consecutive registers with lower 32 bit is the argument passed to sqrt
+and the higher 32 bit is zero. If the source and destinations are
+different the DFmode 64 bits registers is not set properly giving the
+problem in runtime. Such changes are taken care in the implementation of
+the pattern for DFmode for inline expansion of the sqrt.
+
+ChangeLog:
+
+2015-06-16 Ajit Agarwal <ajitkum@xilinx.com>
+ Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+
+ * config/microblaze/microblaze.md (sqrtdf2): New
+ pattern.
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.md | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index a3954a24b6..13f8803428 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -449,6 +449,20 @@
+ (set_attr "mode" "SF")
+ (set_attr "length" "4")])
+
++(define_insn "sqrtdf2"
++ [(set (match_operand:DF 0 "register_operand" "=d")
++ (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))]
++ "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT"
++ {
++ if (REGNO (operands[0]) == REGNO (operands[1]))
++ return "fsqrt\t%0,%1";
++ else
++ return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0";
++ }
++ [(set_attr "type" "fsqrt")
++ (set_attr "mode" "SF")
++ (set_attr "length" "4")])
++
+ (define_insn "fix_truncsfsi2"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (fix:SI (match_operand:SF 1 "register_operand" "d")))]
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0023-Update-MicroBlaze-ashlsi3-movsf-patterns.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0023-Update-MicroBlaze-ashlsi3-movsf-patterns.patch
new file mode 100644
index 0000000..d8eb769
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0023-Update-MicroBlaze-ashlsi3-movsf-patterns.patch
@@ -0,0 +1,78 @@
+From f269f552e1abf182dc3749e0f29b1529fc82644a Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:42 -0700
+Subject: [PATCH] Update MicroBlaze ashlsi3 & movsf patterns
+
+This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in
+print_operand of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and
+movsf_internal patterns beacuse HOST_WIDE_INT_PRINT_HEX is generating
+64-bit value which our instruction doesn't support so using gen_int_mode
+function
+
+ChangeLog:
+
+2016-01-07 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+ Ajit Agarwal <ajitkum@xilinx.com>
+
+ * microblaze.md (ashlsi3_with_mul_nodelay,
+ ashlsi3_with_mul_delay,
+ movsf_internal):
+ Updated the patterns to use gen_int_mode function
+ * microblaze.c (print_operand):
+ updated the 'F' case to use "unsinged int" instead
+ of HOST_WIDE_INT_PRINT_HEX
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.c | 2 +-
+ gcc/config/microblaze/microblaze.md | 10 ++++++++--
+ 2 files changed, 9 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index f46dffff0d..663b20a022 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2507,7 +2507,7 @@ print_operand (FILE * file, rtx op, int letter)
+ unsigned long value_long;
+ REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op),
+ value_long);
+- fprintf (file, HOST_WIDE_INT_PRINT_HEX, value_long);
++ fprintf (file, "0x%08x", (unsigned int) value_long);
+ }
+ else
+ {
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 13f8803428..b9c62b6d0f 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -1366,7 +1366,10 @@
+ (match_operand:SI 2 "immediate_operand" "I")))]
+ "!TARGET_SOFT_MUL
+ && ((1 << INTVAL (operands[2])) <= 32767 && (1 << INTVAL (operands[2])) >= -32768)"
+- "muli\t%0,%1,%m2"
++ {
++ operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode);
++ return "muli\t%0,%1,%2";
++ }
+ ;; This MUL will not generate an imm. Can go into a delay slot.
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")
+@@ -1378,7 +1381,10 @@
+ (ashift:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "immediate_operand" "I")))]
+ "!TARGET_SOFT_MUL"
+- "muli\t%0,%1,%m2"
++ {
++ operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode);
++ return "muli\t%0,%1,%2";
++ }
+ ;; This MUL will generate an IMM. Cannot go into a delay slot
+ [(set_attr "type" "no_delay_arith")
+ (set_attr "mode" "SI")
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0024-8-stage-pipeline-for-microblaze.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0024-8-stage-pipeline-for-microblaze.patch
new file mode 100644
index 0000000..6faa625
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0024-8-stage-pipeline-for-microblaze.patch
@@ -0,0 +1,195 @@
+From 17353cc4ba521f5ad928a1ede61cf03110e366ae Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:43 -0700
+Subject: [PATCH] 8-stage pipeline for microblaze
+
+This patch adds the support for the 8-stage pipeline. The new 8-stage
+pipeline reduces the latencies of float & integer division drastically
+
+ChangeLog:
+
+2016-01-18 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+
+ * microblaze.md (define_automaton mbpipe_8): New
+ * microblaze.c (microblaze_option_override): Update
+ Updated the logic to generate only when MB version is 10.0
+ * microblaze.h (pipeline_type): Update
+ Update the enum with MICROBLAZE_PIPE_8
+ * microblaze.opt (mxl-frequency): New
+ New flag added for 8-stage pipeline
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.c | 13 ++++++
+ gcc/config/microblaze/microblaze.h | 3 +-
+ gcc/config/microblaze/microblaze.md | 79 +++++++++++++++++++++++++++++++++++-
+ gcc/config/microblaze/microblaze.opt | 4 ++
+ 4 files changed, 96 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 663b20a022..e7697bf30d 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -1773,6 +1773,19 @@ microblaze_option_override (void)
+ warning (0, "-mxl-reorder requires -mxl-pattern-compare for -mcpu=v8.30.a");
+ TARGET_REORDER = 0;
+ }
++ ver = ver_int - microblaze_version_to_int("v10.0");
++ if (ver < 0)
++ {
++ if (TARGET_AREA_OPTIMIZED_2)
++ warning (0, "-mxl-frequency can be used only with -mcpu=v10.0 or greater");
++ }
++ else
++ {
++ if (TARGET_AREA_OPTIMIZED_2)
++ microblaze_pipe = MICROBLAZE_PIPE_8;
++ if (TARGET_BARREL_SHIFT)
++ microblaze_has_bitfield = 1;
++ }
+
+ if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL)
+ error ("-mxl-multiply-high requires -mno-xl-soft-mul");
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 82e7e890be..3f48e48f10 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -27,7 +27,8 @@
+ enum pipeline_type
+ {
+ MICROBLAZE_PIPE_3 = 0,
+- MICROBLAZE_PIPE_5 = 1
++ MICROBLAZE_PIPE_5 = 1,
++ MICROBLAZE_PIPE_8 = 2
+ };
+
+ #define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index b9c62b6d0f..61d6412dac 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -35,6 +35,7 @@
+ (R_GOT 20) ;; GOT ptr reg
+ (MB_PIPE_3 0) ;; Microblaze 3-stage pipeline
+ (MB_PIPE_5 1) ;; Microblaze 5-stage pipeline
++ (MB_PIPE_8 2) ;; Microblaze 8-stage pipeline
+ (UNSPEC_SET_GOT 101) ;;
+ (UNSPEC_GOTOFF 102) ;; GOT offset
+ (UNSPEC_PLT 103) ;; jump table
+@@ -80,7 +81,7 @@
+ ;; bshift Shift operations
+
+ (define_attr "type"
+- "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap"
++ "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,fint,trap"
+ (const_string "unknown"))
+
+ ;; Main data type used by the insn
+@@ -222,6 +223,80 @@
+ ;;-----------------------------------------------------------------
+
+
++
++;;----------------------------------------------------------------
++;; Microblaze 8-stage pipeline description (v10.0 and later)
++;;----------------------------------------------------------------
++
++(define_automaton "mbpipe_8")
++(define_cpu_unit "mb8_issue,mb8_iu,mb8_wb,mb8_fpu,mb8_fpu_2,mb8_mul,mb8_mul_2,mb8_div,mb8_div_2,mb8_bs,mb8_bs_2" "mbpipe_8")
++
++(define_insn_reservation "mb8-integer" 1
++ (and (eq_attr "type" "branch,jump,call,arith,darith,icmp,nop,no_delay_arith")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_iu,mb8_wb")
++
++(define_insn_reservation "mb8-special-move" 2
++ (and (eq_attr "type" "move")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_iu*2,mb8_wb")
++
++(define_insn_reservation "mb8-mem-load" 3
++ (and (eq_attr "type" "load,no_delay_load")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_iu,mb8_wb")
++
++(define_insn_reservation "mb8-mem-store" 1
++ (and (eq_attr "type" "store,no_delay_store")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_iu,mb8_wb")
++
++(define_insn_reservation "mb8-mul" 3
++ (and (eq_attr "type" "imul,no_delay_imul")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_mul,mb8_mul_2*2,mb8_wb")
++
++(define_insn_reservation "mb8-div" 30
++ (and (eq_attr "type" "idiv")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_div,mb8_div_2*29,mb8_wb")
++
++(define_insn_reservation "mb8-bs" 2
++ (and (eq_attr "type" "bshift")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_bs,mb8_bs_2,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-add-sub-mul" 1
++ (and (eq_attr "type" "fadd,frsub,fmul")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_fpu,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-fcmp" 3
++ (and (eq_attr "type" "fcmp")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_fpu,mb8_fpu*2,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-div" 24
++ (and (eq_attr "type" "fdiv")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_fpu,mb8_fpu_2*23,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-sqrt" 23
++ (and (eq_attr "type" "fsqrt")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_fpu,mb8_fpu_2*22,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-fcvt" 1
++ (and (eq_attr "type" "fcvt")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_fpu,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-fint" 2
++ (and (eq_attr "type" "fint")
++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
++ "mb8_issue,mb8_fpu,mb8_wb")
++
++
+ ;;----------------------------------------------------------------
+ ;; Microblaze 5-stage pipeline description (v5.00.a and later)
+ ;;----------------------------------------------------------------
+@@ -468,7 +543,7 @@
+ (fix:SI (match_operand:SF 1 "register_operand" "d")))]
+ "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+ "fint\t%0,%1"
+- [(set_attr "type" "fcvt")
++ [(set_attr "type" "fint")
+ (set_attr "mode" "SF")
+ (set_attr "length" "4")])
+
+diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
+index 8847c3daf8..85a9929d74 100644
+--- a/gcc/config/microblaze/microblaze.opt
++++ b/gcc/config/microblaze/microblaze.opt
+@@ -129,3 +129,7 @@ Use hardware prefetch instruction
+
+ mxl-mode-xilkernel
+ Target
++
++mxl-frequency
++Target Mask(AREA_OPTIMIZED_2)
++Use 8 stage pipeline (frequency optimization)
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch
new file mode 100644
index 0000000..ff8e610
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch
@@ -0,0 +1,72 @@
+From fabd23a354496701b4a9ebf6931485b0d61c7bbe Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:45 -0700
+Subject: [PATCH] MicroBlaze correct the const high double immediate value
+
+With this patch the loading of the DI mode immediate values will be
+using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE
+functions, as CONST_DOUBLE_HIGH was returning the sign extension value
+even of the unsigned long long constants also
+
+ChangeLog:
+
+2016-02-03 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+ Ajit Agarwal <ajitkum@xilinx.com>
+
+ * microblaze.c (print_operand): Use REAL_VALUE_FROM_CONST_DOUBLE &
+ REAL_VALUE_TO_TARGET_DOUBLE
+ * long.c (new): Added new testcase
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.c | 6 ++++--
+ gcc/testsuite/gcc.target/microblaze/long.c | 10 ++++++++++
+ 2 files changed, 14 insertions(+), 2 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/microblaze/long.c
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index e7697bf30d..96bf6e1cab 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2493,14 +2493,16 @@ print_operand (FILE * file, rtx op, int letter)
+ else if (letter == 'h' || letter == 'j')
+ {
+ long val[2];
++ long l[2];
+ if (code == CONST_DOUBLE)
+ {
+ if (GET_MODE (op) == DFmode)
+ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
+ else
+ {
+- val[0] = CONST_DOUBLE_HIGH (op);
+- val[1] = CONST_DOUBLE_LOW (op);
++ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
++ val[1] = l[WORDS_BIG_ENDIAN == 0];
++ val[0] = l[WORDS_BIG_ENDIAN != 0];
+ }
+ }
+ else if (code == CONST_INT)
+diff --git a/gcc/testsuite/gcc.target/microblaze/long.c b/gcc/testsuite/gcc.target/microblaze/long.c
+new file mode 100644
+index 0000000000..4d4518619d
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/microblaze/long.c
+@@ -0,0 +1,10 @@
++/* { dg-options "-O0" } */
++#define BASEADDR 0xF0000000ULL
++int main ()
++{
++ unsigned long long start;
++ start = (unsigned long long) BASEADDR;
++ return 0;
++}
++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0x00000000" } } */
++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0xf0000000" } } */
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0026-Fix-internal-compiler-error-with-msmall-divides.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0026-Fix-internal-compiler-error-with-msmall-divides.patch
new file mode 100644
index 0000000..7ea28ee
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0026-Fix-internal-compiler-error-with-msmall-divides.patch
@@ -0,0 +1,42 @@
+From 2149d85f1f7375dd97bf961b2bdb693d6d931c13 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:46 -0700
+Subject: [PATCH] Fix internal compiler error with msmall-divides
+
+This patch will fix the internal error microblaze_expand_divide function
+which comes because of rtx PLUS where the mem_rtx is of type SI and the
+operand is of type QImode. This patch modifies the mem_rtx as QImode and
+Plus as QImode to fix the error.
+
+ChangeLog:
+
+2016-02-23 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+ Ajit Agarwal <ajitkum@xilinx.com>
+
+ * microblaze.c (microblaze_expand_divide): Update
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 96bf6e1cab..a41121264e 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -3719,7 +3719,7 @@ microblaze_expand_divide (rtx operands[])
+ emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
+ emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
+ mem_rtx = gen_rtx_MEM (QImode,
+- gen_rtx_PLUS (Pmode, regt1, div_table_rtx));
++ gen_rtx_PLUS (QImode, regt1, div_table_rtx));
+
+ insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
+ jump = emit_jump_insn_after (gen_jump (div_end_label), insn);
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0027-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0027-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch
new file mode 100644
index 0000000..97422ae
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0027-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch
@@ -0,0 +1,48 @@
+From 34049c9fcaa256befad032cbcd8aa74beecf13dc Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:47 -0700
+Subject: [PATCH] Fix the calculation of high word in a long long 64-bit
+
+This patch will change the calculation of high word in a long long 64-bit.
+Earlier to this patch the high word of long long word (0xF0000000ULL) is
+coming to be 0xFFFFFFFF and low word is 0xF0000000. Instead the high word
+should be 0x00000000 and the low word should be 0xF0000000. This patch
+removes the condition of checking high word = 0 & low word < 0.
+This check is not required for the correctness of calculating 32-bit high
+and low words in a 64-bit long long.
+
+ChangeLog:
+
+2016-03-01 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+ Ajit Agarwal <ajitkum@xilinx.com>
+
+ * config/microblaze/microblaze.c (print_operand): Remove the
+ condition of checking high word = 0 & low word < 0.
+ * testsuite/gcc.target/microblaze/others/long.c: Add -O0 option.
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index a41121264e..2ed64971fb 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2509,9 +2509,6 @@ print_operand (FILE * file, rtx op, int letter)
+ {
+ val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
+ val[1] = INTVAL (op) & 0x00000000ffffffffLL;
+- if (val[0] == 0 && val[1] < 0)
+- val[0] = -1;
+-
+ }
+ fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
+ }
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0028-Add-new-bit-field-instructions.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0028-Add-new-bit-field-instructions.patch
new file mode 100644
index 0000000..02940e2
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0028-Add-new-bit-field-instructions.patch
@@ -0,0 +1,126 @@
+From 90b6f833bd59f89d4192a3dc787fc2c9115b9c00 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:48 -0700
+Subject: [PATCH] Add new bit-field instructions
+
+This patches adds new bsefi and bsifi instructions. BSEFI- The
+instruction shall extract a bit field from a register and place it
+right-adjusted in the destination register. The other bits in the
+destination register shall be set to zero BSIFI- The instruction shall
+insert a right-adjusted bit field from a register at another position in
+the destination register. The rest of the bits in the destination
+register shall be unchanged
+
+ChangeLog:
+
+2016-02-03 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+
+ * microblaze.md (Update): Added new patterns
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.md | 73 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 73 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 61d6412dac..7a00629922 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -980,6 +980,8 @@
+ (set_attr "mode" "DI")
+ (set_attr "length" "20,20,20")])
+
++
++
+ ;;----------------------------------------------------------------
+ ;; Data movement
+ ;;----------------------------------------------------------------
+@@ -1774,6 +1776,7 @@
+ (set_attr "length" "28")]
+ )
+
++
+ ;;----------------------------------------------------------------
+ ;; Setting a register from an integer comparison.
+ ;;----------------------------------------------------------------
+@@ -2473,4 +2476,74 @@
+ DONE;
+ }")
+
++(define_expand "extvsi"
++ [(set (match_operand:SI 0 "register_operand" "r")
++ (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
++ (match_operand:SI 2 "immediate_operand" "I")
++ (match_operand:SI 3 "immediate_operand" "I")))]
++"TARGET_HAS_BITFIELD"
++"
++{
++ unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
++ unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
++
++ if ((len == 0) || (pos + len > 32) )
++ FAIL;
++
++ ;;if (!register_operand (operands[1], VOIDmode))
++ ;; FAIL;
++ if (operands[0] == operands[1])
++ FAIL;
++ if (GET_CODE (operands[1]) == ASHIFT)
++ FAIL;
++;; operands[2] = GEN_INT(INTVAL(operands[2])+1 );
++ emit_insn (gen_extv_32 (operands[0], operands[1],
++ operands[2], operands[3]));
++ DONE;
++}")
++
++(define_insn "extv_32"
++ [(set (match_operand:SI 0 "register_operand" "=r")
++ (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
++ (match_operand:SI 2 "immediate_operand" "I")
++ (match_operand:SI 3 "immediate_operand" "I")))]
++ "TARGET_HAS_BITFIELD && (UINTVAL (operands[2]) > 0)
++ && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)"
++ "bsefi %0,%1,%2,%3"
++ [(set_attr "type" "bshift")
++ (set_attr "length" "4")])
++
++(define_expand "insvsi"
++ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
++ (match_operand:SI 1 "immediate_operand" "I")
++ (match_operand:SI 2 "immediate_operand" "I"))
++ (match_operand:SI 3 "register_operand" "r"))]
++ "TARGET_HAS_BITFIELD"
++ "
++{
++ unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
++ unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
++
++ if (len <= 0 || pos + len > 32)
++ FAIL;
++
++ ;;if (!register_operand (operands[0], VOIDmode))
++ ;; FAIL;
++
++ emit_insn (gen_insv_32 (operands[0], operands[1],
++ operands[2], operands[3]));
++ DONE;
++}")
++
++(define_insn "insv_32"
++ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
++ (match_operand:SI 1 "immediate_operand" "I")
++ (match_operand:SI 2 "immediate_operand" "I"))
++ (match_operand:SI 3 "register_operand" "r"))]
++ "TARGET_HAS_BITFIELD && UINTVAL (operands[1]) > 0
++ && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32"
++ "bsifi %0, %3, %1, %2"
++ [(set_attr "type" "bshift")
++ (set_attr "length" "4")])
++
+ (include "sync.md")
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0029-Fix-bug-in-MB-version-calculation.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0029-Fix-bug-in-MB-version-calculation.patch
new file mode 100644
index 0000000..c3e4bc9
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0029-Fix-bug-in-MB-version-calculation.patch
@@ -0,0 +1,250 @@
+From 3eada9d81437d378ef24f11a8bd046fee5b3505a Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:49 -0700
+Subject: [PATCH] Fix bug in MB version calculation
+
+This patch fixes the bug in microblaze_version_to_int function. Earlier
+the conversion of vXX.YY.Z to int has a bug which is fixed now.
+
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.c | 147 ++++++++++++++++++-------------------
+ 1 file changed, 70 insertions(+), 77 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 2ed64971fb..55dba83882 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -239,6 +239,63 @@ section *sdata2_section;
+ #define TARGET_HAVE_TLS true
+ #endif
+
++/* Convert a version number of the form "vX.YY.Z" to an integer encoding
++ for easier range comparison. */
++static int
++microblaze_version_to_int (const char *version)
++{
++ const char *p, *v;
++ const char *tmpl = "vXX.YY.Z";
++ int iver1 =0, iver2 =0, iver3 =0;
++
++ p = version;
++ v = tmpl;
++
++ while (*p)
++ {
++ if (*v == 'X')
++ { /* Looking for major */
++ if (*p == '.')
++ {
++ *v++;
++ }
++ else
++ {
++ if (!(*p >= '0' && *p <= '9'))
++ return -1;
++ iver1 += (int) (*p - '0');
++ iver1 *= 1000;
++ }
++ }
++ else if (*v == 'Y')
++ { /* Looking for minor */
++ if (!(*p >= '0' && *p <= '9'))
++ return -1;
++ iver2 += (int) (*p - '0');
++ iver2 *= 10;
++ }
++ else if (*v == 'Z')
++ { /* Looking for compat */
++ if (!(*p >= 'a' && *p <= 'z'))
++ return -1;
++ iver3 = ((int) (*p)) - 96;
++ }
++ else
++ {
++ if (*p != *v)
++ return -1;
++ }
++
++ v++;
++ p++;
++ }
++
++ if (*p)
++ return -1;
++
++ return iver1 + iver2 + iver3;
++}
++
+ /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
+ static bool
+ microblaze_const_double_ok (rtx op, machine_mode mode)
+@@ -1267,8 +1324,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
+ {
+ if (TARGET_BARREL_SHIFT)
+ {
+- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a")
+- >= 0)
++ if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a"))
+ *total = COSTS_N_INSNS (1);
+ else
+ *total = COSTS_N_INSNS (2);
+@@ -1329,8 +1385,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
+ }
+ else if (!TARGET_SOFT_MUL)
+ {
+- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a")
+- >= 0)
++ if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a"))
+ *total = COSTS_N_INSNS (1);
+ else
+ *total = COSTS_N_INSNS (3);
+@@ -1610,72 +1665,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
+ return 0;
+ }
+
+-/* Convert a version number of the form "vX.YY.Z" to an integer encoding
+- for easier range comparison. */
+-static int
+-microblaze_version_to_int (const char *version)
+-{
+- const char *p, *v;
+- const char *tmpl = "vXX.YY.Z";
+- int iver = 0;
+-
+- p = version;
+- v = tmpl;
+-
+- while (*p)
+- {
+- if (*v == 'X')
+- { /* Looking for major */
+- if (*p == '.')
+- {
+- v++;
+- }
+- else
+- {
+- if (!(*p >= '0' && *p <= '9'))
+- return -1;
+- iver += (int) (*p - '0');
+- iver *= 10;
+- }
+- }
+- else if (*v == 'Y')
+- { /* Looking for minor */
+- if (!(*p >= '0' && *p <= '9'))
+- return -1;
+- iver += (int) (*p - '0');
+- iver *= 10;
+- }
+- else if (*v == 'Z')
+- { /* Looking for compat */
+- if (!(*p >= 'a' && *p <= 'z'))
+- return -1;
+- iver *= 10;
+- iver += (int) (*p - 'a');
+- }
+- else
+- {
+- if (*p != *v)
+- return -1;
+- }
+-
+- v++;
+- p++;
+- }
+-
+- if (*p)
+- return -1;
+-
+- return iver;
+-}
+-
+-
+ static void
+ microblaze_option_override (void)
+ {
+ register int i, start;
+ register int regno;
+ register machine_mode mode;
+- int ver;
++ int ver,ver_int;
+
+ microblaze_section_threshold = (global_options_set.x_g_switch_value
+ ? g_switch_value
+@@ -1696,13 +1692,13 @@ microblaze_option_override (void)
+ /* Check the MicroBlaze CPU version for any special action to be done. */
+ if (microblaze_select_cpu == NULL)
+ microblaze_select_cpu = MICROBLAZE_DEFAULT_CPU;
+- ver = microblaze_version_to_int (microblaze_select_cpu);
+- if (ver == -1)
++ ver_int = microblaze_version_to_int (microblaze_select_cpu);
++ if (ver_int == -1)
+ {
+ error ("%qs is an invalid argument to -mcpu=", microblaze_select_cpu);
+ }
+
+- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v3.00.a");
++ ver = ver_int - microblaze_version_to_int("v3.00.a");
+ if (ver < 0)
+ {
+ /* No hardware exceptions in earlier versions. So no worries. */
+@@ -1713,8 +1709,7 @@ microblaze_option_override (void)
+ microblaze_pipe = MICROBLAZE_PIPE_3;
+ }
+ else if (ver == 0
+- || (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v4.00.b")
+- == 0))
++ || (ver_int == microblaze_version_to_int("v4.00.b")))
+ {
+ #if 0
+ microblaze_select_flags |= (MICROBLAZE_MASK_NO_UNSAFE_DELAY);
+@@ -1731,11 +1726,9 @@ microblaze_option_override (void)
+ #endif
+ microblaze_no_unsafe_delay = 0;
+ microblaze_pipe = MICROBLAZE_PIPE_5;
+- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") == 0
+- || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu,
+- "v5.00.b") == 0
+- || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu,
+- "v5.00.c") == 0)
++ if ((ver_int == microblaze_version_to_int("v5.00.a"))
++ || (ver_int == microblaze_version_to_int("v5.00.b"))
++ || (ver_int == microblaze_version_to_int("v5.00.c")))
+ {
+ /* Pattern compares are to be turned on by default only when
+ compiling for MB v5.00.'z'. */
+@@ -1743,7 +1736,7 @@ microblaze_option_override (void)
+ }
+ }
+
+- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v6.00.a");
++ ver = ver_int - microblaze_version_to_int("v6.00.a");
+ if (ver < 0)
+ {
+ if (TARGET_MULTIPLY_HIGH)
+@@ -1751,7 +1744,7 @@ microblaze_option_override (void)
+ "-mxl-multiply-high can be used only with -mcpu=v6.00.a or greater");
+ }
+
+- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.10.a");
++ ver = ver_int - microblaze_version_to_int("v8.10.a");
+ microblaze_has_clz = 1;
+ if (ver < 0)
+ {
+@@ -1760,7 +1753,7 @@ microblaze_option_override (void)
+ }
+
+ /* TARGET_REORDER defaults to 2 if -mxl-reorder not specified. */
+- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.30.a");
++ ver = ver_int - microblaze_version_to_int("v8.30.a");
+ if (ver < 0)
+ {
+ if (TARGET_REORDER == 1)
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0030-MicroBlaze-fixing-the-bug-in-the-bit-field-instructi.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0030-MicroBlaze-fixing-the-bug-in-the-bit-field-instructi.patch
new file mode 100644
index 0000000..1d877be
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0030-MicroBlaze-fixing-the-bug-in-the-bit-field-instructi.patch
@@ -0,0 +1,52 @@
+From 0c740ddd203433ef8d979348c085269f8b97cbfc Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:50 -0700
+Subject: [PATCH] MicroBlaze fixing the bug in the bit-field instruction.
+
+Bit field instruction should be generated only if mcpu >10.0
+
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.c | 3 +++
+ gcc/config/microblaze/microblaze.h | 2 ++
+ 2 files changed, 5 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 55dba83882..4f6d399bba 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -159,6 +159,9 @@ int microblaze_no_unsafe_delay;
+ /* Set to one if the targeted core has the CLZ insn. */
+ int microblaze_has_clz = 0;
+
++/* Set to one if the targeted core has barrel-shift and cpu > 10.0 */
++int microblaze_has_bitfield = 0;
++
+ /* Which CPU pipeline do we use. We haven't really standardized on a CPU
+ version having only a particular type of pipeline. There can still be
+ options on the CPU to scale pipeline features up or down. :(
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 3f48e48f10..712525f856 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[];
+
+ extern int microblaze_no_unsafe_delay;
+ extern int microblaze_has_clz;
++extern int microblaze_has_bitfield;
+ extern enum pipeline_type microblaze_pipe;
+
+ #define OBJECT_FORMAT_ELF
+@@ -62,6 +63,7 @@ extern enum pipeline_type microblaze_pipe;
+
+ /* Do we have CLZ? */
+ #define TARGET_HAS_CLZ (TARGET_PATTERN_COMPARE && microblaze_has_clz)
++#define TARGET_HAS_BITFIELD (TARGET_BARREL_SHIFT && microblaze_has_bitfield)
+
+ /* The default is to support PIC. */
+ #define TARGET_SUPPORTS_PIC 1
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0031-Fixing-the-issue-with-MicroBlaze-builtin_alloc.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0031-Fixing-the-issue-with-MicroBlaze-builtin_alloc.patch
new file mode 100644
index 0000000..3786a71
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0031-Fixing-the-issue-with-MicroBlaze-builtin_alloc.patch
@@ -0,0 +1,48 @@
+From fdb99f97b41f7cd06b81e668b88463d0fc2cbe87 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:54 -0700
+Subject: [PATCH] Fixing the issue with MicroBlaze builtin_alloc
+
+Fixing the issue with the builtin_alloc. Register r18 was not properly
+handling the stack pattern which was resolved by using free available
+register
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.md | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 7a00629922..68c3b22bd4 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2076,10 +2076,10 @@
+ ""
+ {
+ rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
+- rtx rtmp = gen_rtx_REG (SImode, R_TMP);
++ rtx reg = gen_reg_rtx (Pmode);
+ rtx neg_op0;
+
+- emit_move_insn (rtmp, retaddr);
++ emit_move_insn (reg, retaddr);
+ if (GET_CODE (operands[1]) != CONST_INT)
+ {
+ neg_op0 = gen_reg_rtx (Pmode);
+@@ -2088,9 +2088,9 @@
+ neg_op0 = GEN_INT (- INTVAL (operands[1]));
+
+ emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
+- emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), rtmp);
++ emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), reg);
+ emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
+- emit_insn (gen_rtx_CLOBBER (SImode, rtmp));
++ emit_insn (gen_rtx_CLOBBER (SImode, reg));
+ DONE;
+ }
+ )
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0032-MicroBlaze-remove-bitfield-instructions-macros.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0032-MicroBlaze-remove-bitfield-instructions-macros.patch
new file mode 100644
index 0000000..29bc752
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0032-MicroBlaze-remove-bitfield-instructions-macros.patch
@@ -0,0 +1,83 @@
+From 646fe1dbaca06f2fe2df4c0da3fa20e0aff0a4ec Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:56 -0700
+Subject: [PATCH] MicroBlaze remove bitfield instructions macros
+
+Remove the conditions in the bit field expand macros to generate the
+instructions in structure bit-field usecases
+
+ChangeLog:
+
+2018-08-16 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+
+ * gcc/config/microblaze/microblaze.md:
+ remove the expand constraints
+
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.md | 40 +++++--------------------------------
+ 1 file changed, 5 insertions(+), 35 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 68c3b22bd4..ef53c3069e 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2482,25 +2482,8 @@
+ (match_operand:SI 2 "immediate_operand" "I")
+ (match_operand:SI 3 "immediate_operand" "I")))]
+ "TARGET_HAS_BITFIELD"
+-"
+-{
+- unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
+- unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
+-
+- if ((len == 0) || (pos + len > 32) )
+- FAIL;
+-
+- ;;if (!register_operand (operands[1], VOIDmode))
+- ;; FAIL;
+- if (operands[0] == operands[1])
+- FAIL;
+- if (GET_CODE (operands[1]) == ASHIFT)
+- FAIL;
+-;; operands[2] = GEN_INT(INTVAL(operands[2])+1 );
+- emit_insn (gen_extv_32 (operands[0], operands[1],
+- operands[2], operands[3]));
+- DONE;
+-}")
++""
++)
+
+ (define_insn "extv_32"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+@@ -2518,22 +2501,9 @@
+ (match_operand:SI 1 "immediate_operand" "I")
+ (match_operand:SI 2 "immediate_operand" "I"))
+ (match_operand:SI 3 "register_operand" "r"))]
+- "TARGET_HAS_BITFIELD"
+- "
+-{
+- unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
+- unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
+-
+- if (len <= 0 || pos + len > 32)
+- FAIL;
+-
+- ;;if (!register_operand (operands[0], VOIDmode))
+- ;; FAIL;
+-
+- emit_insn (gen_insv_32 (operands[0], operands[1],
+- operands[2], operands[3]));
+- DONE;
+-}")
++"TARGET_HAS_BITFIELD"
++""
++)
+
+ (define_insn "insv_32"
+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch
new file mode 100644
index 0000000..eaae566
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch
@@ -0,0 +1,51 @@
+From e2a7a582945d24ede55393462a3360f377f45478 Mon Sep 17 00:00:00 2001
+From: Nathan Rossi <nathan@nathanrossi.com>
+Date: Sun, 5 Nov 2017 23:03:54 +1000
+Subject: [PATCH] MicroBlaze fix signed bit fields with bit field instructions
+
+The 'extv' definition is expected to sign extended the result based on
+the width of the bit field.
+
+ https://gcc.gnu.org/onlinedocs/gccint/Standard-Names.html#index-extvm-instruction-pattern
+
+The MicroBlaze 'bsefi' instruction does not sign extended, it zero
+extends. There is no option for the instruction to sign extended the
+result and no simple instruction or expression to implement a variant
+length sign extend (only sext8/sext16 instructions exist).
+
+As such these definitions needs to be changed to the zero extended
+variant of 'extv' which is 'extzv'. This change updates the existing
+definitions to allow for signed bit fields to function correctly and be
+sign extended.
+
+Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.md | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index ef53c3069e..b52be42d6e 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2476,7 +2476,7 @@
+ DONE;
+ }")
+
+-(define_expand "extvsi"
++(define_expand "extzvsi"
+ [(set (match_operand:SI 0 "register_operand" "r")
+ (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "immediate_operand" "I")
+@@ -2485,7 +2485,7 @@
+ ""
+ )
+
+-(define_insn "extv_32"
++(define_insn "extzv_32"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "immediate_operand" "I")
+--
+2.14.2
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_7.%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_7.%.bbappend
new file mode 100644
index 0000000..9770af6
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_7.%.bbappend
@@ -0,0 +1,38 @@
+# Add MicroBlaze Patches (only when using MicroBlaze)
+FILESEXTRAPATHS_append_microblaze := "${THISDIR}/gcc-7:"
+SRC_URI_append_microblaze = " \
+ file://0001-Revert.patch \
+ file://0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch \
+ file://0003-PR-target-83013.patch \
+ file://0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch \
+ file://0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch \
+ file://0006-Add-MicroBlaze-to-target-supports-for-atomic-builtin.patch \
+ file://0007-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch \
+ file://0008-Allow-MicroBlaze-.weakext-pattern-in-testsuite.patch \
+ file://0009-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch \
+ file://0010-Fix-atomic-side-effects.patch \
+ file://0011-Fix-atomic-boolean-return-value.patch \
+ file://0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch \
+ file://0013-Add-MicroBlaze-ashrsi_3_with_size_opt.patch \
+ file://0014-Removed-MicroBlaze-moddi3-routinue.patch \
+ file://0015-MicroBlaze-fixed-missing-save-of-r18-in-fast_interru.patch \
+ file://0016-MicroBlaze-use-bralid-for-profiler-calls.patch \
+ file://0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch \
+ file://0018-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch \
+ file://0019-MicroBlaze-add-optimized-lshrsi3-When-barrel-shifter.patch \
+ file://0020-Modified-MicroBlaze-trap-instruction.patch \
+ file://0021-Reducing-Stack-space-for-arguments-Currently-in-Micr.patch \
+ file://0022-Inline-Expansion-of-fsqrt-builtin.patch \
+ file://0023-Update-MicroBlaze-ashlsi3-movsf-patterns.patch \
+ file://0024-8-stage-pipeline-for-microblaze.patch \
+ file://0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch \
+ file://0026-Fix-internal-compiler-error-with-msmall-divides.patch \
+ file://0027-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch \
+ file://0028-Add-new-bit-field-instructions.patch \
+ file://0029-Fix-bug-in-MB-version-calculation.patch \
+ file://0030-MicroBlaze-fixing-the-bug-in-the-bit-field-instructi.patch \
+ file://0031-Fixing-the-issue-with-MicroBlaze-builtin_alloc.patch \
+ file://0032-MicroBlaze-remove-bitfield-instructions-macros.patch \
+ file://0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch \
+ "
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0001-Patch-microblaze-Add-wdc.ext.clear-and-wdc.ext.flush.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0001-Patch-microblaze-Add-wdc.ext.clear-and-wdc.ext.flush.patch
new file mode 100644
index 0000000..3575cd7
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0001-Patch-microblaze-Add-wdc.ext.clear-and-wdc.ext.flush.patch
@@ -0,0 +1,69 @@
+From 8ab9a20c73acedbb636a41842a681872af8ae1d6 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Wed, 8 May 2013 11:03:36 +1000
+Subject: [PATCH 01/16] [Patch, microblaze]: Add wdc.ext.clear and
+ wdc.ext.flush insns
+
+Added two new instructions, wdc.ext.clear and wdc.ext.flush,
+to enable MicroBlaze to flush an external cache, which is
+used with the new coherency support for multiprocessing.
+
+Signed-off-by:nagaraju <nmekala@xilix.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ opcodes/microblaze-opc.h | 5 ++++-
+ opcodes/microblaze-opcm.h | 6 +++---
+ 2 files changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index e3cc1d9..f453097 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -91,6 +91,7 @@
+ #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
+ #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
+ #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
++#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
+
+ /* New Mask for msrset, msrclr insns. */
+@@ -101,7 +102,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+
+-#define MAX_OPCODES 289
++#define MAX_OPCODES 291
+
+ struct op_code_struct
+ {
+@@ -174,7 +175,9 @@ struct op_code_struct
+ {"wic", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
+ {"wdc", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
+ {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
++ {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
+ {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
++ {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
+ {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
+ {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
+ {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 6868389..8f5c1cb 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -31,9 +31,9 @@ enum microblaze_instr
+ idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
+ ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
+ andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+- wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
+- brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+- bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
++ wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar,
++ br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned,
++ blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+ imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+ brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+ bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0003-Patch-microblaze-Initial-port-of-microblaze-core-rea.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0003-Patch-microblaze-Initial-port-of-microblaze-core-rea.patch
new file mode 100644
index 0000000..5d85640
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0003-Patch-microblaze-Initial-port-of-microblaze-core-rea.patch
@@ -0,0 +1,384 @@
+From da27c7161c676550f5fe8a4e0f7f395e5e0d4770 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@petalogix.com>
+Date: Fri, 18 May 2012 11:49:50 +1000
+Subject: [PATCH 03/16] [Patch, microblaze]: Initial port of microblaze core
+ reading support
+
+Added support for reading notes in linux core dumps
+Support for reading of PRSTATUS and PSINFO information for rebuilding
+".reg" sections of core dumps at run time.
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
+Upstream-Status: Pending
+---
+ bfd/elf32-microblaze.c | 64 ++++++++++++++++++++++++++++++++
+ gdb/configure.tgt | 2 +-
+ gdb/microblaze-linux-tdep.c | 61 +++++++++++++++++++++++++++++++
+ gdb/microblaze-tdep.c | 89 +++++++++++++++++++++++++++++++++++++++++++++
+ gdb/microblaze-tdep.h | 28 ++++++++++++++
+ 5 files changed, 243 insertions(+), 1 deletion(-)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index 9837b18..cbd18f0 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -668,6 +668,67 @@ microblaze_elf_is_local_label_name (bfd *abfd, const char *name)
+ return _bfd_elf_is_local_label_name (abfd, name);
+ }
+
++/* Support for core dump NOTE sections. */
++static bfd_boolean
++microblaze_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
++{
++ int offset;
++ unsigned int size;
++
++ switch (note->descsz)
++ {
++ default:
++ return FALSE;
++
++ case 228: /* Linux/MicroBlaze */
++ /* pr_cursig */
++ elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
++
++ /* pr_pid */
++ elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24);
++
++ /* pr_reg */
++ offset = 72;
++ size = 50 * 4;
++
++ break;
++ }
++
++ /* Make a ".reg/999" section. */
++ return _bfd_elfcore_make_pseudosection (abfd, ".reg",
++ size, note->descpos + offset);
++}
++
++static bfd_boolean
++microblaze_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
++{
++ switch (note->descsz)
++ {
++ default:
++ return FALSE;
++
++ case 128: /* Linux/MicroBlaze elf_prpsinfo */
++ elf_tdata (abfd)->core->program
++ = _bfd_elfcore_strndup (abfd, note->descdata + 32, 16);
++ elf_tdata (abfd)->core->command
++ = _bfd_elfcore_strndup (abfd, note->descdata + 48, 80);
++ }
++
++ /* Note that for some reason, a spurious space is tacked
++ onto the end of the args in some (at least one anyway)
++ implementations, so strip it off if it exists. */
++
++ {
++ char *command = elf_tdata (abfd)->core->command;
++ int n = strlen (command);
++
++ if (0 < n && command[n - 1] == ' ')
++ command[n - 1] = '\0';
++ }
++
++ return TRUE;
++}
++
+ /* The microblaze linker (like many others) needs to keep track of
+ the number of relocs that it decides to copy as dynamic relocs in
+ check_relocs for each symbol. This is so that it can later discard
+@@ -3506,4 +3567,7 @@ microblaze_elf_add_symbol_hook (bfd *abfd,
+ #define elf_backend_size_dynamic_sections microblaze_elf_size_dynamic_sections
+ #define elf_backend_add_symbol_hook microblaze_elf_add_symbol_hook
+
++#define elf_backend_grok_prstatus microblaze_elf_grok_prstatus
++#define elf_backend_grok_psinfo microblaze_elf_grok_psinfo
++
+ #include "elf32-target.h"
+diff --git a/gdb/configure.tgt b/gdb/configure.tgt
+index 01311b2..9297c56 100644
+--- a/gdb/configure.tgt
++++ b/gdb/configure.tgt
+@@ -340,7 +340,7 @@ mep-*-*)
+
+ microblaze*-linux-*|microblaze*-*-linux*)
+ # Target: Xilinx MicroBlaze running Linux
+- gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o microblaze-rom.o \
++ gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o microblaze-rom.o glibc-tdep.o \
+ monitor.o dsrec.o solib-svr4.o symfile-mem.o linux-tdep.o"
+ gdb_sim=../sim/microblaze/libsim.a
+ ;;
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index 8d360eb..7e6b61b 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -32,6 +32,7 @@
+ #include "regset.h"
+ #include "solib-svr4.h"
+ #include "microblaze-tdep.h"
++#include "glibc-tdep.h"
+ #include "trad-frame.h"
+ #include "frame-unwind.h"
+ #include "tramp-frame.h"
+@@ -116,6 +117,43 @@ static struct tramp_frame microblaze_linux_sighandler_tramp_frame =
+ microblaze_linux_sighandler_cache_init
+ };
+
++const struct microblaze_gregset microblaze_linux_core_gregset;
++
++static void
++microblaze_linux_supply_core_gregset (const struct regset *regset,
++ struct regcache *regcache,
++ int regnum, const void *gregs, size_t len)
++{
++ microblaze_supply_gregset (µblaze_linux_core_gregset, regcache,
++ regnum, gregs);
++}
++
++static void
++microblaze_linux_collect_core_gregset (const struct regset *regset,
++ const struct regcache *regcache,
++ int regnum, void *gregs, size_t len)
++{
++ microblaze_collect_gregset (µblaze_linux_core_gregset, regcache,
++ regnum, gregs);
++}
++
++static void
++microblaze_linux_supply_core_fpregset (const struct regset *regset,
++ struct regcache *regcache,
++ int regnum, const void *fpregs, size_t len)
++{
++ /* FIXME. */
++ microblaze_supply_fpregset (regcache, regnum, fpregs);
++}
++
++static void
++microblaze_linux_collect_core_fpregset (const struct regset *regset,
++ const struct regcache *regcache,
++ int regnum, void *fpregs, size_t len)
++{
++ /* FIXME. */
++ microblaze_collect_fpregset (regcache, regnum, fpregs);
++}
+
+ static void
+ microblaze_linux_init_abi (struct gdbarch_info info,
+@@ -123,6 +161,10 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+ {
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
++ tdep->gregset = regset_alloc (gdbarch, microblaze_linux_supply_core_gregset,
++ microblaze_linux_collect_core_gregset);
++ tdep->sizeof_gregset = 200;
++
+ linux_init_abi (info, gdbarch);
+
+ set_gdbarch_memory_remove_breakpoint (gdbarch,
+@@ -135,6 +177,25 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+ /* Trampolines. */
+ tramp_frame_prepend_unwinder (gdbarch,
+ µblaze_linux_sighandler_tramp_frame);
++
++ /* BFD target for core files. */
++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++ else
++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++
++
++ /* Shared library handling. */
++ set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
++ set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
++
++ set_gdbarch_regset_from_core_section (gdbarch,
++ microblaze_regset_from_core_section);
++
++ /* Enable TLS support. */
++ set_gdbarch_fetch_tls_load_module_address (gdbarch,
++ svr4_fetch_objfile_link_map);
++
+ }
+
+ /* -Wmissing-prototypes */
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 14c1b52..36cf1ca 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -145,6 +145,14 @@ microblaze_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
+ return sp;
+ }
+
++static CORE_ADDR
++microblaze_store_arguments (struct regcache *regcache, int nargs,
++ struct value **args, CORE_ADDR sp,
++ int struct_return, CORE_ADDR struct_addr)
++{
++ error (_("store_arguments not implemented"));
++ return sp;
++}
+
+ static CORE_ADDR
+ microblaze_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
+@@ -536,6 +544,12 @@ microblaze_frame_base_address (struct frame_info *next_frame,
+ return cache->base;
+ }
+
++static const struct frame_unwind *
++microblaze_frame_sniffer (struct frame_info *next_frame)
++{
++ return µblaze_frame_unwind;
++}
++
+ static const struct frame_base microblaze_frame_base =
+ {
+ µblaze_frame_unwind,
+@@ -664,6 +678,70 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
+ return dwarf2_to_reg_map[reg];
+ }
+
++
++void
++microblaze_supply_gregset (const struct microblaze_gregset *gregset,
++ struct regcache *regcache,
++ int regnum, const void *gregs)
++{
++ unsigned int *regs = gregs;
++ if (regnum >= 0)
++ regcache_raw_supply (regcache, regnum, regs + regnum);
++
++ if (regnum == -1) {
++ int i;
++
++ for (i = 0; i < 50; i++) {
++ regcache_raw_supply (regcache, i, regs + i);
++ }
++ }
++}
++
++
++void
++microblaze_collect_gregset (const struct microblaze_gregset *gregset,
++ const struct regcache *regcache,
++ int regnum, void *gregs)
++{
++ /* FIXME. */
++}
++
++void
++microblaze_supply_fpregset (struct regcache *regcache,
++ int regnum, const void *fpregs)
++{
++ /* FIXME. */
++}
++
++void
++microblaze_collect_fpregset (const struct regcache *regcache,
++ int regnum, void *fpregs)
++{
++ /* FIXME. */
++}
++
++
++/* Return the appropriate register set for the core section identified
++ by SECT_NAME and SECT_SIZE. */
++
++const struct regset *
++microblaze_regset_from_core_section (struct gdbarch *gdbarch,
++ const char *sect_name, size_t sect_size)
++{
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++
++ microblaze_debug ("microblaze_regset_from_core_section, sect_name = %s\n", sect_name);
++
++ if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset)
++ return tdep->gregset;
++
++ if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset)
++ return tdep->fpregset;
++
++ microblaze_debug ("microblaze_regset_from_core_section returning null :-( \n");
++ return NULL;
++}
++
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ {
+@@ -679,6 +757,11 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ tdep = XNEW (struct gdbarch_tdep);
+ gdbarch = gdbarch_alloc (&info, tdep);
+
++ tdep->gregset = NULL;
++ tdep->sizeof_gregset = 0;
++ tdep->fpregset = NULL;
++ tdep->sizeof_fpregset = 0;
++
+ set_gdbarch_long_double_bit (gdbarch, 128);
+
+ set_gdbarch_num_regs (gdbarch, MICROBLAZE_NUM_REGS);
+@@ -726,6 +809,12 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ frame_unwind_append_unwinder (gdbarch, µblaze_frame_unwind);
+ frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
+
++ /* If we have register sets, enable the generic core file support. */
++ if (tdep->gregset) {
++ set_gdbarch_regset_from_core_section (gdbarch,
++ microblaze_regset_from_core_section);
++ }
++
+ return gdbarch;
+ }
+
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index a532092..fec24b9 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -22,8 +22,22 @@
+
+
+ /* Microblaze architecture-specific information. */
++struct microblaze_gregset
++{
++ unsigned int gregs[32];
++ unsigned int fpregs[32];
++ unsigned int pregs[16];
++};
++
+ struct gdbarch_tdep
+ {
++ int dummy; // declare something.
++
++ /* Register sets. */
++ struct regset *gregset;
++ size_t sizeof_gregset;
++ struct regset *fpregset;
++ size_t sizeof_fpregset;
+ };
+
+ struct microblaze_frame_cache
+@@ -117,4 +131,18 @@ enum microblaze_regnum
+ Only used for native debugging. */
+ #define MICROBLAZE_BREAKPOINT {0xb9, 0xcc, 0x00, 0x60}
+
++extern void microblaze_supply_gregset (const struct microblaze_gregset *gregset,
++ struct regcache *regcache,
++ int regnum, const void *gregs);
++extern void microblaze_collect_gregset (const struct microblaze_gregset *gregset,
++ const struct regcache *regcache,
++ int regnum, void *gregs);
++extern void microblaze_supply_fpregset (struct regcache *regcache,
++ int regnum, const void *fpregs);
++extern void microblaze_collect_fpregset (const struct regcache *regcache,
++ int regnum, void *fpregs);
++
++extern const struct regset * microblaze_regset_from_core_section (struct gdbarch *gdbarch,
++ const char *sect_name, size_t sect_size);
++
+ #endif /* microblaze-tdep.h */
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0004-Patch-microblaze-Communicate-in-larger-blocks-with-t.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0004-Patch-microblaze-Communicate-in-larger-blocks-with-t.patch
new file mode 100644
index 0000000..b14e409
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0004-Patch-microblaze-Communicate-in-larger-blocks-with-t.patch
@@ -0,0 +1,67 @@
+From 26e124f0d78233b1d976bd4b787f6a7866bcb7e7 Mon Sep 17 00:00:00 2001
+From: nagaraju <nmekala@xilix.com>
+Date: Wed, 4 Jan 2012 16:59:33 +0530
+Subject: [PATCH 04/16] [Patch, microblaze]: Communicate in larger blocks with
+ the target
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Upstream-Status: Pending
+---
+ gdb/microblaze-tdep.c | 25 ++++++++++++++++++++++---
+ 1 file changed, 22 insertions(+), 3 deletions(-)
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 36cf1ca..76e87b3 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -242,6 +242,10 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+ int flags = 0;
+ int save_hidden_pointer_found = 0;
+ int non_stack_instruction_found = 0;
++ int n_insns;
++ unsigned long *insn_block;
++ gdb_byte *buf_block;
++ int ti, tj;
+
+ /* Find the start of this function. */
+ find_pc_partial_function (pc, &name, &func_addr, &func_end);
+@@ -281,9 +285,23 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+ name, paddress (gdbarch, func_addr),
+ paddress (gdbarch, stop));
+
++/* Do a block read to minimize the transaction with the Debug Agent */
++ n_insns = (stop == func_addr) ? 1 : ((stop - func_addr) / INST_WORD_SIZE);
++ insn_block = (unsigned long *)calloc(n_insns, sizeof(unsigned long));
++ buf_block = (gdb_byte *)calloc(n_insns * INST_WORD_SIZE, sizeof(gdb_byte));
++
++ target_read_memory (func_addr, buf_block, n_insns * INST_WORD_SIZE );
++
++ for(ti = 0; ti < n_insns; ti++){
++ insn_block[ti] = 0;
++ for( tj = ti * INST_WORD_SIZE; tj < (ti + 1) * INST_WORD_SIZE; tj++ )
++ insn_block[ti] = (insn_block[ti] << 8) | buf_block[tj];
++ }
++
+ for (addr = func_addr; addr < stop; addr += INST_WORD_SIZE)
+ {
+- insn = microblaze_fetch_instruction (addr);
++ //insn = microblaze_fetch_instruction (addr);
++ insn = insn_block[(addr - func_addr) / INST_WORD_SIZE];
+ op = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
+ microblaze_debug ("%s %08lx\n", paddress (gdbarch, pc), insn);
+
+@@ -409,8 +427,9 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+ part of the prologue. */
+ if (save_hidden_pointer_found)
+ prologue_end_addr -= INST_WORD_SIZE;
+-
+- return prologue_end_addr;
++ free(insn_block);
++ free(buf_block);
++ return prologue_end_addr;
+ }
+
+ static CORE_ADDR
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0005-Patch-microblaze-Add-mb-singlestepping.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0005-Patch-microblaze-Add-mb-singlestepping.patch
new file mode 100644
index 0000000..e490f02
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0005-Patch-microblaze-Add-mb-singlestepping.patch
@@ -0,0 +1,200 @@
+From 5c3a08f407e1cbee5b0a4ca6092165b97acddda5 Mon Sep 17 00:00:00 2001
+From: "Edgar E. Iglesias" <edgar@axis.com>
+Date: Fri, 24 Feb 2012 11:52:30 +0100
+Subject: [PATCH 05/16] [Patch, microblaze]: Add mb singlestepping.
+
+Fix prologue analysis for little-endian.
+Always provide a frame base.
+
+Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
+Upstream-Status: Pending
+---
+ gdb/microblaze-tdep.c | 123 ++++++++++++++++++++++++++++++++++++++++++++------
+ 1 file changed, 108 insertions(+), 15 deletions(-)
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 76e87b3..50b68d2 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -243,9 +243,7 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+ int save_hidden_pointer_found = 0;
+ int non_stack_instruction_found = 0;
+ int n_insns;
+- unsigned long *insn_block;
+- gdb_byte *buf_block;
+- int ti, tj;
++ unsigned int *insn_block;
+
+ /* Find the start of this function. */
+ find_pc_partial_function (pc, &name, &func_addr, &func_end);
+@@ -287,23 +285,16 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+
+ /* Do a block read to minimize the transaction with the Debug Agent */
+ n_insns = (stop == func_addr) ? 1 : ((stop - func_addr) / INST_WORD_SIZE);
+- insn_block = (unsigned long *)calloc(n_insns, sizeof(unsigned long));
+- buf_block = (gdb_byte *)calloc(n_insns * INST_WORD_SIZE, sizeof(gdb_byte));
++ insn_block = calloc(n_insns, sizeof(unsigned long));
+
+- target_read_memory (func_addr, buf_block, n_insns * INST_WORD_SIZE );
+-
+- for(ti = 0; ti < n_insns; ti++){
+- insn_block[ti] = 0;
+- for( tj = ti * INST_WORD_SIZE; tj < (ti + 1) * INST_WORD_SIZE; tj++ )
+- insn_block[ti] = (insn_block[ti] << 8) | buf_block[tj];
+- }
++ target_read_memory (func_addr, (void*) insn_block, n_insns * INST_WORD_SIZE );
+
+ for (addr = func_addr; addr < stop; addr += INST_WORD_SIZE)
+ {
+ //insn = microblaze_fetch_instruction (addr);
+ insn = insn_block[(addr - func_addr) / INST_WORD_SIZE];
+ op = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
+- microblaze_debug ("%s %08lx\n", paddress (gdbarch, pc), insn);
++ microblaze_debug ("%s %08lx op=%x r%d r%d imm=%d\n", paddress (gdbarch, addr), insn, op, rd, ra, imm);
+
+ /* This code is very sensitive to what functions are present in the
+ prologue. It assumes that the (addi, addik, swi, sw) can be the
+@@ -428,7 +419,6 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+ if (save_hidden_pointer_found)
+ prologue_end_addr -= INST_WORD_SIZE;
+ free(insn_block);
+- free(buf_block);
+ return prologue_end_addr;
+ }
+
+@@ -502,6 +492,7 @@ microblaze_frame_cache (struct frame_info *next_frame, void **this_cache)
+
+ func = get_frame_func (next_frame);
+
++ cache->base = get_frame_register_unsigned (next_frame, gdbarch_sp_regnum (gdbarch));
+ cache->pc = get_frame_address_in_block (next_frame);
+
+ return cache;
+@@ -518,7 +509,7 @@ microblaze_frame_this_id (struct frame_info *next_frame, void **this_cache,
+ if (cache->base == 0)
+ return;
+
+- (*this_id) = frame_id_build (cache->base, cache->pc);
++ (*this_id) = frame_id_build (cache->base, get_frame_pc (next_frame));
+ }
+
+ static struct value *
+@@ -661,6 +652,107 @@ microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
+ return (TYPE_LENGTH (type) == 16);
+ }
+
++int
++microblaze_software_single_step (struct frame_info *frame)
++{
++ struct gdbarch *arch = get_frame_arch (frame);
++ struct address_space *aspace = get_frame_address_space (frame);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
++ static char le_breakp[] = MICROBLAZE_BREAKPOINT_LE;
++ static char be_breakp[] = MICROBLAZE_BREAKPOINT;
++ enum bfd_endian byte_order = gdbarch_byte_order (arch);
++ char *breakp = byte_order == BFD_ENDIAN_BIG ? be_breakp : le_breakp;
++ int ret = 0;
++
++ /* Save the address and the values of the next_pc and the target */
++ static struct sstep_breaks
++ {
++ CORE_ADDR address;
++ bfd_boolean valid;
++ /* Shadow contents. */
++ char data[INST_WORD_SIZE];
++ } stepbreaks[2];
++ int ii;
++
++ if (1)
++ {
++ CORE_ADDR pc;
++ long insn;
++ enum microblaze_instr minstr;
++ bfd_boolean isunsignednum;
++ enum microblaze_instr_type insn_type;
++ short delay_slots;
++ int imm;
++ bfd_boolean immfound = FALSE;
++
++ /* Set a breakpoint at the next instruction */
++ /* If the current instruction is an imm, set it at the inst after */
++ /* If the instruction has a delay slot, skip the delay slot */
++ pc = get_frame_pc (frame);
++ insn = microblaze_fetch_instruction (pc);
++ minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots);
++ if (insn_type == immediate_inst)
++ {
++ int rd, ra, rb;
++ immfound = TRUE;
++ minstr = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
++ pc = pc + INST_WORD_SIZE;
++ insn = microblaze_fetch_instruction (pc);
++ minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots);
++ }
++ stepbreaks[0].address = pc + (delay_slots * INST_WORD_SIZE) + INST_WORD_SIZE;
++ if (insn_type != return_inst) {
++ stepbreaks[0].valid = TRUE;
++ } else {
++ stepbreaks[0].valid = FALSE;
++ }
++
++ microblaze_debug ("single-step insn_type=%x insn=%x\n", insn_type, insn);
++ /* Now check for branch or return instructions */
++ if (insn_type == branch_inst || insn_type == return_inst) {
++ int limm;
++ int lrd, lra, lrb;
++ int ra, rb;
++ bfd_boolean targetvalid;
++ bfd_boolean unconditionalbranch;
++ microblaze_decode_insn(insn, &lrd, &lra, &lrb, &limm);
++ if (lra >= 0 && lra < MICROBLAZE_NUM_REGS)
++ ra = get_frame_register_unsigned (frame, lra);
++ else
++ ra = 0;
++ if (lrb >= 0 && lrb < MICROBLAZE_NUM_REGS)
++ rb = get_frame_register_unsigned (frame, lrb);
++ else
++ rb = 0;
++ stepbreaks[1].address = microblaze_get_target_address (insn, immfound, imm, pc, ra, rb, &targetvalid, &unconditionalbranch);
++ microblaze_debug ("single-step uncondbr=%d targetvalid=%d target=%x\n", unconditionalbranch, targetvalid, stepbreaks[1].address);
++ if (unconditionalbranch)
++ stepbreaks[0].valid = FALSE; /* This is a unconditional branch: will not come to the next address */
++ if (targetvalid && (stepbreaks[0].valid == FALSE ||
++ (stepbreaks[0].address != stepbreaks[1].address))
++ && (stepbreaks[1].address != pc)) {
++ stepbreaks[1].valid = TRUE;
++ } else {
++ stepbreaks[1].valid = FALSE;
++ }
++ } else {
++ stepbreaks[1].valid = FALSE;
++ }
++
++ /* Insert the breakpoints */
++ for (ii = 0; ii < 2; ++ii)
++ {
++
++ /* ignore invalid breakpoint. */
++ if (stepbreaks[ii].valid) {
++ insert_single_step_breakpoint (arch, aspace, stepbreaks[ii].address);
++ ret = 1;
++ }
++ }
++ }
++ return ret;
++}
++
+ static void
+ microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc)
+ {
+@@ -809,6 +901,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
+
+ set_gdbarch_breakpoint_from_pc (gdbarch, microblaze_breakpoint_from_pc);
++ set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
+
+ set_gdbarch_frame_args_skip (gdbarch, 8);
+
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0006-Patch-microblaze-Add-initial-port-of-linux-gdbserver.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0006-Patch-microblaze-Add-initial-port-of-linux-gdbserver.patch
new file mode 100644
index 0000000..cb2eec1
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0006-Patch-microblaze-Add-initial-port-of-linux-gdbserver.patch
@@ -0,0 +1,553 @@
+From 2112c9ded01ddd08f0e31e5ce23eecac6c04e8c4 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@petalogix.com>
+Date: Mon, 6 Feb 2012 10:28:29 +1000
+Subject: [PATCH 06/16] [Patch, microblaze]: Add initial port of linux
+ gdbserver
+
+add gdb_proc_service_h to gdbserver microblaze-linux
+
+gdbserver needs to initialise the microblaze registers
+
+other archs use this step to run a *_arch_setup() to carry out all
+architecture specific setup - may need to add in future
+
+ * add linux-ptrace.o to gdbserver configure
+ * gdb/configure.tgt: Set build_gdbserver=yes
+ * Update breakpoint opcode
+ * fix segfault on connecting gdbserver
+ * add microblaze_linux_memory_remove_breakpoint
+ * add set_solib_svr4_fetch_link_map_offsets
+ * add set_gdbarch_fetch_tls_load_module_address
+ * Force reading of r0 as 0, prevent stores
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+Upstream-Status: Pending
+---
+ gdb/configure.host | 3 +
+ gdb/configure.tgt | 1 +
+ gdb/gdbserver/Makefile.in | 4 +
+ gdb/gdbserver/configure.srv | 6 +
+ gdb/gdbserver/linux-microblaze-low.c | 228 +++++++++++++++++++++++++++++++++++
+ gdb/microblaze-linux-tdep.c | 25 +++-
+ gdb/microblaze-tdep.c | 45 ++++++-
+ gdb/microblaze-tdep.h | 3 +-
+ gdb/regformats/reg-microblaze.dat | 39 ++++++
+ 9 files changed, 348 insertions(+), 6 deletions(-)
+ create mode 100644 gdb/gdbserver/linux-microblaze-low.c
+ create mode 100644 gdb/regformats/reg-microblaze.dat
+
+diff --git a/gdb/configure.host b/gdb/configure.host
+index 15a8288..76cc5fe 100644
+--- a/gdb/configure.host
++++ b/gdb/configure.host
+@@ -59,6 +59,7 @@ i[34567]86*) gdb_host_cpu=i386 ;;
+ m68*) gdb_host_cpu=m68k ;;
+ m88*) gdb_host_cpu=m88k ;;
+ mips*) gdb_host_cpu=mips ;;
++microblaze*) gdb_host_cpu=microblaze ;;
+ powerpc* | rs6000) gdb_host_cpu=powerpc ;;
+ sparcv9 | sparc64) gdb_host_cpu=sparc ;;
+ s390*) gdb_host_cpu=s390 ;;
+@@ -133,6 +134,8 @@ mips*-*-netbsd* | mips*-*-knetbsd*-gnu)
+ gdb_host=nbsd ;;
+ mips64*-*-openbsd*) gdb_host=obsd64 ;;
+
++microblaze*-*linux*) gdb_host=linux ;;
++
+ powerpc-*-aix* | rs6000-*-* | powerpc64-*-aix*)
+ gdb_host=aix ;;
+ powerpc*-*-freebsd*) gdb_host=fbsd ;;
+diff --git a/gdb/configure.tgt b/gdb/configure.tgt
+index 9297c56..3a7951a 100644
+--- a/gdb/configure.tgt
++++ b/gdb/configure.tgt
+@@ -343,6 +343,7 @@ microblaze*-linux-*|microblaze*-*-linux*)
+ gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o microblaze-rom.o glibc-tdep.o \
+ monitor.o dsrec.o solib-svr4.o symfile-mem.o linux-tdep.o"
+ gdb_sim=../sim/microblaze/libsim.a
++ build_gdbserver=yes
+ ;;
+ microblaze*-*-*)
+ # Target: Xilinx MicroBlaze running standalone
+diff --git a/gdb/gdbserver/Makefile.in b/gdb/gdbserver/Makefile.in
+index f773fa2..a11ace1 100644
+--- a/gdb/gdbserver/Makefile.in
++++ b/gdb/gdbserver/Makefile.in
+@@ -148,6 +148,7 @@ SFILES= $(srcdir)/gdbreplay.c $(srcdir)/inferiors.c $(srcdir)/dll.c \
+ $(srcdir)/linux-ia64-low.c $(srcdir)/linux-low.c \
+ $(srcdir)/linux-m32r-low.c \
+ $(srcdir)/linux-m68k-low.c $(srcdir)/linux-mips-low.c \
++ $(srcdir)/linux-microblaze-low.c \
+ $(srcdir)/linux-nios2-low.c \
+ $(srcdir)/linux-ppc-low.c \
+ $(srcdir)/linux-s390-low.c \
+@@ -329,6 +330,7 @@ clean:
+ rm -f arm-with-iwmmxt.c
+ rm -f arm-with-vfpv2.c arm-with-vfpv3.c arm-with-neon.c
+ rm -f mips-linux.c mips64-linux.c
++ rm -f microblaze-linux.c
+ rm -f nios2-linux.c
+ rm -f powerpc-32.c powerpc-32l.c powerpc-64l.c powerpc-e500l.c
+ rm -f powerpc-altivec32l.c powerpc-cell32l.c powerpc-vsx32l.c
+@@ -612,6 +614,8 @@ reg-m68k.c : $(srcdir)/../regformats/reg-m68k.dat $(regdat_sh)
+ $(SHELL) $(regdat_sh) $(srcdir)/../regformats/reg-m68k.dat reg-m68k.c
+ reg-cf.c : $(srcdir)/../regformats/reg-cf.dat $(regdat_sh)
+ $(SHELL) $(regdat_sh) $(srcdir)/../regformats/reg-cf.dat reg-cf.c
++microblaze-linux.c : $(srcdir)/../regformats/reg-microblaze.dat $(regdat_sh)
++ $(SHELL) $(regdat_sh) $(srcdir)/../regformats/reg-microblaze.dat microblaze-linux.c
+ mips-linux.c : $(srcdir)/../regformats/mips-linux.dat $(regdat_sh)
+ $(SHELL) $(regdat_sh) $(srcdir)/../regformats/mips-linux.dat mips-linux.c
+ mips-dsp-linux.c : $(srcdir)/../regformats/mips-dsp-linux.dat $(regdat_sh)
+diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
+index cc4f53d..359c756 100644
+--- a/gdb/gdbserver/configure.srv
++++ b/gdb/gdbserver/configure.srv
+@@ -198,6 +198,12 @@ case "${target}" in
+ srv_linux_usrregs=yes
+ srv_linux_thread_db=yes
+ ;;
++ microblaze*-*-linux*) srv_regobj=microblaze-linux.o
++ srv_tgtobj="$srv_linux_obj linux-microblaze-low.o"
++ srv_linux_usrregs=yes
++ srv_linux_regsets=yes
++ srv_linux_thread_db=yes
++ ;;
+ nios2*-*-linux*) srv_regobj="nios2-linux.o"
+ srv_tgtobj="$srv_linux_obj linux-nios2-low.o"
+ srv_xmlfiles="nios2-linux.xml"
+diff --git a/gdb/gdbserver/linux-microblaze-low.c b/gdb/gdbserver/linux-microblaze-low.c
+new file mode 100644
+index 0000000..279df9f
+--- /dev/null
++++ b/gdb/gdbserver/linux-microblaze-low.c
+@@ -0,0 +1,228 @@
++/* GNU/Linux/Microblaze specific low level interface, for the remote server for
++ GDB.
++ Copyright (C) 1995-2013 Free Software Foundation, Inc.
++
++ This file is part of GDB.
++
++ This program is free software; you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 3 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program. If not, see <http://www.gnu.org/licenses/>. */
++
++#include "server.h"
++#include "linux-low.h"
++
++#include <asm/ptrace.h>
++#include <sys/procfs.h>
++#include <sys/ptrace.h>
++
++#include "gdb_proc_service.h"
++
++static int microblaze_regmap[] =
++ {PT_GPR(0), PT_GPR(1), PT_GPR(2), PT_GPR(3),
++ PT_GPR(4), PT_GPR(5), PT_GPR(6), PT_GPR(7),
++ PT_GPR(8), PT_GPR(9), PT_GPR(10), PT_GPR(11),
++ PT_GPR(12), PT_GPR(13), PT_GPR(14), PT_GPR(15),
++ PT_GPR(16), PT_GPR(17), PT_GPR(18), PT_GPR(19),
++ PT_GPR(20), PT_GPR(21), PT_GPR(22), PT_GPR(23),
++ PT_GPR(24), PT_GPR(25), PT_GPR(26), PT_GPR(27),
++ PT_GPR(28), PT_GPR(29), PT_GPR(30), PT_GPR(31),
++ PT_PC, PT_MSR, PT_EAR, PT_ESR,
++ PT_FSR
++ };
++
++#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0])
++
++/* Defined in auto-generated file microblaze-linux.c. */
++void init_registers_microblaze (void);
++extern const struct target_desc *tdesc_microblaze;
++
++static int
++microblaze_cannot_store_register (int regno)
++{
++ if (microblaze_regmap[regno] == -1 || regno == 0)
++ return 1;
++
++ return 0;
++}
++
++static int
++microblaze_cannot_fetch_register (int regno)
++{
++ return 0;
++}
++
++static CORE_ADDR
++microblaze_get_pc (struct regcache *regcache)
++{
++ unsigned long pc;
++
++ collect_register_by_name (regcache, "pc", &pc);
++ return (CORE_ADDR) pc;
++}
++
++static void
++microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc)
++{
++ unsigned long newpc = pc;
++
++ supply_register_by_name (regcache, "pc", &newpc);
++}
++
++/* dbtrap insn */
++/* brki r16, 0x18; */
++static const unsigned long microblaze_breakpoint = 0xba0c0018;
++#define microblaze_breakpoint_len 4
++
++static int
++microblaze_breakpoint_at (CORE_ADDR where)
++{
++ unsigned long insn;
++
++ (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
++ if (insn == microblaze_breakpoint)
++ return 1;
++ /* If necessary, recognize more trap instructions here. GDB only uses the
++ one. */
++ return 0;
++}
++
++static CORE_ADDR
++microblaze_reinsert_addr (struct regcache *regcache)
++{
++ unsigned long pc;
++ collect_register_by_name (regcache, "r15", &pc);
++ return pc;
++}
++
++#ifdef HAVE_PTRACE_GETREGS
++
++static void
++microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
++{
++ int size = register_size (regcache->tdesc, regno);
++
++ memset (buf, 0, sizeof (long));
++
++ if (size < sizeof (long))
++ collect_register (regcache, regno, buf + sizeof (long) - size);
++ else
++ collect_register (regcache, regno, buf);
++}
++
++static void
++microblaze_supply_ptrace_register (struct regcache *regcache,
++ int regno, const char *buf)
++{
++ int size = register_size (regcache->tdesc, regno);
++
++ if (regno == 0) {
++ unsigned long regbuf_0 = 0;
++ /* clobbering r0 so that it is always 0 as enforced by hardware */
++ supply_register (regcache, regno, (const char*)®buf_0);
++ } else {
++ if (size < sizeof (long))
++ supply_register (regcache, regno, buf + sizeof (long) - size);
++ else
++ supply_register (regcache, regno, buf);
++ }
++}
++
++/* Provide only a fill function for the general register set. ps_lgetregs
++ will use this for NPTL support. */
++
++static void microblaze_fill_gregset (struct regcache *regcache, void *buf)
++{
++ int i;
++
++ for (i = 0; i < 32; i++)
++ microblaze_collect_ptrace_register (regcache, i, (char *) buf + microblaze_regmap[i]);
++}
++
++static void
++microblaze_store_gregset (struct regcache *regcache, const void *buf)
++{
++ int i;
++
++ for (i = 0; i < 32; i++)
++ supply_register (regcache, i, (char *) buf + microblaze_regmap[i]);
++}
++
++#endif /* HAVE_PTRACE_GETREGS */
++
++static struct regset_info microblaze_regsets[] = {
++#ifdef HAVE_PTRACE_GETREGS
++ { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset },
++ { 0, 0, 0, -1, -1, NULL, NULL },
++#endif /* HAVE_PTRACE_GETREGS */
++ { 0, 0, 0, -1, -1, NULL, NULL }
++};
++
++static struct regsets_info microblaze_regsets_info =
++ {
++ microblaze_regsets, /* regsets */
++ 0, /* num_regsets */
++ NULL, /* disabled_regsets */
++ };
++
++static struct usrregs_info microblaze_usrregs_info =
++ {
++ microblaze_num_regs,
++ microblaze_regmap,
++ };
++
++static struct regs_info regs_info =
++ {
++ NULL, /* regset_bitmap */
++ µblaze_usrregs_info,
++ µblaze_regsets_info
++ };
++
++static const struct regs_info *
++microblaze_regs_info (void)
++{
++ return ®s_info;
++}
++
++static void
++microblaze_arch_setup (void)
++{
++ current_process ()->tdesc = tdesc_microblaze;
++}
++
++struct linux_target_ops the_low_target = {
++ microblaze_arch_setup,
++ microblaze_regs_info,
++ microblaze_cannot_fetch_register,
++ microblaze_cannot_store_register,
++ NULL, /* fetch_register */
++ microblaze_get_pc,
++ microblaze_set_pc,
++ (const unsigned char *) µblaze_breakpoint,
++ microblaze_breakpoint_len,
++ microblaze_reinsert_addr,
++ 0,
++ microblaze_breakpoint_at,
++ NULL,
++ NULL,
++ NULL,
++ NULL,
++ microblaze_collect_ptrace_register,
++ microblaze_supply_ptrace_register,
++};
++
++void
++initialize_low_arch (void)
++{
++ init_registers_microblaze ();
++
++ initialize_regsets_info (µblaze_regsets_info);
++}
+\ No newline at end of file
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index 7e6b61b..cf58e21 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -38,6 +38,22 @@
+ #include "tramp-frame.h"
+ #include "linux-tdep.h"
+
++static int microblaze_debug_flag = 0;
++
++static void
++microblaze_debug (const char *fmt, ...)
++{
++ if (microblaze_debug_flag)
++ {
++ va_list args;
++
++ va_start (args, fmt);
++ printf_unfiltered ("MICROBLAZE LINUX: ");
++ vprintf_unfiltered (fmt, args);
++ va_end (args);
++ }
++}
++
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ struct bp_target_info *bp_tgt)
+@@ -47,20 +63,27 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ int val;
+ int bplen;
+ gdb_byte old_contents[BREAKPOINT_MAX];
++ struct cleanup *cleanup;
+
+ /* Determine appropriate breakpoint contents and size for this address. */
+ bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
+ if (bp == NULL)
+ error (_("Software breakpoints not implemented for this target."));
+
++ /* Make sure we see the memory breakpoints. */
++ cleanup = make_show_memory_breakpoints_cleanup (1);
+ val = target_read_memory (addr, old_contents, bplen);
+
+ /* If our breakpoint is no longer at the address, this means that the
+ program modified the code on us, so it is wrong to put back the
+ old value. */
+ if (val == 0 && memcmp (bp, old_contents, bplen) == 0)
+- val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++ {
++ val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++ microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr);
++ }
+
++ do_cleanups (cleanup);
+ return val;
+ }
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 50b68d2..1c6dbfe 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -164,6 +164,39 @@ microblaze_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
+ return sp;
+ }
+
++static int
++microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
++ struct bp_target_info *bp_tgt)
++{
++ CORE_ADDR addr = bp_tgt->placed_address;
++ const unsigned char *bp;
++ int val;
++ int bplen;
++ gdb_byte old_contents[BREAKPOINT_MAX];
++ struct cleanup *cleanup;
++
++ /* Determine appropriate breakpoint contents and size for this address. */
++ bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
++ if (bp == NULL)
++ error (_("Software breakpoints not implemented for this target."));
++
++ /* Make sure we see the memory breakpoints. */
++ cleanup = make_show_memory_breakpoints_cleanup (1);
++ val = target_read_memory (addr, old_contents, bplen);
++
++ /* If our breakpoint is no longer at the address, this means that the
++ program modified the code on us, so it is wrong to put back the
++ old value. */
++ if (val == 0 && memcmp (bp, old_contents, bplen) == 0)
++ {
++ val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++ microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr);
++ }
++
++ do_cleanups (cleanup);
++ return val;
++}
++
+ static const gdb_byte *
+ microblaze_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc,
+ int *len)
+@@ -291,8 +324,8 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+
+ for (addr = func_addr; addr < stop; addr += INST_WORD_SIZE)
+ {
+- //insn = microblaze_fetch_instruction (addr);
+- insn = insn_block[(addr - func_addr) / INST_WORD_SIZE];
++ insn = microblaze_fetch_instruction (addr);
++ //insn = insn_block[(addr - func_addr) / INST_WORD_SIZE];
+ op = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
+ microblaze_debug ("%s %08lx op=%x r%d r%d imm=%d\n", paddress (gdbarch, addr), insn, op, rd, ra, imm);
+
+@@ -724,13 +757,15 @@ microblaze_software_single_step (struct frame_info *frame)
+ rb = get_frame_register_unsigned (frame, lrb);
+ else
+ rb = 0;
++
+ stepbreaks[1].address = microblaze_get_target_address (insn, immfound, imm, pc, ra, rb, &targetvalid, &unconditionalbranch);
+- microblaze_debug ("single-step uncondbr=%d targetvalid=%d target=%x\n", unconditionalbranch, targetvalid, stepbreaks[1].address);
++ microblaze_debug ("single-step uncondbr=%d targetvalid=%d target=%x\n", unconditionalbranch, targetvalid, stepbreaks[1].address);
++
+ if (unconditionalbranch)
+ stepbreaks[0].valid = FALSE; /* This is a unconditional branch: will not come to the next address */
+ if (targetvalid && (stepbreaks[0].valid == FALSE ||
+ (stepbreaks[0].address != stepbreaks[1].address))
+- && (stepbreaks[1].address != pc)) {
++ && (stepbreaks[1].address != pc)) {
+ stepbreaks[1].valid = TRUE;
+ } else {
+ stepbreaks[1].valid = FALSE;
+@@ -900,6 +935,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ /* Stack grows downward. */
+ set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
+
++ set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
++
+ set_gdbarch_breakpoint_from_pc (gdbarch, microblaze_breakpoint_from_pc);
+ set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
+
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index fec24b9..98aa0f5 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -129,7 +129,8 @@ enum microblaze_regnum
+
+ /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used.
+ Only used for native debugging. */
+-#define MICROBLAZE_BREAKPOINT {0xb9, 0xcc, 0x00, 0x60}
++#define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18}
++#define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba}
+
+ extern void microblaze_supply_gregset (const struct microblaze_gregset *gregset,
+ struct regcache *regcache,
+diff --git a/gdb/regformats/reg-microblaze.dat b/gdb/regformats/reg-microblaze.dat
+new file mode 100644
+index 0000000..a5dd0a0
+--- /dev/null
++++ b/gdb/regformats/reg-microblaze.dat
+@@ -0,0 +1,39 @@
++name:microblaze
++expedite:r1,pc
++32:r0
++32:r1
++32:r2
++32:r3
++32:r4
++32:r5
++32:r6
++32:r7
++32:r8
++32:r9
++32:r10
++32:r11
++32:r12
++32:r13
++32:r14
++32:r15
++32:r16
++32:r17
++32:r18
++32:r19
++32:r20
++32:r21
++32:r22
++32:r23
++32:r24
++32:r25
++32:r26
++32:r27
++32:r28
++32:r29
++32:r30
++32:r31
++32:pc
++32:msr
++32:ear
++32:esr
++32:fsr
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0007-Patch-microblaze-Add-slr-and-shr-regs-and-little-end.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0007-Patch-microblaze-Add-slr-and-shr-regs-and-little-end.patch
new file mode 100644
index 0000000..7cd1190
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0007-Patch-microblaze-Add-slr-and-shr-regs-and-little-end.patch
@@ -0,0 +1,82 @@
+From fb2af2fffb673dbb14d743c8da94c4a83b71c792 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Mon, 26 Nov 2012 17:39:17 +1000
+Subject: [PATCH 07/16] [Patch, microblaze]: Add slr and shr regs and
+ little-endian breakpoint
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ gdb/microblaze-tdep.c | 10 ++++++++--
+ gdb/microblaze-tdep.h | 6 ++++--
+ gdb/regformats/reg-microblaze.dat | 2 ++
+ 3 files changed, 14 insertions(+), 4 deletions(-)
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 1c6dbfe..0ce4947 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -73,7 +73,8 @@ static const char *microblaze_register_names[] =
+ "rpc", "rmsr", "rear", "resr", "rfsr", "rbtr",
+ "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6",
+ "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11",
+- "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi"
++ "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi",
++ "rslr", "rshr"
+ };
+
+ #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names)
+@@ -201,10 +202,15 @@ static const gdb_byte *
+ microblaze_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc,
+ int *len)
+ {
++ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ static gdb_byte break_insn[] = MICROBLAZE_BREAKPOINT;
++ static gdb_byte break_insn_le[] = MICROBLAZE_BREAKPOINT_LE;
+
+ *len = sizeof (break_insn);
+- return break_insn;
++ if (byte_order == BFD_ENDIAN_BIG)
++ return break_insn;
++ else
++ return break_insn_le;
+ }
+
+ /* Allocate and initialize a frame cache. */
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index 98aa0f5..cd32e9f 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -56,7 +56,7 @@ struct microblaze_frame_cache
+ int fp_regnum;
+
+ /* Offsets to saved registers. */
+- int register_offsets[57]; /* Must match MICROBLAZE_NUM_REGS. */
++ int register_offsets[59]; /* Must match MICROBLAZE_NUM_REGS. */
+
+ /* Table of saved registers. */
+ struct trad_frame_saved_reg *saved_regs;
+@@ -121,7 +121,9 @@ enum microblaze_regnum
+ MICROBLAZE_RTLBX_REGNUM,
+ MICROBLAZE_RTLBSX_REGNUM,
+ MICROBLAZE_RTLBLO_REGNUM,
+- MICROBLAZE_RTLBHI_REGNUM
++ MICROBLAZE_RTLBHI_REGNUM,
++ MICROBLAZE_SLR_REGNUM,
++ MICROBLAZE_SHR_REGNUM
+ };
+
+ /* All registers are 32 bits. */
+diff --git a/gdb/regformats/reg-microblaze.dat b/gdb/regformats/reg-microblaze.dat
+index a5dd0a0..bd8a438 100644
+--- a/gdb/regformats/reg-microblaze.dat
++++ b/gdb/regformats/reg-microblaze.dat
+@@ -37,3 +37,5 @@ expedite:r1,pc
+ 32:ear
+ 32:esr
+ 32:fsr
++32:slr
++32:shr
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0008-Patch-microblaze-Added-Backtrace-support-to-GDB.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0008-Patch-microblaze-Added-Backtrace-support-to-GDB.patch
new file mode 100644
index 0000000..7f075d5
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0008-Patch-microblaze-Added-Backtrace-support-to-GDB.patch
@@ -0,0 +1,156 @@
+From 7944750e435100e72913f01aa0a43b7d7cffd421 Mon Sep 17 00:00:00 2001
+From: nagaraju <nmekala@xilix.com>
+Date: Tue, 3 Sep 2013 12:09:47 +0530
+Subject: [PATCH 08/16] [Patch, microblaze]: Added Backtrace support to GDB
+
+Added backtrace support without debugging information.
+
+Earlier backtrace used to work only when debug information is available.
+Previous pc & sp values are calculated incorrectly due to which backtrace
+was failing.
+
+In this patch, previous frame sp & pc values are calculated correctly
+in microblaze_frame_cache function and supplied them to
+microblaze_frame_prev_register function
+
+Signed-off-by:nagaraju <nmekala@xilix.com>
+Upstream-Status: Pending
+---
+ gdb/microblaze-tdep.c | 42 ++++++++++++++++++++++++++++++++++--------
+ gdb/microblaze-tdep.h | 5 +++--
+ 2 files changed, 37 insertions(+), 10 deletions(-)
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 0ce4947..247740e 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -225,6 +225,7 @@ microblaze_alloc_frame_cache (void)
+ /* Base address. */
+ cache->base = 0;
+ cache->pc = 0;
++ cache->saved_sp = 0;
+
+ /* Frameless until proven otherwise. */
+ cache->frameless_p = 1;
+@@ -347,6 +348,7 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+ cache->frameless_p = 0; /* Frame found. */
+ save_hidden_pointer_found = 0;
+ non_stack_instruction_found = 0;
++ cache->register_offsets[rd] = -imm;
+ continue;
+ }
+ else if (IS_SPILL_SP(op, rd, ra))
+@@ -508,6 +510,7 @@ microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
+ return start_pc;
+ }
+
++enum { REG_UNAVAIL = (CORE_ADDR) -1 };
+ /* Normal frames. */
+
+ static struct microblaze_frame_cache *
+@@ -515,7 +518,7 @@ microblaze_frame_cache (struct frame_info *next_frame, void **this_cache)
+ {
+ struct microblaze_frame_cache *cache;
+ struct gdbarch *gdbarch = get_frame_arch (next_frame);
+- CORE_ADDR func;
++ CORE_ADDR current_pc;
+ int rn;
+
+ if (*this_cache)
+@@ -529,10 +532,18 @@ microblaze_frame_cache (struct frame_info *next_frame, void **this_cache)
+ for (rn = 0; rn < gdbarch_num_regs (gdbarch); rn++)
+ cache->register_offsets[rn] = -1;
+
+- func = get_frame_func (next_frame);
++ cache->pc = get_frame_func (next_frame);
++ current_pc = get_frame_pc (next_frame);
++
++ if (cache->pc)
++ microblaze_analyze_prologue (gdbarch, cache->pc, current_pc,
++ cache);
+
+ cache->base = get_frame_register_unsigned (next_frame, gdbarch_sp_regnum (gdbarch));
+- cache->pc = get_frame_address_in_block (next_frame);
++ cache->saved_sp = cache->base + cache->framesize;
++
++ cache->register_offsets[MICROBLAZE_PREV_PC_REGNUM] = cache->base;
++ cache->register_offsets[MICROBLAZE_SP_REGNUM] = cache->saved_sp;
+
+ return cache;
+ }
+@@ -548,7 +559,7 @@ microblaze_frame_this_id (struct frame_info *next_frame, void **this_cache,
+ if (cache->base == 0)
+ return;
+
+- (*this_id) = frame_id_build (cache->base, get_frame_pc (next_frame));
++ (*this_id) = frame_id_build (cache->base, cache->pc);
+ }
+
+ static struct value *
+@@ -558,6 +569,14 @@ microblaze_frame_prev_register (struct frame_info *this_frame,
+ struct microblaze_frame_cache *cache =
+ microblaze_frame_cache (this_frame, this_cache);
+
++ if ((regnum == MICROBLAZE_SP_REGNUM &&
++ cache->register_offsets[MICROBLAZE_SP_REGNUM])
++ || (regnum == MICROBLAZE_FP_REGNUM &&
++ cache->register_offsets[MICROBLAZE_SP_REGNUM]))
++
++ return frame_unwind_got_constant (this_frame, regnum,
++ cache->register_offsets[MICROBLAZE_SP_REGNUM]);
++
+ if (cache->frameless_p)
+ {
+ if (regnum == MICROBLAZE_PC_REGNUM)
+@@ -565,11 +584,18 @@ microblaze_frame_prev_register (struct frame_info *this_frame,
+ if (regnum == MICROBLAZE_SP_REGNUM)
+ regnum = 1;
+ return trad_frame_get_prev_register (this_frame,
+- cache->saved_regs, regnum);
++ cache->saved_regs, regnum);
+ }
+- else
+- return trad_frame_get_prev_register (this_frame, cache->saved_regs,
+- regnum);
++
++ if (regnum == MICROBLAZE_PC_REGNUM)
++ {
++ regnum = 15;
++ return frame_unwind_got_memory (this_frame, regnum,
++ cache->register_offsets[MICROBLAZE_PREV_PC_REGNUM]);
++ }
++
++ return trad_frame_get_prev_register (this_frame, cache->saved_regs,
++ regnum);
+
+ }
+
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index cd32e9f..14eb3ab 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -57,6 +57,7 @@ struct microblaze_frame_cache
+
+ /* Offsets to saved registers. */
+ int register_offsets[59]; /* Must match MICROBLAZE_NUM_REGS. */
++ CORE_ADDR saved_sp;
+
+ /* Table of saved registers. */
+ struct trad_frame_saved_reg *saved_regs;
+@@ -80,11 +81,11 @@ enum microblaze_regnum
+ MICROBLAZE_R12_REGNUM,
+ MICROBLAZE_R13_REGNUM,
+ MICROBLAZE_R14_REGNUM,
+- MICROBLAZE_R15_REGNUM,
++ MICROBLAZE_R15_REGNUM, MICROBLAZE_PREV_PC_REGNUM = MICROBLAZE_R15_REGNUM,
+ MICROBLAZE_R16_REGNUM,
+ MICROBLAZE_R17_REGNUM,
+ MICROBLAZE_R18_REGNUM,
+- MICROBLAZE_R19_REGNUM,
++ MICROBLAZE_R19_REGNUM, MICROBLAZE_FP_REGNUM = MICROBLAZE_R19_REGNUM,
+ MICROBLAZE_R20_REGNUM,
+ MICROBLAZE_R21_REGNUM,
+ MICROBLAZE_R22_REGNUM,
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0009-Patch-microblaze-Initial-support-for-native-gdb.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0009-Patch-microblaze-Initial-support-for-native-gdb.patch
new file mode 100644
index 0000000..1ad6b89
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0009-Patch-microblaze-Initial-support-for-native-gdb.patch
@@ -0,0 +1,495 @@
+From c7b918283f2e438deef78aae84f6b748a7a1bb54 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@petalogix.com>
+Date: Fri, 20 Jul 2012 15:18:35 +1000
+Subject: [PATCH 09/16] [Patch, microblaze]: Initial support for native gdb
+
+microblaze: Follow PPC method of getting setting registers
+using PTRACE PEEK/POKE
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Upstream-Status: Pending
+---
+ gdb/Makefile.in | 4 +-
+ gdb/config/microblaze/linux.mh | 10 +
+ gdb/microblaze-linux-nat.c | 431 +++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 443 insertions(+), 2 deletions(-)
+ create mode 100644 gdb/config/microblaze/linux.mh
+ create mode 100644 gdb/microblaze-linux-nat.c
+
+diff --git a/gdb/Makefile.in b/gdb/Makefile.in
+index f2c16ec..12870a4 100644
+--- a/gdb/Makefile.in
++++ b/gdb/Makefile.in
+@@ -904,7 +904,7 @@ top.h bsd-kvm.h gdb-stabs.h reggroups.h \
+ annotate.h sim-regno.h dictionary.h dfp.h main.h frame-unwind.h \
+ remote-fileio.h i386-linux-tdep.h vax-tdep.h objc-lang.h \
+ sentinel-frame.h bcache.h symfile.h windows-tdep.h linux-tdep.h \
+-gdb_usleep.h jit.h xml-syscall.h microblaze-tdep.h \
++gdb_usleep.h jit.h xml-syscall.h microblaze-tdep.h microblaze-linux-tdep.h \
+ psymtab.h psympriv.h progspace.h bfin-tdep.h ia64-hpux-tdep.h \
+ amd64-darwin-tdep.h charset-list.h \
+ config/djgpp/langinfo.h config/djgpp/nl_types.h darwin-nat.h \
+@@ -1631,7 +1631,7 @@ ALLDEPFILES = \
+ m68kbsd-nat.c m68kbsd-tdep.c \
+ m68klinux-nat.c m68klinux-tdep.c \
+ m88k-tdep.c m88kbsd-nat.c \
+- microblaze-tdep.c microblaze-linux-tdep.c \
++ microblaze-tdep.c microblaze-linux-nat.c microblaze-linux-tdep.c \
+ mingw-hdep.c \
+ mips-linux-nat.c mips-linux-tdep.c \
+ mips-irix-tdep.c \
+diff --git a/gdb/config/microblaze/linux.mh b/gdb/config/microblaze/linux.mh
+new file mode 100644
+index 0000000..547d103
+--- /dev/null
++++ b/gdb/config/microblaze/linux.mh
+@@ -0,0 +1,10 @@
++# Host: Microblaze, running Linux
++
++NAT_FILE= config/nm-linux.h
++NATDEPFILES= inf-ptrace.o fork-child.o \
++ microblaze-linux-nat.o proc-service.o linux-thread-db.o \
++ linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o \
++ linux-waitpid.o
++NAT_CDEPS = $(srcdir)/proc-service.list
++
++LOADLIBES = -ldl $(RDYNAMIC)
+diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c
+new file mode 100644
+index 0000000..81f8346
+--- /dev/null
++++ b/gdb/microblaze-linux-nat.c
+@@ -0,0 +1,431 @@
++/* Microblaze GNU/Linux native support.
++
++ Copyright (C) 1988-1989, 1991-1992, 1994, 1996, 2000-2012 Free
++ Software Foundation, Inc.
++
++ This file is part of GDB.
++
++ This program is free software; you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 3 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program. If not, see <http://www.gnu.org/licenses/>. */
++
++#include "defs.h"
++#include "arch-utils.h"
++#include "dis-asm.h"
++#include "frame.h"
++#include "trad-frame.h"
++#include "symtab.h"
++#include "value.h"
++#include "gdbcmd.h"
++#include "breakpoint.h"
++#include "inferior.h"
++#include "regcache.h"
++#include "target.h"
++#include "frame.h"
++#include "frame-base.h"
++#include "frame-unwind.h"
++#include "dwarf2-frame.h"
++#include "osabi.h"
++
++#include "gdb_assert.h"
++#include <string.h>
++#include "target-descriptions.h"
++#include "opcodes/microblaze-opcm.h"
++#include "opcodes/microblaze-dis.h"
++
++#include "linux-nat.h"
++#include "target-descriptions.h"
++
++#include <sys/user.h>
++#include <sys/utsname.h>
++#include <sys/procfs.h>
++#include <sys/ptrace.h>
++
++/* Prototypes for supply_gregset etc. */
++#include "gregset.h"
++
++#include "microblaze-tdep.h"
++
++#include <elf/common.h>
++#include "auxv.h"
++
++/* Defines ps_err_e, struct ps_prochandle. */
++#include "gdb_proc_service.h"
++
++/* On GNU/Linux, threads are implemented as pseudo-processes, in which
++ case we may be tracing more than one process at a time. In that
++ case, inferior_ptid will contain the main process ID and the
++ individual thread (process) ID. get_thread_id () is used to get
++ the thread id if it's available, and the process id otherwise. */
++
++int
++get_thread_id (ptid_t ptid)
++{
++ int tid = ptid_get_lwp (ptid);
++ if (0 == tid)
++ tid = ptid_get_pid (ptid);
++ return tid;
++}
++
++#define GET_THREAD_ID(PTID) get_thread_id (PTID)
++
++/* Non-zero if our kernel may support the PTRACE_GETREGS and
++ PTRACE_SETREGS requests, for reading and writing the
++ general-purpose registers. Zero if we've tried one of
++ them and gotten an error. */
++int have_ptrace_getsetregs = 1;
++
++static int
++microblaze_register_u_addr (struct gdbarch *gdbarch, int regno)
++{
++ int u_addr = -1;
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
++ interface, and not the wordsize of the program's ABI. */
++ int wordsize = sizeof (long);
++
++ /* General purpose registers occupy 1 slot each in the buffer. */
++ if (regno >= MICROBLAZE_R0_REGNUM
++ && regno <= MICROBLAZE_FSR_REGNUM)
++ u_addr = (regno * wordsize);
++
++ return u_addr;
++}
++
++
++static void
++fetch_register (struct regcache *regcache, int tid, int regno)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ /* This isn't really an address. But ptrace thinks of it as one. */
++ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
++ int bytes_transferred;
++ unsigned int offset; /* Offset of registers within the u area. */
++ char buf[MAX_REGISTER_SIZE];
++
++ if (regaddr == -1)
++ {
++ memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */
++ regcache_raw_supply (regcache, regno, buf);
++ return;
++ }
++
++ /* Read the raw register using sizeof(long) sized chunks. On a
++ 32-bit platform, 64-bit floating-point registers will require two
++ transfers. */
++ for (bytes_transferred = 0;
++ bytes_transferred < register_size (gdbarch, regno);
++ bytes_transferred += sizeof (long))
++ {
++ long l;
++
++ errno = 0;
++ l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
++ regaddr += sizeof (long);
++ if (errno != 0)
++ {
++ char message[128];
++ sprintf (message, "reading register %s (#%d)",
++ gdbarch_register_name (gdbarch, regno), regno);
++ perror_with_name (message);
++ }
++ memcpy (&buf[bytes_transferred], &l, sizeof (l));
++ }
++
++ /* Now supply the register. Keep in mind that the regcache's idea
++ of the register's size may not be a multiple of sizeof
++ (long). */
++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
++ {
++ /* Little-endian values are always found at the left end of the
++ bytes transferred. */
++ regcache_raw_supply (regcache, regno, buf);
++ }
++ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++ {
++ /* Big-endian values are found at the right end of the bytes
++ transferred. */
++ size_t padding = (bytes_transferred - register_size (gdbarch, regno));
++ regcache_raw_supply (regcache, regno, buf + padding);
++ }
++ else
++ internal_error (__FILE__, __LINE__,
++ _("fetch_register: unexpected byte order: %d"),
++ gdbarch_byte_order (gdbarch));
++}
++
++/* This function actually issues the request to ptrace, telling
++ it to get all general-purpose registers and put them into the
++ specified regset.
++
++ If the ptrace request does not exist, this function returns 0
++ and properly sets the have_ptrace_* flag. If the request fails,
++ this function calls perror_with_name. Otherwise, if the request
++ succeeds, then the regcache gets filled and 1 is returned. */
++static int
++fetch_all_gp_regs (struct regcache *regcache, int tid)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ gdb_gregset_t gregset;
++
++ if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
++ {
++ if (errno == EIO)
++ {
++ have_ptrace_getsetregs = 0;
++ return 0;
++ }
++ perror_with_name (_("Couldn't get general-purpose registers."));
++ }
++
++ supply_gregset (regcache, (const gdb_gregset_t *) &gregset);
++
++ return 1;
++}
++
++
++/* This is a wrapper for the fetch_all_gp_regs function. It is
++ responsible for verifying if this target has the ptrace request
++ that can be used to fetch all general-purpose registers at one
++ shot. If it doesn't, then we should fetch them using the
++ old-fashioned way, which is to iterate over the registers and
++ request them one by one. */
++static void
++fetch_gp_regs (struct regcache *regcache, int tid)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ int i;
++
++ if (have_ptrace_getsetregs)
++ if (fetch_all_gp_regs (regcache, tid))
++ return;
++
++ /* If we've hit this point, it doesn't really matter which
++ architecture we are using. We just need to read the
++ registers in the "old-fashioned way". */
++ for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)
++ fetch_register (regcache, tid, i);
++}
++
++
++static void
++store_register (const struct regcache *regcache, int tid, int regno)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ /* This isn't really an address. But ptrace thinks of it as one. */
++ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
++ int i;
++ size_t bytes_to_transfer;
++ char buf[MAX_REGISTER_SIZE];
++
++ if (regaddr == -1)
++ return;
++
++ /* First collect the register. Keep in mind that the regcache's
++ idea of the register's size may not be a multiple of sizeof
++ (long). */
++ memset (buf, 0, sizeof buf);
++ bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
++ {
++ /* Little-endian values always sit at the left end of the buffer. */
++ regcache_raw_collect (regcache, regno, buf);
++ }
++ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++ {
++ /* Big-endian values sit at the right end of the buffer. */
++ size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
++ regcache_raw_collect (regcache, regno, buf + padding);
++ }
++
++ for (i = 0; i < bytes_to_transfer; i += sizeof (long))
++ {
++ long l;
++
++ memcpy (&l, &buf[i], sizeof (l));
++ errno = 0;
++ ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l);
++ regaddr += sizeof (long);
++
++ if (errno != 0)
++ {
++ char message[128];
++ sprintf (message, "writing register %s (#%d)",
++ gdbarch_register_name (gdbarch, regno), regno);
++ perror_with_name (message);
++ }
++ }
++}
++
++/* This function actually issues the request to ptrace, telling
++ it to store all general-purpose registers present in the specified
++ regset.
++
++ If the ptrace request does not exist, this function returns 0
++ and properly sets the have_ptrace_* flag. If the request fails,
++ this function calls perror_with_name. Otherwise, if the request
++ succeeds, then the regcache is stored and 1 is returned. */
++static int
++store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ gdb_gregset_t gregset;
++
++ if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
++ {
++ if (errno == EIO)
++ {
++ have_ptrace_getsetregs = 0;
++ return 0;
++ }
++ perror_with_name (_("Couldn't get general-purpose registers."));
++ }
++
++ fill_gregset (regcache, &gregset, regno);
++
++ if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0)
++ {
++ if (errno == EIO)
++ {
++ have_ptrace_getsetregs = 0;
++ return 0;
++ }
++ perror_with_name (_("Couldn't set general-purpose registers."));
++ }
++
++ return 1;
++}
++
++/* This is a wrapper for the store_all_gp_regs function. It is
++ responsible for verifying if this target has the ptrace request
++ that can be used to store all general-purpose registers at one
++ shot. If it doesn't, then we should store them using the
++ old-fashioned way, which is to iterate over the registers and
++ store them one by one. */
++static void
++store_gp_regs (const struct regcache *regcache, int tid, int regno)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ int i;
++
++ if (have_ptrace_getsetregs)
++ if (store_all_gp_regs (regcache, tid, regno))
++ return;
++
++ /* If we hit this point, it doesn't really matter which
++ architecture we are using. We just need to store the
++ registers in the "old-fashioned way". */
++ for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)
++ store_register (regcache, tid, i);
++}
++
++
++/* Fetch registers from the child process. Fetch all registers if
++ regno == -1, otherwise fetch all general registers or all floating
++ point registers depending upon the value of regno. */
++
++static void
++microblaze_linux_fetch_inferior_registers (struct target_ops *ops,
++ struct regcache *regcache, int regno)
++{
++ /* Get the thread id for the ptrace call. */
++ int tid = GET_THREAD_ID (inferior_ptid);
++
++ if (regno == -1)
++ fetch_gp_regs (regcache, tid);
++ else
++ fetch_register (regcache, tid, regno);
++}
++
++/* Store registers back into the inferior. Store all registers if
++ regno == -1, otherwise store all general registers or all floating
++ point registers depending upon the value of regno. */
++
++static void
++microblaze_linux_store_inferior_registers (struct target_ops *ops,
++ struct regcache *regcache, int regno)
++{
++ /* Get the thread id for the ptrace call. */
++ int tid = GET_THREAD_ID (inferior_ptid);
++
++ if (regno >= 0)
++ store_register (regcache, tid, regno);
++ else
++ store_gp_regs (regcache, tid, -1);
++}
++
++/* Wrapper functions for the standard regset handling, used by
++ thread debugging. */
++
++void
++fill_gregset (const struct regcache *regcache,
++ gdb_gregset_t *gregsetp, int regno)
++{
++ microblaze_collect_gregset (NULL, regcache, regno, gregsetp);
++}
++
++void
++supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
++{
++ microblaze_supply_gregset (NULL, regcache, -1, gregsetp);
++}
++
++void
++fill_fpregset (const struct regcache *regcache,
++ gdb_fpregset_t *fpregsetp, int regno)
++{
++ /* FIXME. */
++}
++
++void
++supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
++{
++ /* FIXME. */
++}
++
++static const struct target_desc *
++microblaze_linux_read_description (struct target_ops *ops)
++{
++ CORE_ADDR microblaze_hwcap = 0;
++
++ if (target_auxv_search (ops, AT_HWCAP, µblaze_hwcap) != 1)
++ return NULL;
++
++ return NULL;
++}
++
++
++void _initialize_microblaze_linux_nat (void);
++
++void
++_initialize_microblaze_linux_nat (void)
++{
++ struct target_ops *t;
++
++ /* Fill in the generic GNU/Linux methods. */
++ t = linux_target ();
++
++ /* Add our register access methods. */
++ t->to_fetch_registers = microblaze_linux_fetch_inferior_registers;
++ t->to_store_registers = microblaze_linux_store_inferior_registers;
++
++ t->to_read_description = microblaze_linux_read_description;
++
++ /* Register the target. */
++ linux_nat_add_target (t);
++}
+--
+1.9.0
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0010-Patch-gdb-Robustify-inline-function-support.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0010-Patch-gdb-Robustify-inline-function-support.patch
new file mode 100644
index 0000000..3912ca5
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0010-Patch-gdb-Robustify-inline-function-support.patch
@@ -0,0 +1,43 @@
+From a02963a97d7ce38b0af205f9e3e6dd7e0e06d9be Mon Sep 17 00:00:00 2001
+From: "Edgar E. Iglesias" <edgar@axis.com>
+Date: Mon, 27 Feb 2012 06:28:00 +0100
+Subject: [PATCH 10/16] [Patch, gdb]: Robustify inline function support
+
+Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
+Upstream-Status: Pending
+---
+ gdb/blockframe.c | 3 ++-
+ gdb/inline-frame.c | 3 +++
+ 2 files changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/gdb/blockframe.c b/gdb/blockframe.c
+index 0a9381e..ba41d85 100644
+--- a/gdb/blockframe.c
++++ b/gdb/blockframe.c
+@@ -77,7 +77,8 @@ get_frame_block (struct frame_info *frame, CORE_ADDR *addr_in_block)
+ inline_count--;
+
+ bl = BLOCK_SUPERBLOCK (bl);
+- gdb_assert (bl != NULL);
++ if (!bl)
++ return NULL;
+ }
+
+ return bl;
+diff --git a/gdb/inline-frame.c b/gdb/inline-frame.c
+index eb82143..a793390 100644
+--- a/gdb/inline-frame.c
++++ b/gdb/inline-frame.c
+@@ -231,6 +231,9 @@ inline_frame_sniffer (const struct frame_unwind *self,
+ cur_block = BLOCK_SUPERBLOCK (cur_block);
+ }
+
++ if (depth == 0)
++ return 0;
++
+ /* Check how many inlined functions already have frames. */
+ for (next_frame = get_next_frame (this_frame);
+ next_frame && get_frame_type (next_frame) == INLINE_FRAME;
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0011-Patch-gdb-Fix-debug-message-when-register-is-unavail.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0011-Patch-gdb-Fix-debug-message-when-register-is-unavail.patch
new file mode 100644
index 0000000..bdec77c
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0011-Patch-gdb-Fix-debug-message-when-register-is-unavail.patch
@@ -0,0 +1,43 @@
+From a05fb34192727fc1b63c827ed006ddde846ce6b8 Mon Sep 17 00:00:00 2001
+From: Nathan Rossi <nathan.rossi@petalogix.com>
+Date: Tue, 8 May 2012 18:11:17 +1000
+Subject: [PATCH 11/16] [Patch, gdb]: Fix debug message when register is
+ unavailable
+
+Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ gdb/frame.c | 13 ++++++++++---
+ 1 file changed, 10 insertions(+), 3 deletions(-)
+
+diff --git a/gdb/frame.c b/gdb/frame.c
+index 013d602..4d0766f 100644
+--- a/gdb/frame.c
++++ b/gdb/frame.c
+@@ -1134,12 +1134,19 @@ frame_unwind_register_value (struct frame_info *frame, int regnum)
+ else
+ {
+ int i;
+- const gdb_byte *buf = value_contents (value);
++ const gdb_byte *buf = NULL;
++ if (value_entirely_available(value)) {
++ buf = value_contents (value);
++ }
+
+ fprintf_unfiltered (gdb_stdlog, " bytes=");
+ fprintf_unfiltered (gdb_stdlog, "[");
+- for (i = 0; i < register_size (gdbarch, regnum); i++)
+- fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]);
++ if (buf != NULL) {
++ for (i = 0; i < register_size (gdbarch, regnum); i++)
++ fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]);
++ } else {
++ fprintf_unfiltered (gdb_stdlog, "unavailable");
++ }
+ fprintf_unfiltered (gdb_stdlog, "]");
+ }
+ }
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0012-LOCAL-Disable-the-warning-message-for-eh_frame_hdr.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0012-LOCAL-Disable-the-warning-message-for-eh_frame_hdr.patch
new file mode 100644
index 0000000..819cd17
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0012-LOCAL-Disable-the-warning-message-for-eh_frame_hdr.patch
@@ -0,0 +1,34 @@
+From f54d5334afe799e15ca21c5d83097a4c81bbab7e Mon Sep 17 00:00:00 2001
+From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
+Date: Fri, 22 Jun 2012 01:20:20 +0200
+Subject: [PATCH 12/16] [LOCAL]: Disable the warning message for eh_frame_hdr
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Upstream-Status: Pending
+---
+ bfd/elf-eh-frame.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c
+index 0f0a563..7d8e047 100644
+--- a/bfd/elf-eh-frame.c
++++ b/bfd/elf-eh-frame.c
+@@ -919,9 +919,12 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info,
+ goto success;
+
+ free_no_table:
+- (*info->callbacks->einfo)
+- (_("%P: error in %B(%A); no .eh_frame_hdr table will be created.\n"),
+- abfd, sec);
++ /* FIXME: Remove the microblaze specifics when relaxing gets fixed. */
++ if (bfd_get_arch(abfd) != bfd_arch_microblaze) {
++ (*info->callbacks->einfo)
++ (_("%P: error in %B(%A); no .eh_frame_hdr table will be created.\n"),
++ abfd, sec);
++ }
+ hdr_info->table = FALSE;
+ if (sec_info)
+ free (sec_info);
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0013-LOCAL-Fix-relaxation-of-assembler-resolved-reference.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0013-LOCAL-Fix-relaxation-of-assembler-resolved-reference.patch
new file mode 100644
index 0000000..3a0eae8
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0013-LOCAL-Fix-relaxation-of-assembler-resolved-reference.patch
@@ -0,0 +1,64 @@
+From c9f1f07e5b0756069e3d4b04eb9505027f09677f Mon Sep 17 00:00:00 2001
+From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
+Date: Tue, 14 Feb 2012 01:00:22 +0100
+Subject: [PATCH 13/16] [LOCAL]: Fix relaxation of assembler resolved
+ references
+
+Upstream-Status: Pending
+---
+ bfd/elf32-microblaze.c | 39 +++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 39 insertions(+)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index cbd18f0..f90df47 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -1968,6 +1968,45 @@ microblaze_elf_relax_section (bfd *abfd,
+ irelscanend = irelocs + o->reloc_count;
+ for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+ {
++ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
++ {
++ unsigned int val;
++
++ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
++
++ /* This was a PC-relative instruction that was completely resolved. */
++ if (ocontents == NULL)
++ {
++ if (elf_section_data (o)->this_hdr.contents != NULL)
++ ocontents = elf_section_data (o)->this_hdr.contents;
++ else
++ {
++ /* We always cache the section contents.
++ Perhaps, if info->keep_memory is FALSE, we
++ should free them, if we are permitted to. */
++
++ if (o->rawsize == 0)
++ o->rawsize = o->size;
++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++ if (ocontents == NULL)
++ goto error_return;
++ if (!bfd_get_section_contents (abfd, o, ocontents,
++ (file_ptr) 0,
++ o->rawsize))
++ goto error_return;
++ elf_section_data (o)->this_hdr.contents = ocontents;
++ }
++ }
++
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend
++ + isym->st_value, sec);
++ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
++ irelscan->r_addend);
++ }
++ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
++ fprintf(stderr, "Unhandled NONE 64\n");
++ }
+ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+ {
+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0014-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0014-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch
new file mode 100644
index 0000000..85cee9d
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0014-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch
@@ -0,0 +1,192 @@
+From aca2758cff1f8fdc5ad7b6076ef985ba9ec5f857 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Mon, 4 Feb 2013 12:15:22 +1000
+Subject: [PATCH 14/16] [LOCAL]: Fixup debug_loc sections after linker
+ relaxation
+
+Adds a new reloctype R_MICROBLAZE_32_NONE, used for passing
+reloc info from the assembler to the linker when the linker
+manages to fully resolve a local symbol reference.
+
+This is a workaround for design flaws in the assembler to
+linker interface with regards to linker relaxation.
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ bfd/bfd-in2.h | 5 +++++
+ bfd/elf32-microblaze.c | 45 +++++++++++++++++++++++++++++++++++++--------
+ bfd/libbfd.h | 1 +
+ bfd/reloc.c | 6 ++++++
+ include/elf/microblaze.h | 1 +
+ 5 files changed, 50 insertions(+), 8 deletions(-)
+
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 8b7f2ee..de38907 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -5449,6 +5449,11 @@ value relative to the read-write small data area anchor */
+ expressions of the form "Symbol Op Symbol" */
+ BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
+
++/* This is a 32 bit reloc that stores the 32 bit pc relative
++value in two words (with an imm instruction). No relocation is
++done here - only used for relaxing */
++ BFD_RELOC_MICROBLAZE_32_NONE,
++
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction). No relocation is
+ done here - only used for relaxing */
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index f90df47..a3f89b9 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -177,6 +177,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+ FALSE), /* PC relative offset? */
+
+ /* This reloc does nothing. Used for relaxation. */
++ HOWTO (R_MICROBLAZE_32_NONE, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 32, /* Bitsize. */
++ TRUE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_bitfield, /* Complain on overflow. */
++ NULL, /* Special Function. */
++ "R_MICROBLAZE_32_NONE",/* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
+ HOWTO (R_MICROBLAZE_64_NONE, /* Type. */
+ 0, /* Rightshift. */
+ 2, /* Size (0 = byte, 1 = short, 2 = long). */
+@@ -532,7 +546,10 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+ case BFD_RELOC_NONE:
+ microblaze_reloc = R_MICROBLAZE_NONE;
+ break;
+- case BFD_RELOC_MICROBLAZE_64_NONE:
++ case BFD_RELOC_MICROBLAZE_32_NONE:
++ microblaze_reloc = R_MICROBLAZE_32_NONE;
++ break;
++ case BFD_RELOC_MICROBLAZE_64_NONE:
+ microblaze_reloc = R_MICROBLAZE_64_NONE;
+ break;
+ case BFD_RELOC_32:
+@@ -1913,14 +1930,22 @@ microblaze_elf_relax_section (bfd *abfd,
+ }
+ break;
+ case R_MICROBLAZE_NONE:
++ case R_MICROBLAZE_32_NONE:
+ {
+ /* This was a PC-relative instruction that was
+ completely resolved. */
+ int sfix, efix;
++ unsigned int val;
+ bfd_vma target_address;
+ target_address = irel->r_addend + irel->r_offset;
+ sfix = calc_fixup (irel->r_offset, 0, sec);
+ efix = calc_fixup (target_address, 0, sec);
++
++ /* Validate the in-band val. */
++ val = bfd_get_32 (abfd, contents + irel->r_offset);
++ if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++ }
+ irel->r_addend -= (efix - sfix);
+ /* Should use HOWTO. */
+ microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
+@@ -1968,12 +1993,16 @@ microblaze_elf_relax_section (bfd *abfd,
+ irelscanend = irelocs + o->reloc_count;
+ for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+ {
+- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
++ if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
+ {
+ unsigned int val;
+
+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+
++ /* hax: We only do the following fixup for debug location lists. */
++ if (strcmp(".debug_loc", o->name))
++ continue;
++
+ /* This was a PC-relative instruction that was completely resolved. */
+ if (ocontents == NULL)
+ {
+@@ -1998,15 +2027,15 @@ microblaze_elf_relax_section (bfd *abfd,
+ }
+ }
+
+- irelscan->r_addend -= calc_fixup (irelscan->r_addend
+- + isym->st_value, sec);
+ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++ if (val != irelscan->r_addend) {
++ fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
++ }
++
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
+ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
+ irelscan->r_addend);
+ }
+- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
+- fprintf(stderr, "Unhandled NONE 64\n");
+- }
+ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+ {
+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+@@ -2066,7 +2095,7 @@ microblaze_elf_relax_section (bfd *abfd,
+ elf_section_data (o)->this_hdr.contents = ocontents;
+ }
+ }
+- irelscan->r_addend -= calc_fixup (irel->r_addend
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend
+ + isym->st_value,
+ 0,
+ sec);
+diff --git a/bfd/libbfd.h b/bfd/libbfd.h
+index 09f307f..840c662 100644
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -2644,6 +2644,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+ "BFD_RELOC_MICROBLAZE_32_ROSDA",
+ "BFD_RELOC_MICROBLAZE_32_RWSDA",
+ "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
++ "BFD_RELOC_MICROBLAZE_32_NONE",
+ "BFD_RELOC_MICROBLAZE_64_NONE",
+ "BFD_RELOC_MICROBLAZE_64_GOTPC",
+ "BFD_RELOC_MICROBLAZE_64_GOT",
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index 7f46c58..5bcd52d 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6396,6 +6396,12 @@ ENUMDOC
+ This is a 32 bit reloc for the microblaze to handle
+ expressions of the form "Symbol Op Symbol"
+ ENUM
++ BFD_RELOC_MICROBLAZE_32_NONE
++ENUMDOC
++ This is a 32 bit reloc that stores the 32 bit pc relative
++ value in two words (with an imm instruction). No relocation is
++ done here - only used for relaxing
++ENUM
+ BFD_RELOC_MICROBLAZE_64_NONE
+ ENUMDOC
+ This is a 64 bit reloc that stores the 32 bit pc relative
+diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
+index effca20..f8420dc 100644
+--- a/include/elf/microblaze.h
++++ b/include/elf/microblaze.h
+@@ -58,6 +58,7 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
+ RELOC_NUMBER (R_MICROBLAZE_TLSDTPREL64, 27) /* TLS Offset Within TLS Block */
+ RELOC_NUMBER (R_MICROBLAZE_TLSGOTTPREL32, 28) /* TLS Offset From Thread Pointer */
+ RELOC_NUMBER (R_MICROBLAZE_TLSTPREL32, 29) /* TLS Offset From Thread Pointer */
++ RELOC_NUMBER (R_MICROBLAZE_32_NONE, 30)
+
+ END_RELOC_NUMBERS (R_MICROBLAZE_max)
+
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0015-LOCAL-upstream-change-to-garbage-collection-sweep-ca.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0015-LOCAL-upstream-change-to-garbage-collection-sweep-ca.patch
new file mode 100644
index 0000000..0bb66a9
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/files/0015-LOCAL-upstream-change-to-garbage-collection-sweep-ca.patch
@@ -0,0 +1,40 @@
+From 22c63d4d79ac488403340470c14c73bad4984fa3 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Wed, 27 Feb 2013 13:56:11 +1000
+Subject: [PATCH 15/16] [LOCAL]: upstream change to garbage collection sweep
+ causes mb regression
+
+Upstream change for PR13177 now clears the def_regular during gc_sweep of a
+section. (All other archs in binutils/bfd/elf32-*.c received an update
+to a warning about unresolvable relocations - this warning is not present
+in binutils/bfd/elf32-microblaze.c, but this warning check would not
+prevent the error being seen)
+
+The visible issue with this change is when running a c++ application
+in Petalinux which links libstdc++.so for exception handling it segfaults
+on execution.
+
+This does not occur if static linking libstdc++.a, so its during the
+relocations for a shared lib with garbage collection this occurs
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ bfd/elflink.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/bfd/elflink.c b/bfd/elflink.c
+index 6756fb1..f21dc06 100644
+--- a/bfd/elflink.c
++++ b/bfd/elflink.c
+@@ -11932,7 +11932,6 @@ elf_gc_sweep_symbol (struct elf_link_hash_entry *h, void *data)
+
+ inf = (struct elf_gc_sweep_symbol_info *) data;
+ (*inf->hide_symbol) (inf->info, h, TRUE);
+- h->def_regular = 0;
+ h->ref_regular = 0;
+ h->ref_regular_nonweak = 0;
+ }
+--
+1.9.0
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-7.7.1.inc b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-7.7.1.inc
new file mode 100644
index 0000000..396f0fc
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-7.7.1.inc
@@ -0,0 +1,12 @@
+LICENSE = "GPLv2 & GPLv3 & LGPLv2 & LGPLv3"
+LIC_FILES_CHKSUM = "file://COPYING;md5=59530bdf33659b29e73d4adb9f9f6552 \
+ file://COPYING3;md5=d32239bcb673463ab874e80d47fae504 \
+ file://COPYING3.LIB;md5=6a6a8e020838b23406c81b19c1d46df6 \
+ file://COPYING.LIB;md5=9f604d8a4f8e74f4f5140845a21b6674"
+
+S = "${WORKDIR}/${BPN}-${PV}"
+
+SRC_URI = "${GNU_MIRROR}/gdb/gdb-${PV}.tar.gz"
+SRC_URI[md5sum] = "45b07b53d81832d32ccd4829465d4886"
+SRC_URI[sha256sum] = "eefadb9831e3695d1eaef34e98b8f1fb441df6fe5071317ea49c6bd6ba213eff"
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-cross-canadian_7.7.1.bb b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-cross-canadian_7.7.1.bb
new file mode 100644
index 0000000..c349ebb
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-cross-canadian_7.7.1.bb
@@ -0,0 +1,4 @@
+require recipes-devtools/gdb/gdb-common.inc
+require recipes-devtools/gdb/gdb-cross-canadian.inc
+require gdb-${PV}.inc
+require gdb-microblaze-7.7.inc
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-cross_7.7.1.bb b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-cross_7.7.1.bb
new file mode 100644
index 0000000..98b3359
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-cross_7.7.1.bb
@@ -0,0 +1,3 @@
+require recipes-devtools/gdb/gdb-cross.inc
+require gdb-${PV}.inc
+require gdb-microblaze-7.7.inc
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-microblaze-7.7.inc b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-microblaze-7.7.inc
new file mode 100644
index 0000000..d1aba82
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb-microblaze-7.7.inc
@@ -0,0 +1,22 @@
+
+# MicroBlaze does not support LTTng UST
+LTTNGUST_microblaze = ""
+
+# Add MicroBlaze Patches
+FILESEXTRAPATHS_append := "${THISDIR}/files:"
+SRC_URI_append = " \
+ file://0001-Patch-microblaze-Add-wdc.ext.clear-and-wdc.ext.flush.patch \
+ file://0003-Patch-microblaze-Initial-port-of-microblaze-core-rea.patch \
+ file://0004-Patch-microblaze-Communicate-in-larger-blocks-with-t.patch \
+ file://0005-Patch-microblaze-Add-mb-singlestepping.patch \
+ file://0006-Patch-microblaze-Add-initial-port-of-linux-gdbserver.patch \
+ file://0007-Patch-microblaze-Add-slr-and-shr-regs-and-little-end.patch \
+ file://0008-Patch-microblaze-Added-Backtrace-support-to-GDB.patch \
+ file://0009-Patch-microblaze-Initial-support-for-native-gdb.patch \
+ file://0010-Patch-gdb-Robustify-inline-function-support.patch \
+ file://0011-Patch-gdb-Fix-debug-message-when-register-is-unavail.patch \
+ file://0012-LOCAL-Disable-the-warning-message-for-eh_frame_hdr.patch \
+ file://0013-LOCAL-Fix-relaxation-of-assembler-resolved-reference.patch \
+ file://0014-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch \
+ file://0015-LOCAL-upstream-change-to-garbage-collection-sweep-ca.patch \
+ "
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb_7.7.1.bb b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb_7.7.1.bb
new file mode 100644
index 0000000..80b589a
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gdb/gdb_7.7.1.bb
@@ -0,0 +1,29 @@
+require recipes-devtools/gdb/gdb-common.inc
+require gdb-${PV}.inc
+require gdb-microblaze-7.7.inc
+
+inherit gettext
+inherit python-dir
+
+PACKAGECONFIG ??= ""
+PACKAGECONFIG[python] = "--with-python=${WORKDIR}/python,--without-python,python"
+PACKAGECONFIG[babeltrace] = "--with-babeltrace,--without-babeltrace,babeltrace"
+
+do_configure_prepend() {
+ if [ -n "${@bb.utils.contains('PACKAGECONFIG', 'python', 'python', '', d)}" ]; then
+ cat > ${WORKDIR}/python << EOF
+#!/bin/sh
+case "\$2" in
+ --includes) echo "-I${STAGING_INCDIR}/${PYTHON_DIR}/" ;;
+ --ldflags) echo "-Wl,-rpath-link,${STAGING_LIBDIR}/.. -Wl,-rpath,${libdir}/.. -lpthread -ldl -lutil -lm -lpython${PYTHON_BASEVERSION}" ;;
+ --exec-prefix) echo "${exec_prefix}" ;;
+ *) exit 1 ;;
+esac
+exit 0
+EOF
+ chmod +x ${WORKDIR}/python
+ fi
+}
+
+PACKAGES =+ "gdbserver"
+FILES_gdbserver = "${bindir}/gdbserver"
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/qemu/qemu_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/qemu/qemu_%.bbappend
new file mode 100644
index 0000000..3d3a54f
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/qemu/qemu_%.bbappend
@@ -0,0 +1,2 @@
+QEMU_TARGETS += "microblazeel microblaze"
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/kernel-module-vcu.bb b/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/kernel-module-vcu.bb
new file mode 100644
index 0000000..e09dd5d
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/kernel-module-vcu.bb
@@ -0,0 +1,29 @@
+SUMMARY = "Linux kernel module for Video Code Unit"
+DESCRIPTION = "Out-of-tree VCU decoder, encoder and common kernel modules provider for MPSoC EV devices"
+SECTION = "kernel/modules"
+LICENSE = "GPLv2"
+LIC_FILES_CHKSUM = "file://LICENSE.md;md5=eb723b61539feef013de476e68b5c50a"
+
+XILINX_VCU_VERSION = "1.0.0"
+XILINX_RELEASE_VERSION = "2018.1"
+PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}"
+
+S = "${WORKDIR}/git"
+
+BRANCH ?= "master"
+REPO ?= "git://github.com/xilinx/vcu-modules.git;protocol=https"
+SRCREV ?= "646185390cc1850969c0fa3db59fc8f0e511922e"
+
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
+
+inherit module
+
+EXTRA_OEMAKE += "O=${STAGING_KERNEL_BUILDDIR}"
+
+RDEPENDS_${PN} = "vcu-firmware"
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE_zynqmp = "zynqmp"
+
+PACKAGE_ARCH = "${SOC_FAMILY}"
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/libomxil-xlnx.bb b/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/libomxil-xlnx.bb
new file mode 100644
index 0000000..76fdb9a
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/libomxil-xlnx.bb
@@ -0,0 +1,51 @@
+SUMMARY = "OpenMAX Integration layer for VCU"
+DESCRIPTION = "OMX IL Libraries,test applications and headers for VCU"
+LICENSE = "Proprietary"
+LIC_FILES_CHKSUM = "file://LICENSE.md;md5=03a7aef7e6f6a76a59fd9b8ba450b493"
+
+XILINX_VCU_VERSION = "1.0.0"
+XILINX_RELEASE_VERSION = "2018.1"
+PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}"
+
+BRANCH ?= "master"
+REPO ?= "git://github.com/xilinx/vcu-omx-il.git;protocol=https"
+SRCREV ?= "68e385ace99ab699feaa50f24b7a78680c411f75"
+
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
+
+S = "${WORKDIR}/git"
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE_zynqmp = "zynqmp"
+
+PACKAGE_ARCH = "${SOC_FAMILY}"
+
+DEPENDS = "libvcu-xlnx"
+RDEPENDS_${PN} = "kernel-module-vcu libvcu-xlnx"
+
+EXTERNAL_INCLUDE="${STAGING_INCDIR}/vcu-ctrl-sw/include"
+
+EXTRA_OEMAKE = " \
+ CC='${CC}' CXX='${CXX} ${CXXFLAGS}' \
+ EXTERNAL_INCLUDE='${EXTERNAL_INCLUDE}' \
+ "
+
+do_install() {
+ install -d ${D}${libdir}
+ install -d ${D}${includedir}/vcu-omx-il
+
+ install -m 0644 ${S}/omx_header/*.h ${D}${includedir}/vcu-omx-il
+
+ install -Dm 0755 ${S}/bin/omx_decoder.exe ${D}/${bindir}/omx_decoder.exe
+ install -Dm 0755 ${S}/bin/omx_encoder.exe ${D}/${bindir}/omx_encoder.exe
+
+ oe_libinstall -C ${S}/bin/ -so libOMX.allegro.core ${D}/${libdir}/
+ oe_libinstall -C ${S}/bin/ -so libOMX.allegro.video_decoder ${D}/${libdir}/
+ oe_libinstall -C ${S}/bin/ -so libOMX.allegro.video_encoder ${D}/${libdir}/
+}
+
+# These libraries shouldn't get installed in world builds unless something
+# explicitly depends upon them.
+
+EXCLUDE_FROM_WORLD = "1"
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/libvcu-xlnx.bb b/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/libvcu-xlnx.bb
new file mode 100644
index 0000000..8e2369b
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/libvcu-xlnx.bb
@@ -0,0 +1,43 @@
+SUMMARY = "Control Software for VCU"
+DESCRIPTION = "Control software libraries, test applications and headers provider for VCU"
+LICENSE = "Proprietary"
+LIC_FILES_CHKSUM = "file://LICENSE.md;md5=03a7aef7e6f6a76a59fd9b8ba450b493"
+
+XILINX_VCU_VERSION = "1.0.0"
+XILINX_RELEASE_VERSION = "2018.1"
+PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}"
+
+BRANCH ?= "master"
+REPO ?= "git://github.com/xilinx/vcu-ctrl-sw.git;protocol=https"
+SRCREV = "aa4b6871346c915f28a069190afec5d30963762f"
+
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
+
+S = "${WORKDIR}/git"
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE_zynqmp = "zynqmp"
+
+PACKAGE_ARCH = "${SOC_FAMILY}"
+
+RDEPENDS_${PN} = "kernel-module-vcu"
+
+EXTRA_OEMAKE = "CC='${CC}' CXX='${CXX} ${CXXFLAGS}'"
+
+do_install() {
+ install -d ${D}${libdir}
+ install -d ${D}${includedir}/vcu-ctrl-sw/include
+
+ install -Dm 0755 ${S}/bin/AL_Encoder.exe ${D}/${bindir}/AL_Encoder.exe
+ install -Dm 0755 ${S}/bin/AL_Decoder.exe ${D}/${bindir}/AL_Decoder.exe
+
+ oe_runmake install_headers INSTALL_HDR_PATH=${D}${includedir}/vcu-ctrl-sw/include
+ oe_libinstall -C ${S}/bin/ -so liballegro_decode ${D}/${libdir}/
+ oe_libinstall -C ${S}/bin/ -so liballegro_encode ${D}/${libdir}/
+}
+
+# These libraries shouldn't get installed in world builds unless something
+# explicitly depends upon them.
+
+EXCLUDE_FROM_WORLD = "1"
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/vcu-firmware.bb b/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/vcu-firmware.bb
new file mode 100644
index 0000000..1cb2125
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-multimedia/vcu/vcu-firmware.bb
@@ -0,0 +1,40 @@
+SUMMARY = "Firmware for VCU"
+DESCRIPTION = "Firmware binaries provider for VCU"
+LICENSE = "Proprietary"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=63b45903a9a50120df488435f03cf498"
+
+XILINX_VCU_VERSION = "1.0.0"
+XILINX_RELEASE_VERSION = "2018.1"
+PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}"
+
+S = "${WORKDIR}/git"
+
+BRANCH ?= "master"
+REPO ?= "git://github.com/xilinx/vcu-firmware.git;protocol=https"
+SRCREV ?= "7c6f282da07253c1987665846ed676059925ef40"
+
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE_zynqmp = "zynqmp"
+
+PACKAGE_ARCH = "${SOC_FAMILY}"
+
+do_install() {
+ install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5d_b.fw ${D}/lib/firmware/al5d_b.fw
+ install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5d.fw ${D}/lib/firmware/al5d.fw
+ install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5e_b.fw ${D}/lib/firmware/al5e_b.fw
+ install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5e.fw ${D}/lib/firmware/al5e.fw
+}
+
+# Inhibit warnings about files being stripped
+INHIBIT_PACKAGE_DEBUG_SPLIT = "1"
+INHIBIT_PACKAGE_STRIP = "1"
+FILES_${PN} = "/lib/firmware/*"
+
+# These libraries shouldn't get installed in world builds unless something
+# explicitly depends upon them.
+EXCLUDE_FROM_WORLD = "1"
+
+INSANE_SKIP_${PN} = "ldflags"