{
    "name": "p10bmc",
    "version": "A3",
    "data_region": {
        "patch": true,
        "ecc_region": true,
        "key": [
            {
                "types": "rsa_pub_oem",
                "key_pem": "rsa_pub_oem_dss_key.pem",
                "offset": "0x40",
                "number_id": 0,
                "sha_mode": "SHA512"
            },
            {
                "types": "rsa_pub_oem",
                "key_pem": "P10BMCAspeedSBPubKey_2.pem",
                "offset": "0x240",
                "number_id": 1,
                "sha_mode": "SHA512"
            },
            {
                "types": "rsa_pub_oem",
                "key_pem": "P10BMCAspeedSBPubKey_3.pem",
                "offset": "0x440",
                "number_id": 2,
                "sha_mode": "SHA512"
            }
        ],
        "user_data": [
            {
                "types": "dw_hex",
                "file": "emmc_patch.hex",
                "offset": "0x1B80"
            }
        ]
    },
    "config_region": {
        "Disable OTP Memory BIST Mode":                 true,
        "Enable Secure Boot":                           false,
        "User region ECC enable":                       true,
        "Secure Region ECC enable":                     false,
        "Disable low security key":                     false,
        "Ignore Secure Boot hardware strap":            false,
        "Secure Boot Mode":                             "Mode_2",
        "Disable Uart Message of ROM code":             false,
        "Secure crypto RSA length":                     "RSA4096",
        "Hash mode":                                    "SHA512",
        "Disable patch code":                           false,
        "Disable Boot from Uart":                       false,
        "Secure Region size":                           "0x0",
        "Write Protect: Secure Region":                 true,
        "Write Protect: User region":                   true,
        "Write Protect: Configure region":              true,
        "Write Protect: OTP strap region":              true,
        "Copy Boot Image to Internal SRAM":             true,
        "Enable image encryption":                      false,
        "Enable write Protect of OTP key retire bits":  false,
        "Disable Auto Boot from UART or VUART":         false,
        "OTP memory lock enable":                       false,
        "Key Revision":                                 "0x0",
        "Secure boot header offset":                    "0x0",
        "Boot From UART Port Selection":                "UART5",
        "Disable Auto Boot from UART":                  false,
        "Disable Auto Boot from VUART2 over PCIE":      true,
        "Disable Auto Boot from VUART2 over LPC":       true,
        "Disable ROM code based programming control":   true,
        "Rollback prevention shift bit number":         "0x0",
        "Extra Data Write Protection Region Size":      "0x0",
        "Erase signature data after secure boot check": false,
        "Erase RSA public key after secure boot check": false,
        "User define data: random number low":          "0x0",
        "User define data: random number high":         "0x0",
        "Manifest ID":                                  "0x0",
        "Patch code location":                          "0x6E0",
        "Patch code size":                              "0x18"
    },
    "otp_strap": {
        "Enable secure boot":                           { "value": false },
        "Enable boot from eMMC":                        { "value": true },
        "Boot from debug SPI":                          { "value": false },
        "Disable ARM CM3":                              { "value": true },
        "Enable dedicated VGA BIOS ROM":                { "value": false },
        "MAC 1 RMII mode":                              { "value": "RMII/NCSI" },
        "MAC 2 RMII mode":                              { "value": "RMII/NCSI" },
        "CPU frequency":                                { "value": "1.2GHz" },
        "HCLK ratio":                                   { "value": "default" },
        "VGA memory size":                              { "value": "16MB" },
        "CPU/AXI clock ratio":                          { "value": "2:1" },
        "Disable ARM JTAG debug":                       { "value": true },
        "VGA class code":                               { "value": "vga_device" },
        "Disable debug 0":                              { "value": false },
        "Boot from eMMC speed mode":                    { "value": "normal" },
        "Enable PCIe EHCI":                             { "value": false },
        "Disable ARM JTAG trust world debug":           { "value": true },
        "Disable dedicated BMC function":               { "value": false },
        "Enable dedicate PCIe RC reset":                { "value": false },
        "Disable watchdog to reset full chip":          { "value": false },
        "Internal bridge speed selection":              { "value": "1x" },
        "Disable RVAS function":                        { "value": false },
        "MAC 3 RMII mode":                              { "value": "RMII/NCSI" },
        "MAC 4 RMII mode":                              { "value": "RMII/NCSI" },
        "SuperIO configuration address selection":      { "value": "0x2e" },
        "Disable LPC to decode SuperIO":                { "value": true },
        "Disable debug 1":                              { "value": false },
        "Enable ACPI":                                  { "value": false },
        "Select LPC/eSPI":                              { "value": "LPC" },
        "Enable SAFS":                                  { "value": false },
        "Enable boot from uart5":                       { "value": false },
        "Enable boot SPI 3B address mode auto-clear":   { "value": false },
        "Enable SPI 3B/4B address mode auto detection": { "value": false },
        "Enable boot SPI or eMMC ABR":                  { "value": true },
        "Boot SPI ABR Mode":                            { "value": "dual" },
        "Boot SPI flash size":                          { "value": "0" },
        "Enable host SPI ABR":                          { "value": false },
        "Enable host SPI ABR mode select pin":          { "value": false },
        "Host SPI ABR Mode":                            { "value": "dual" },
        "Host SPI flash size":                          { "value": "0" },
        "Enable boot SPI auxiliary control pins":       { "value": false },
        "Boot SPI CRTM size":                           { "value": "0" },
        "Host SPI CRTM size":                           { "value": "0" },
        "Enable host SPI auxiliary control pins":       { "value": false },
        "Enable GPIO Pass Through":                     { "value": false },
        "Enable Dedicate GPIO Strap Pins":              { "value": false }
    }
}