tree 88d629d5b0030952f7ef2a81326ba71be2ceeeb2
parent 265bd49e0929631e54770326f7bab7fd013a71ca
author Tim Lee <timlee660101@gmail.com> 1687935724 +0800
committer Tim Lee <chli30@nuvoton.com> 1688442629 +0000

meta-nuvoton: npcm8xx-igps: update to 03.09.01

Changelog:

IGPS 03.09.01 - Jun 26th 2023
==============
- TIP FW 0.6.0 L0 0.4.9 L1
  * New memory map. TIP_VIRTUAL_FLASH_BASE_ADDR moved to 0x1000000.
  * Fix NVIC_TrapHandlerCommon: uart reconfig should be after
    sampling
    core registers.
  * Fix DRAM window handling bug, in order to allow loading images to
    any address in DRAM.
  * In recovery mode: add an option to go to halt
    (print "N" at the start).
  * Add the support for enforcing recovery image to match
    active at boot time
  * Add support for ECC 384 + 521
  * Add the support of ecc HW with tip_ecc_hw_ncl.c instead of old
    implementation using mbedtls code
  * Wake all 4 cores when jump to DRAM
    (feature was limited to RAM2 only).
  * Bug fix SFDP dummy byte.

- Remove no_tip file from ReplaceComponent.bat

- uboot:
  New memory map.

- bl31: Release V2.8.2
  * change load address of BL31 to 0x02000000
  * change load address of OPTEE-OS to 0x02100000
  * change load address of BL33 to 0x06208000

- optee: Release npcm845x_3.18.0_v1.0-697
  * change load address of OPTEE-OS from to 0x02100000

- bootblock 0.3.3
  * Add header field GMMAP at offset 0x152 which is copied to
    INTCR4.GMMAP0 and 1.

- XML: add bootblock field to select GMMAP. Default is zero.
  If it's FF value is set as before by bootblock, according to DRAM
  size.

- XML: bootblock sets MC to 1050MHz by default.

- Bug fix in Open_all_ports batch.

Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I7ae7eb915530397e1a1a3f26a766e208e02c25c1