meta-openembedded and poky: subtree updates

Squash of the following due to dependencies among them
and OpenBMC changes:

meta-openembedded: subtree update:d0748372d2..9201611135
meta-openembedded: subtree update:9201611135..17fd382f34
poky: subtree update:9052e5b32a..2e11d97b6c
poky: subtree update:2e11d97b6c..a8544811d7

The change log was too large for the jenkins plugin
to handle therefore it has been removed. Here is
the first and last commit of each subtree:

meta-openembedded:d0748372d2
      cppzmq: bump to version 4.6.0
meta-openembedded:17fd382f34
      mpv: Remove X11 dependency
poky:9052e5b32a
      package_ipk: Remove pointless comment to trigger rebuild
poky:a8544811d7
      pbzip2: Fix license warning

Change-Id: If0fc6c37629642ee207a4ca2f7aa501a2c673cd6
Signed-off-by: Andrew Geissler <geissonator@yahoo.com>
diff --git a/meta-openembedded/meta-oe/recipes-devtools/android-tools/android-tools/core/0013-adb-Support-riscv64.patch b/meta-openembedded/meta-oe/recipes-devtools/android-tools/android-tools/core/0013-adb-Support-riscv64.patch
new file mode 100644
index 0000000..a8434af
--- /dev/null
+++ b/meta-openembedded/meta-oe/recipes-devtools/android-tools/android-tools/core/0013-adb-Support-riscv64.patch
@@ -0,0 +1,189 @@
+From 48ddf4fb999931942c359350fb31cd557514e1c6 Mon Sep 17 00:00:00 2001
+From: Chenxi Mao <maochenxi@eswin.com>
+Date: Mon, 20 Apr 2020 15:27:22 +0800
+Subject: [PATCH 1/1] adb: Support riscv64
+
+---
+ include/cutils/atomic-inline.h  |   2 +
+ include/cutils/atomic-riscv64.h | 156 ++++++++++++++++++++++++++++++++
+ 2 files changed, 158 insertions(+)
+ create mode 100644 include/cutils/atomic-riscv64.h
+
+diff --git a/include/cutils/atomic-inline.h b/include/cutils/atomic-inline.h
+index a31e913579..b5dc38209c 100644
+--- a/include/cutils/atomic-inline.h
++++ b/include/cutils/atomic-inline.h
+@@ -55,6 +55,8 @@ extern "C" {
+ #include <cutils/atomic-mips64.h>
+ #elif defined(__mips__)
+ #include <cutils/atomic-mips.h>
++#elif defined(__riscv) && __riscv_xlen == 64
++#include <cutils/atomic-riscv64.h>
+ #else
+ #error atomic operations are unsupported
+ #endif
+diff --git a/include/cutils/atomic-riscv64.h b/include/cutils/atomic-riscv64.h
+new file mode 100644
+index 0000000000..2664db5a86
+--- /dev/null
++++ b/include/cutils/atomic-riscv64.h
+@@ -0,0 +1,156 @@
++/*
++ * Copyright (C) 2014 The Android Open Source Project
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions
++ * are met:
++ *  * Redistributions of source code must retain the above copyright
++ *    notice, this list of conditions and the following disclaimer.
++ *  * Redistributions in binary form must reproduce the above copyright
++ *    notice, this list of conditions and the following disclaimer in
++ *    the documentation and/or other materials provided with the
++ *    distribution.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
++ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
++ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
++ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
++ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
++ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
++ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
++ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
++ * SUCH DAMAGE.
++ */
++
++#ifndef ANDROID_CUTILS_ATOMIC_RISCV64_H
++#define ANDROID_CUTILS_ATOMIC_RISCV64_H
++
++#include <stdint.h>
++
++#ifndef ANDROID_ATOMIC_INLINE
++#define ANDROID_ATOMIC_INLINE inline __attribute__((always_inline))
++#endif
++
++/*
++   TODOAArch64: Revisit the below functions and check for potential
++   optimizations using assembly code or otherwise.
++*/
++
++extern ANDROID_ATOMIC_INLINE
++void android_compiler_barrier(void)
++{
++    __asm__ __volatile__ ("" : : : "memory");
++}
++
++extern ANDROID_ATOMIC_INLINE
++void android_memory_barrier(void)
++{
++    __asm__ __volatile__ ("fence rw,rw" : : : "memory");
++}
++
++extern ANDROID_ATOMIC_INLINE
++int32_t android_atomic_acquire_load(volatile const int32_t *ptr)
++{
++    int32_t value = *ptr;
++    android_memory_barrier();
++    return value;
++}
++
++extern ANDROID_ATOMIC_INLINE
++int32_t android_atomic_release_load(volatile const int32_t *ptr)
++{
++    android_memory_barrier();
++    return *ptr;
++}
++
++extern ANDROID_ATOMIC_INLINE
++void android_atomic_acquire_store(int32_t value, volatile int32_t *ptr)
++{
++    *ptr = value;
++    android_memory_barrier();
++}
++
++extern ANDROID_ATOMIC_INLINE
++void android_atomic_release_store(int32_t value, volatile int32_t *ptr)
++{
++    android_memory_barrier();
++    *ptr = value;
++}
++
++extern ANDROID_ATOMIC_INLINE
++int android_atomic_cas(int32_t old_value, int32_t new_value,
++                       volatile int32_t *ptr)
++{
++    return __sync_val_compare_and_swap(ptr, old_value, new_value) != old_value;
++}
++
++extern ANDROID_ATOMIC_INLINE
++int android_atomic_acquire_cas(int32_t old_value, int32_t new_value,
++                               volatile int32_t *ptr)
++{
++    int status = android_atomic_cas(old_value, new_value, ptr);
++    android_memory_barrier();
++    return status;
++}
++
++extern ANDROID_ATOMIC_INLINE
++int android_atomic_release_cas(int32_t old_value, int32_t new_value,
++                               volatile int32_t *ptr)
++{
++    android_memory_barrier();
++    return android_atomic_cas(old_value, new_value, ptr);
++}
++
++extern ANDROID_ATOMIC_INLINE
++int32_t android_atomic_add(int32_t increment, volatile int32_t *ptr)
++{
++    int32_t prev, status;
++    android_memory_barrier();
++    do {
++        prev = *ptr;
++        status = android_atomic_cas(prev, prev + increment, ptr);
++    } while (__builtin_expect(status != 0, 0));
++    return prev;
++}
++
++extern ANDROID_ATOMIC_INLINE
++int32_t android_atomic_inc(volatile int32_t *addr)
++{
++    return android_atomic_add(1, addr);
++}
++
++extern ANDROID_ATOMIC_INLINE
++int32_t android_atomic_dec(volatile int32_t *addr)
++{
++    return android_atomic_add(-1, addr);
++}
++
++extern ANDROID_ATOMIC_INLINE
++int32_t android_atomic_and(int32_t value, volatile int32_t *ptr)
++{
++    int32_t prev, status;
++    android_memory_barrier();
++    do {
++        prev = *ptr;
++        status = android_atomic_cas(prev, prev & value, ptr);
++    } while (__builtin_expect(status != 0, 0));
++    return prev;
++}
++
++extern ANDROID_ATOMIC_INLINE
++int32_t android_atomic_or(int32_t value, volatile int32_t *ptr)
++{
++    int32_t prev, status;
++    android_memory_barrier();
++    do {
++        prev = *ptr;
++        status = android_atomic_cas(prev, prev | value, ptr);
++    } while (__builtin_expect(status != 0, 0));
++    return prev;
++}
++
++#endif /* ANDROID_CUTILS_ATOMIC_RISCV_H */
+-- 
+2.17.1
+