meta-xilinx: subtree update:757bac706c..bef2bf9b15
Alejandro Enedino Hernandez Samaniego (76):
libmali-xlnx: Use update-alternatives to switch between GL backends
libmali-xlnx: modify REQUIRED_DISTRO_FEATURES
libmali-xlnx: only use and install dependencies that the DISTRO supports
libmali-xlnx: fix x11 headers
libmali-xlnx: Dont provide KHR headers
libmali-xlnx: Change version on gbm.pc to be compatible with mesa
libmali-xlnx: modify version on egl.pc for compatibility
run-postinsts: Pass the output of the scripts run to kmsg
zynqmp-pmu.conf: Upgrade tune to use Microblaze v10.0
zynqmp-pmu.conf: Update to Microblaze v11.0
newlib: export CC_FOR_TARGET as CC
gcc-cross: Dont override EXTRA_OECONF unless DISTRO is xilinx-standalone
Adds MACHINE.conf containing default tune for Cortex R5
Adds MACHINE.conf containing default tune for Cortex A53
toolchain: Provide specific configuration for cross(-canadian) gcc and binutils
Adds MACHINE.conf containing default tune for Cortex A72
xilinx-standalone: switch override and append
xilinx-standalone: Add staticdev packages for newlib and libgloss to dependencies
xilinx-standalone: Reorganize toolchain configure options
toolchain: add cortex-A9 options for gcc and binutils
gcc-cross-microblazeel: disable multilib
gcc: Separate binutils options
gcc: Add multilib-list=aprofile configure option for cortex A9
gcc-runtime: Enable bulding libsdtc++ for baremetal applications
gcc-runtime: Set correct overrides now that the build has been fixed in oe-core
gcc-xilinx-standalone: Enable multilib builds for baremetal microblaze
gcc-microblaze: Remove multilib builds that arent working (m64)
meta-xilinx-standalone: Restructure layer properly, gcc and binutils belong on recipes-devtools
newlib: Keep version numbers on bbappends
meta-xilinx-standalone: Restructure layer properly, newlib belongs to recipes-bsp
gcc-runtime: Move gcc-runtime to GCCs directory
layer.conf: Include recipe files from a pattern with no directory required
Create machines that use SOC_FAMILY
Microblaze-pmu: Change overrides to reflect machine name changes from zynqmp-pmu to microblaze-pmu
cortexr5: Change overrides to reflect machine name changes from cortexr5 to zynqmp and versal variants
cortexa72: To keep up with a standard rename cortexa72 to add its SOC_FAMILY to its name
meta-xilinx-bsp: Unify machine confs
cortexr5-versal.conf: Include the tune inc file from the correct path
cortexr5-zynqmp.conf: Include the tune inc file from the correct path
tune-cortexrm: Include PACKAGE_EXTRA_ARCHS to avoid parsing errors
esw: first step to move everything into an embeddedsw class
pmufw: Install and hence package and strip the pmufw elf file
fix license and compatible host for now
pmufw: fix filename on elf file and fix task order to get stripped elf file deployed
libxil: add flow for a53 using dtg
device-tree.bbappend: add appent to support cortexa53 MACHINE
device-tree: switch to AUTOREV to keep up with the repo changes for now
zynqmp-fsbl: Sync flow with pmufw
libxil: fix device tree flags for a53
libxil: Fix DTB and DTG flow to make it more transparent for the user
Fix XILINX_RELEASE_VERSION
Increase layer priority
device-tree: the Flags used from device tree have to be set on the device tree recipe, not in the libxil one
esw.bbclass: Fix devtool and externalsrc flow
esw.bbclass: Install artifacts from the build directory vs WORKDIR
pmufw: Install artifacts from the build directory vs WORKDIR
esw.bbclass: Make it possible for packages to use the cmake ncurses gui
libxil: Unify flow and get DTB using the device-tree recipe instead of creating it manually
SOC_FAMILY: Change overrides
Microblaze-pmu: Change overrides to reflect machine name chanches from zynqmp-pmu to microblaze-pmu
device-tree: Install psu_init files as well
fsbl: avoid using underscore in the directory filename
meta-xilinx-standalone: Restructure layer properly, pmufw and fsbl belong on recipes-applications
meta-xilinx-standalone: device-tree belongs on recipes-bsp
meta-xilinx-standalone: Restructure layer properly, move existing libraries from decoupling to recipes-libraries
zynqmp-fsbl: Fix race condition on copy_psu_init
device-tree: Fix install directory
meta-xilinx-standalone: clean up layer
libraries: Add inherit on python3native on libraries that were invoking nativepython3
meta-xilinx: Include templates for local.conf and bblayers.conf
esw: fix machines that have been renamed
libgloss: Dont install libgloss as libxil since we actually have libxil
esw: Switch release version to 2020.1
xilinx-standalone: Add buildhistory to the DISTRO to avoid cooker errors
device-tree: Override repo for supported machines
system-zcu102: Create heterogeneous machine configuration for ZCU102 evaluation board.
Anirudha Sarangi (4):
meta-xilinx-standalone: conf: distro: Add new distro for freertos
meta-xilinx-standalone: classes: Update CMAKE_SYSTEM_NAME for Freertos
meta-xilinx-standalone: recipes-libraries: Add recipe for freertos
meta-xilinx-standalone: recipes-applications: freertos-hello-world: Add recipe for freertos hello world
Appana Durga Kedareswara rao (82):
libxil: Add recipes for libxil and xilstandalone
pmufw: recipes for pmufw app generation in decoupled flow
Add recipes for xilffs and xilpm libraries
Add recipes for building zynqmp fsbl application
meta-xilinx-standalone: Add support for PLM and dependent library recipes
zynqmp-fsbl: Copy psu_init files to source code
meta-xilinx: meta-xilinx-standalone: Update source url path
meta-xilinx: meta-xilinx-standalone: comment flto flags by default
meta-xilinx-standalone: Using S instead of WORKDIR
meta-xilinx-standalone: classes: Add bbclass for building esw examples
meta-xilinx-standalone: recipes-drivers: Add recipe for compiling csudma driver examples
meta-xilinx-standalone: recipes-drivers: Add recipe for compiling emacps driver examples
meta-xilinx-standalone: recipes-drivers: Add recipe for compiling axiethernet driver examples
meta-xilinx-standalone: recipes-drivers: Add recipe for compiling axicdma driver examples
meta-xilinx-standalone: recipes-drivers: Add recipe for compiling axidma driver examples
meta-xilinx-standalone: recipes-drivers: Add recipe for compiling llfifo driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling mcdma driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling zdma driver examples
meta-xilinx-standalone: recipes-applications: Add recipe for compiling hello world application
meta-xilinx-standalone: classes: Update md5 checksum as per latest license
meta-xilinx-standalone: Add support for cortexa72 processor
meta-xilinx-standalone: recipes-libraries: xilstandalone: Cleanup the recipe
meta-xilinx-standalone: recipes-libraries: libxil: Cleanup the recipe
meta-xilinx-standalone: classes: cleanup the class
meta-xilinx-standalone: recipes-applications: hello-world: Remove dependency on esw_examples class
meta-xilinx-standalone: recipes-libraries: Add recipe for xilmailbox
cortexa72: Update cortexa72 machine variable naming
meta-xilinx: Add support for cortexr5 processor
meta-xilinx-standalone: Add dependencies on python3-dtc-native
meta-xilinx-standalone: recipes-libraries: xiltimer: Add task for generating cmake meta-data
meta-xilinx-standalone: recipes-libraries: lwip: Add recipe for lwip
meta-xilinx-standalone: recipes-applications: lwip-echo-server: Add recipe for compiling lwip echo server application
meta-xilinx-standalone: Add support for versal cortexr5 processor
meta-xilinx-standalone: recipes-applications: lwip-tcp-perf-client: Add recipe for compiling lwip tcp perf client application
meta-xilinx-standalone: recipes-applications: lwip-tcp-perf-server: Add recipe for compiling lwip tcp perf server application
meta-xilinx-standalone: recipes-applications: lwip-udp-perf-server: Add recipe for compiling lwip udp perf server application
meta-xilinx-standalone: recipes-applications: lwip-udp-perf-client: Add recipe for compiling lwip udp perf client application
meta-xilinx-standalone: recipes-applications: freertos-lwip-echo-server: Add recipe for compiling freertos lwip echo server application
meta-xilinx-standalone: recipes-applications: freertos-lwip-tcp-perf-client: Add recipe for compiling freertos lwip tcp perf client application
meta-xilinx-standalone: recipes-applications: freertos-lwip-tcp-perf-server: Add recipe for compiling freertos lwip tcp perf server application
meta-xilinx-standalone: recipes-applications: freertos-lwip-udp-perf-client: Add recipe for compiling freertos lwip udp perf client application
meta-xilinx-standalone: recipes-applications: freertos-lwip-udp-perf-server: Add recipe for compiling freertos lwip udp perf server application
meta-xilinx-standalone: recipes-libraries: Update depends list for socket mode
meta-xilinx-standalone: recipes-libraries: Add recipe for xilpuf
meta-xilinx-standalone: recipes-libraries: Fix workarounds
meta-xilinx-standalone: recipes-libraries: xilloader: Update depends list
meta-xilinx-standalone: recipes-applications: freertos-hello-world: Fix do_deploy elf variable name
meta-xilinx-standalone: classes: esw: Remove unneeded DISTRO check
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling dmaps driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling usbpsu driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling axivdma driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling emaclite driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling xxvethernet driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling scugic driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling ttcps driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling tmrctr driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling qspipsu driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling ospipsv driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling resetps driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling clockps driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling canfd driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling canps driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling can driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling wdtps driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling rtcpsu driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling gpiops driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling sdps driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling ipipsu driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling nandpsu driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling devcfg driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling mbox driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling mutex driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling uartlite driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling uartps driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling gpio driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling spips driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling qspips driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling xadcps driver examples
meta-xilinx-standalone: recipe-drivers: Add recipe for compiling sysmon driver examples
device-tree: Install psu_init files as well for zynqmp machines
meta-xilinx-standalone: recipes-applications: zynqmp-fsbl: Correct cflags based on the machine type
meta-xilinx-standalone: recipes-bsp: device-tree: Install psu_init* files only for standalone configuration
Bruce Ashfield (1):
linux-xlnx: cleanup and make yocto-kernel-cache available
Himanshu Choudhary (8):
xrt_git:zocl_git: added package_class for generating rpm
zocl_git: added post install script
xrt_git: added veral flags and dependencies
xrt_git:zocl_git: license and PV update from meta-xilinx-internal
xrt,zocl:Update commit id for 2020.1 release
xrt_git:zocl_git: updated commitid > CR-1063204
xrt_git:zocl_git: update commitid for 2020.1 release
xrt_git:zocl_git: update commitid for 2020.1 release
Jaewon Lee (28):
Update recipes for 2019.2 release
u-boot-zynq-scr: reworking boot.scr recipe to work for zynq and zynqmp
u-boot-zynq-scr: Setting sd as default bootmode for versal
zynq/zynqmp confs: Adding boot.scr to IMAGE_BOOT_FILES
bootgen_1.0.bb: Adding initial bootgen recipe to build bootgen
flashstrip utility: Build and ship flash strip utility needed for qemu
machine-xilinx-default.inc: Adding required dependencies to image_wic
**TEMPORARY**: Removing preferred provider overrides for mali backend
meson: Adding patch to add microblaze as supported CPU
glibc-locale_%.bbappend: Fix directory installed but not shipped issue
Revert "**TEMPORARY**: Removing preferred provider overrides for mali backend"
arm-trusted-firmware.inc: Changing generic DEBUG to DEBUG_ATF
gcc-cross-canadian_%.bbappend:temporary hack to build gcc cross canadian
gcc-source: Adding microblaze patch to fix compiler crash with -freg-struct-return
newlib: Adding xilinx specific patches on top of newlib/libgloss 3.1.0
cortexa*.conf: Change arch-armv8.inc to arch-armv8a.inc
gdb: Switching microblaze to use upstream gdb version 8.3.1
microblaze gdb/binutils: Adding necessary patches for microblaze
Using tune-cortexa72-cortexa53.inc for versal and zynqmp tunes
qemu-system-aarch64-multiarch: Adding comment for future fix
xilinx-standalone.conf: Adding qemu to TOOLCHAIN_HOST_TASK
arm-trusted-firmware.inc: installing elf with standard name
u-boot-xlnx:Updating defconfig for all zynq machines
Correcting ':' placement for appending file paths
Add older version of OpenCV 3.4.3
opencv_3.4.3.bb: Removing tiny-dnn from SRC_URI
versal confs: Upping RAM in runqemu command to 8G for versal boards
versal confs: cleaning up unnecessary file loading in runqemu command
Jean-Francois Dagenais (3):
libmali-xlnx: clean and fix FILESXTRAPATHS
libmali-xlnx: make version recognizable
kernel-module-mali: add patch to check dma_map_page error
Jeegar Patel (1):
kernel-module-vcu.bb : Autoload dmaproxy module on boot
Madhurkiran Harikrishnan (14):
libmali-xlnx: MALI will not provide wayland-egl
libmali-xlnx.bb: ABIs are made consistent for all backends
libmali-xlnx: Squash all monolithic library name into a variable
libmali-xlnx: Upgrade the userspace driver to r9p0
kernel-module-mali: Upgrade the kernel space driver to r9p0
weston: Migrate ZynqMP specific patches for weston to meta-xilinx
weston: Remove opaque substitute for ARGB8888 as ZynqMP DP does not support
kernel-module-mali: Make the driver compatible with kernel 5.4
Revert "libmali-xlnx: Dont provide KHR headers"
mesa: Do not provide KHR headers
cairo: For ZynqMP enable glesv2 packageconfig
libglu: Add build time dependency on glesv2 for zynqmp
xf86-video-armsoc: Bypass the exa layer to free the root pixmap
libmali: Fetch mali binaries from rel-v2020.1 branch
Manjukumar Matha (17):
libmali-xlnx: upgrade MALI recipe for 2019.2
xrt_git.bb: Fix xrt recipe for externalsrc
zocl_git.bb: Update the S path for zocl
kernel-module-hdmi_git.bb: New Yocto recipe for Xilinx HDMI drivers
machine-xilinx-default.inc: Add qemu-xilinx-helper-native as preferred provider
zynq-generic.conf: Add qemu wiring to generic conf
meta-xilinx-pynq: Add layer to support PYNQ
image-types-xilinx-qemu.bbclass: Add sector size as 512K
ultra96-zynqmp.conf: Add support for Ultra96 evaluation board
linux-firmware_git.bbappend: Add hook for wl18xx and bts file
vc-p-a2197-00-versal.conf:Add versal Tenzing +SE1 board configuration
kc705-microblaze: Update u-boot patch for kc705
layer.conf: Update XILINX_RELEASE_VERSION to v2020.1
libgpg-error: Add microblaze platform specific gpg-error.h file
qemu-xilinx-native: Enable packageconfig option for libgcrypt
qemu-xilinx.inc: Remove stale packageconfig options
qemu-xilinx.inc: Configure qemu-xilinx with gcrypt
Mark Hatle (82):
binutils/gcc: Refactor the oeconf
Revert "binutils/gcc: Refactor the oeconf"
gcc-runtime: Make the baremetal changes specific to class-target
binutils/gcc: Refactor the oeconf
gcc: Remove cortexa53 errata fixes
binutils: Merge latest binutils work
Revert "gcc-microblaze: Remove multilib builds that arent working (m64)"
gcc-cross-canadian: Fix issue being unable to find stdio.h
Enable multilib baremetal toolchains
gcc-runtime: Fix C++ multilib headers
Limit multilib toolchains to symlinks to the main toolchain
Create new baremetal toolchain machines
Fix arm cortex r/m profiles
microblaze-tc: Minor update and corrections
Adjust the microblaze standalone toolchain to match vitis expectations.
newlib: Adjust configuration for standalone to allow BSP library
qemu-xilinx: Point to master branch by default
distro/xilinx-standalone: Make LTO optional
distr/xilinx-standalone: Switch default optimization from ESW to Distro
cortex-r5: Add cortexr5f configuration
xilinx-standalone: When building for cortexr5, add -DARMR5 for CCARGS
newlib: Move microblaze support
newlib: Cleanup and merge the two newlib bbappends into a single append
python3-dtc: Add python3 dtc module
Ensure that bbappends do not affect task hashes
xlnx-compatible-os.bbclass: Class to allow recipes to list OS compatibility
Remove hardcoded XILINX_RELEASE_VERSION in recipes
meta-xilinx-standalone: Add dependencies on python3-dtc
meta-xilinx-standalone/device-tree: remove duplicate internal references
lopper: Add lopper utility
xilinx-standalone: sync distros
xilinx-standalone.inc: Replace qemu dependency with mingw32 specific recipe
lopper: Add runtime dependency of python3-dtc
cortexa53-zynqmp/cortexa72-versal: Fix cortex based BSPs
README.md: revise README.md based
README.md: Add information about the new embeddedsw support
microblaze_dtb.py: Convert a dtb to one or more microblaze TUNE_FEATURES
linux-xlnx: Use new default defconfigs
meta-xilinx-bsp: Rename soc configuration masquerading as a tune file
meta-xilinx-bsp: Remove default values
machine-xilinx-overrides: Make this generic
meta-xilinx-bsp: Update recipes to use SOC_FAMILY_ARCH and SOC_VARIANT_ARCH
meta-xilinx-bsp: rename machine-xilinx-override to xilinx-soc-family.inc
meta-xilinx-standalone: Move soc overrides from meta-xilinx-default
meta-xilinx-bsp: Adjust soc to permit multiple CPU/TUNES
libmali-xlnx: Remove virtual provides
meta-xilinx-bsp: remove redundant PREFERRED_PROVIDER
Revert "libmali-xlnx: Remove virtual provides"
meta-xilinx-bsp: machine-xilinx-default.inc allow empty WIC_DEPENDS
microblaze_dtb.py: Move to scripts subdir
zc706-zynq7: Add qemu wiring for zc706 machine
qemu-zynq7: Add qemu wiring for zc706 machine
meta-xilinx-bsp: cleanup qemu references
xilinx-qemu: Move -multiarch extension to the machine-xilinx-qemu
*-generic.conf: Add QEMU support to each of the generic BSPs
versal-generic: Move from vck190 to vc-p-a2197-00-versal
esw.bbclass: Adjust get_xlnx_cmake_process to use both tune and machine
Revise COMPATIBLE_MACHINE settings
esw.bbclass: Move DTBFILE to a single definition
xilinx-standalone.conf: Add workaround for microblaze -Os bug
Revert "linux-xlnx: Use new default defconfigs"
qemu-xilinx.inc: Move the URL to 'gitsm' and disable compile time submodules
esw.bbclass: Only work with xilinx-standalone distro
Rename plm_git.bb to plm-standalong_git.bb
meta-xilinx-standalone esw.bbclass: Allow SRCREV and SRC_URI to be overwritten
esw.bbclass: Change 'or' to 'and' to verify EXTERNALSRC is defined
Revert "xlnx-compatible-os.bbclass: Class to allow recipes to list OS compatibility"
Define COMPATIBLE_HOST to prevent mix of Linux and Baremetal recipes
device-tree.bbappend: Move to COMPATIBLE_HOST
machines: Move from SERIAL_CONSOLE (deprecated) to SERIAL_CONSOLES
machines: Move from SERIAL_CONSOLE (deprecated) to SERIAL_CONSOLES
machines: Allow the user to override SERIAL_CONSOLES
machines: Remove default SERIAL_CONSOLES_CHECK
machines: Allow user to override SERIAL_CONSOLE
microblaze machines: Set LINKER_HASH_STYLE defaults
kernel-module-mali: WIP
libcma: Fix SRC_URI definition
binutils: Microblaze integrate fix from upstream
init-ifupdown: Fix BSPs that were setting partial overrides
zynq-generic.conf: Remove the qemu overrides, not needed
meta-xilinx-standalone gcc: Fix microblaze crtend.o
lopper: Fix python3 reference in lopper_sanity.py
Min Ma (1):
xrt_git.bb: update XRT dependency
Mubin Usman Sayyed (3):
meta-xilinx-bsp: conf: machine: Add standalone based machine for zynq
meta-xilinx-standalone: Add support for zynq
meta-xilinx-standalone: classes: esw: Update ESW_CFLAGS with spec file
Mukund PVVN (3):
zcu1275-zynqmp.conf: Rename zc1275 to zcu1275
zcu1285-zynqmp.conf: Update UBOOT_MACHINE
v350-versal.conf:Add versal board configuration
Peter Ogden (1):
python3-pynq.bb: Update PYNQ to 2.5.1
Sai Hari Chandana Kalluri (54):
u-boot-xlnx_2019.2.bb: Rename zc1275 to zcu1275 board name
ultra96-zynqmp.conf: Include mipi as MACHINE_FEATURE
linux-xlnx.inc: Add MIPI kernel configuration for Ultra96
pynq-ultra96-*: Add Ultra96 specific pynq example demo:
vck-sc-zynqmp: Machine configuration for vck190 system controller
v350-versal.conf: Enforce system.dtb name when using virtual/dtb
vmk180-versal.conf: Add machine configuration for vmk180-versal
tune-versal.inc: Set default SOC_VARIANT = s80
arm-trusted-firmware_2019.2.bbappend: Update compilation flag
u-boot-xlnx: Add the platform init file for zcu216-zynqmp
plm_2019.2.bb: recipe to build plm standalone
psm-firmware_2019.2.bb: Create psm-firmware recipe for standalone build
versal-mb.conf: Add machine configuration to support standalone build for versal components like plm, psm-firmware
vck190-versal.conf: Add deploy dir for psm and plm firmware
tune-versal.inc: Rename include file from arch-armv8 to arch-armv8a
Move recipes to use _%.bb instead of version
qemu-*: Upgrade QEMU version 2.11 -> 4.1.5
Upgrade recipes to 2020.1
libmali-xlnx: Provide single shlib provider for libMali.so.9
"**TEMPORARY**" linux-xlnx.inc: Trim PV variable expansion
Revert "Revert "**TEMPORARY**: Removing preferred provider overrides for mali backend""
versal-generic: Add versal-generic machine configuration
Revert "**TEMPORARY**: Removing preferred provider overrides for mali backend"""
qemu-xilinx*: Enable qemu-xilinx-native as PROVIDER for qemu-native
u-boot-zyqn-scr.bb: Update DEVICETREE and KERNEL LOAD ADDRESS for zynqmp machines
u-boot-xlnx:Update UBOOT-MACHINE to xilinx_zynqmp_virt_defconfig for all zynqmp machines
qemu-xilinx: Enable qemu-xilinx to provide nativesdk-qemu
zedboard-zynq7.conf:update u-boot binary name
qemu-system-aarch64-multiarch: Update the binpath for qemu targets
zcu102-zynqmp.conf: Modify PMU_FIRMWARE_DEPLOY_DIR and PMU_FIRMWARE_IMAGE_NAME
Update KERNEL_VERSION to 5.4
zcu102-zynqmp.conf: Pass dtb and dtb load address as QB_OPT args for qemuboot
Enable kernel configurations for viruatlization distro feature
zc702-zynq7: Add qemu wiring for zc702 machine
qemu-xilinx-multiarch-helper-native_1.0.bb: Move multiarch wrapper script to bindir
qemuboot-xilinx.bbclass: Remove the subdir added to the qemu target path
external-hdf.bbappend: move to meta-xilinx-tools layer
xrt: Remove references to PACKAGE_CLASSES from xrt recipes
kernel-module-hdmi: Update LICENSE_CHECKSUM for kenrel-module-hdmi
xilinx-kmeta: Upstream xen and ocicontainer configs to YP kernel-cache
Update commit ids for 2020.1 release
arm-trusted-firmware.inc: Update package version
Update commit ids for 2020.1 release
lopper: Update commit id for 2020.1 release
layer.conf: Set layer compat to dunfell & gatesgarth
qemu-xilinx-native.inc: Fix the patch file names for dunfell Fix patch file names for dunfell
libmali-xlnx: Inherit features_check instead of distro_features_check
gcc-9*: Upgrade gcc from 9.2->10.1
libgloss, newlib: Upgrade version from 3.1 -> 3.3
meson_%.bbappend: Remove bbappend from layer
qemu-xilinx.inc: Add patch to enable/disbable libudev in qemu configure
python3-dtc_1.5.1.bb: Explicitly set the path to run make during configure
qemu-devicetrees: Use python3 instead of python
u-boot-xlnx.inc: Explicitly set builddir path
Sandeep Gundlupet Raju (2):
conf/machine/kc705-microbalzeel.conf: Fix U-boot defconfig
local.conf.sample: Updating XILINX_VER_MAIN
Swagath Gadde (4):
u-boot-zynq-scr: Add pxeboot support in u-boot-scr
zcu216-zynqmp: Add support for zcu216 board
u-boot-zynq-scr:Add initrd label to pxe config
zcu208-zynqmp: Add support for zcu208 board
Varalaxmi Bingi (4):
Update XILINX_RELEASE_VERSION to v2020.1
zcu1285-zynqmp.conf:using common u-boot defconfig
u-boot-xlnx.inc:u-boot-xlnx_2020.1.bb: kc705 patch
removing kc705 patch
Vishal Sagar (3):
kernel-module-hdmi_git.bb: Add versal support
kernel-module-hdmi: Update for 2020.1 release
kernel-module-hdmi: Update commit id and license md5sum for 2020.1
ch vamshi krishna (1):
xrt_git.bb: Add icd support for edge platforms
Signed-off-by: Andrew Geissler <geissonator@yahoo.com>
Change-Id: I71ace4a7992c023b84c864abd45e634b5e48f751
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend
deleted file mode 100644
index 1a00c61..0000000
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend
+++ /dev/null
@@ -1,32 +0,0 @@
-FILESEXTRAPATHS_append_microblaze := "${THISDIR}/binutils-2.32:"
-SRC_URI_append_microblaze = " \
- file://0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch \
- file://0002-Add-mlittle-endian-and-mbig-endian-flags.patch \
- file://0003-Disable-the-warning-message-for-eh_frame_hdr.patch \
- file://0004-Fix-relaxation-of-assembler-resolved-references.patch \
- file://0005-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch \
- file://0006-upstream-change-to-garbage-collection-sweep-causes-m.patch \
- file://0007-Fix-bug-in-TLSTPREL-Relocation.patch \
- file://0008-Added-Address-extension-instructions.patch \
- file://0009-fixing-the-MAX_OPCODES-to-correct-value.patch \
- file://0010-Add-new-bit-field-instructions.patch \
- file://0011-fixing-the-imm-bug.patch \
- file://0012-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch \
- file://0013-fixing-the-constant-range-check-issue.patch \
- file://0014-Patch-Microblaze-Compiler-will-give-error-messages-i.patch \
- file://0015-intial-commit-of-MB-64-bit.patch \
- file://0016-MB-X-initial-commit.patch \
- file://0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch \
- file://0018-Added-relocations-for-MB-X.patch \
- file://0019-Fixed-MB-x-relocation-issues.patch \
- file://0020-Fixing-the-branch-related-issues.patch \
- file://0021-Fixed-address-computation-issues-with-64bit-address.patch \
- file://0022-Adding-new-relocation-to-support-64bit-rodata.patch \
- file://0023-fixing-the-.bss-relocation-issue.patch \
- file://0024-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch \
- file://0025-Patch-MicroBlaze-fixed-Build-issue-which-are-due-to-.patch \
- file://0026-Patch-Microblaze-changes-of-PR22458-failure-to-choos.patch \
- file://0029-Patch-Microblaze-Binutils-security-check-is-causing-.patch \
- file://0030-fixing-the-long-long-long-mingw-toolchain-issue.patch \
- file://0031-fixing-the-_STACK_SIZE-issue-with-the-flto-flag.patch \
- "
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0031-fixing-the-_STACK_SIZE-issue-with-the-flto-flag.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0031-fixing-the-_STACK_SIZE-issue-with-the-flto-flag.patch
deleted file mode 100644
index 8c54f76..0000000
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0031-fixing-the-_STACK_SIZE-issue-with-the-flto-flag.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From e28b33db95e6b71afe2eaca9d7090b3bfc20f08e Mon Sep 17 00:00:00 2001
-From: Nagaraju <nmekala@xilinx.com>
-Date: Wed, 20 Mar 2019 11:42:07 +0530
-Subject: [PATCH] fixing the _STACK_SIZE issue with the flto flag
-
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
-
----
- ld/scripttempl/elfmicroblaze.sc | 12 ++++++------
- 1 file changed, 6 insertions(+), 6 deletions(-)
-
-diff --git a/ld/scripttempl/elfmicroblaze.sc b/ld/scripttempl/elfmicroblaze.sc
-index 30b9c28..6be0f4e 100644
---- a/ld/scripttempl/elfmicroblaze.sc
-+++ b/ld/scripttempl/elfmicroblaze.sc
-@@ -63,9 +63,9 @@ ${RELOCATING+${LIB_SEARCH_DIRS}}
-
- ${RELOCATING+ENTRY (${ENTRY})}
-
--${RELOCATING+_TEXT_START_ADDR = DEFINED(_TEXT_START_ADDR) ? _TEXT_START_ADDR : 0x50;
--_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x0;
--_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;}
-+${RELOCATING+_DEF_TEXT_START_ADDR = DEFINED(_TEXT_START_ADDR) ? _TEXT_START_ADDR : 0x50;
-+_DEF_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x0;
-+_DEF_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;}
-
- SECTIONS
- {
-@@ -75,7 +75,7 @@ SECTIONS
- .vectors.debug_sw_break 0x18 : { KEEP (*(.vectors.debug_sw_break)) } = 0
- .vectors.hw_exception 0x20 : { KEEP (*(.vectors.hw_exception)) } = 0
-
-- ${RELOCATING+. = _TEXT_START_ADDR;}
-+ ${RELOCATING+. = _DEF_TEXT_START_ADDR;}
-
- ${RELOCATING+ _ftext = .;}
- .text : {
-@@ -207,7 +207,7 @@ SECTIONS
- .heap : {
- ${RELOCATING+ _heap = .;}
- ${RELOCATING+ _heap_start = .;}
-- ${RELOCATING+ . += _HEAP_SIZE;}
-+ ${RELOCATING+ . += _DEF_HEAP_SIZE;}
- ${RELOCATING+ _heap_end = .;}
- }
-
-@@ -215,7 +215,7 @@ SECTIONS
-
- .stack : {
- ${RELOCATING+ _stack_end = .;}
-- ${RELOCATING+ . += _STACK_SIZE;}
-+ ${RELOCATING+ . += _DEF_STACK_SIZE;}
- ${RELOCATING+ . = ALIGN(. != 0 ? 8 : 1);}
- ${RELOCATING+ _stack = .;}
- ${RELOCATING+ _end = .;}
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-cross-canadian_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-cross-canadian_%.bbappend
new file mode 100644
index 0000000..e439cae
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-cross-canadian_%.bbappend
@@ -0,0 +1,4 @@
+MICROBLAZEPATCHES = ""
+MICROBLAZEPATCHES_microblaze = "binutils-microblaze.inc"
+
+require ${MICROBLAZEPATCHES}
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-cross_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-cross_%.bbappend
new file mode 100644
index 0000000..e439cae
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-cross_%.bbappend
@@ -0,0 +1,4 @@
+MICROBLAZEPATCHES = ""
+MICROBLAZEPATCHES_microblaze = "binutils-microblaze.inc"
+
+require ${MICROBLAZEPATCHES}
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-microblaze.inc b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-microblaze.inc
new file mode 100644
index 0000000..f2f2991
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-microblaze.inc
@@ -0,0 +1,50 @@
+FILESEXTRAPATHS_append := ":${THISDIR}/binutils"
+
+SRC_URI_append = " \
+ file://0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch \
+ file://0002-Add-mlittle-endian-and-mbig-endian-flags.patch \
+ file://0003-Disable-the-warning-message-for-eh_frame_hdr.patch \
+ file://0004-Fix-relaxation-of-assembler-resolved-references.patch \
+ file://0005-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch \
+ file://0006-upstream-change-to-garbage-collection-sweep-causes-m.patch \
+ file://0007-Fix-bug-in-TLSTPREL-Relocation.patch \
+ file://0008-Added-Address-extension-instructions.patch \
+ file://0009-fixing-the-MAX_OPCODES-to-correct-value.patch \
+ file://0010-Add-new-bit-field-instructions.patch \
+ file://0011-fixing-the-imm-bug.patch \
+ file://0012-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch \
+ file://0013-fixing-the-constant-range-check-issue.patch \
+ file://0014-Patch-Microblaze-Compiler-will-give-error-messages-i.patch \
+ file://0015-intial-commit-of-MB-64-bit.patch \
+ file://0016-MB-X-initial-commit.patch \
+ file://0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch \
+ file://0018-Added-relocations-for-MB-X.patch \
+ file://0019-Fixed-MB-x-relocation-issues.patch \
+ file://0020-Fixing-the-branch-related-issues.patch \
+ file://0021-Fixed-address-computation-issues-with-64bit-address.patch \
+ file://0022-Adding-new-relocation-to-support-64bit-rodata.patch \
+ file://0023-fixing-the-.bss-relocation-issue.patch \
+ file://0024-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch \
+ file://0025-Patch-MicroBlaze-fixed-Build-issue-which-are-due-to-.patch \
+ file://0026-Patch-Microblaze-changes-of-PR22458-failure-to-choos.patch \
+ file://0027-Revert-ld-Remove-unused-expression-state.patch \
+ file://0028-Patch-Microblaze-Binutils-security-check-is-causing-.patch \
+ file://0029-fixing-the-long-long-long-mingw-toolchain-issue.patch \
+ file://0030-Added-support-to-new-arithmetic-single-register-inst.patch \
+ file://0031-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch \
+ file://0032-Add-initial-port-of-linux-gdbserver.patch \
+ file://0033-Initial-port-of-core-reading-support.patch \
+ file://0034-Fix-debug-message-when-register-is-unavailable.patch \
+ file://0035-revert-master-rebase-changes-to-gdbserver.patch \
+ file://0036-revert-master-rebase-changes-to-gdbserver-previous-c.patch \
+ file://0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch \
+ file://0038-Initial-support-for-native-gdb.patch \
+ file://0039-Fixing-the-issues-related-to-GDB-7.12.patch \
+ file://0040-Patch-microblaze-Adding-64-bit-MB-support.patch \
+ file://0041-patch-MicroBlaze-porting-GDB-for-linux.patch \
+ file://0042-Correcting-the-register-names-from-slr-shr-to-rslr-r.patch \
+ file://0043-Removing-the-header-gdb_assert.h-from-MB-target-file.patch \
+ file://0044-gdb-microblaze-linux-nat.c-Fix-target-compilation-of.patch \
+ file://0045-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch \
+ file://0046-Patch-MicroBlaze-m64-This-patch-will-remove-imml-0-a.patch \
+ "
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
similarity index 92%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
index 5860848..e0de79f 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
@@ -1,22 +1,21 @@
-From ad671256112cfee47871e91c6d390daea1b8fa2f Mon Sep 17 00:00:00 2001
+From 247ead894f7079a4ededf2b48a65ffa6e78e2222 Mon Sep 17 00:00:00 2001
From: David Holsgrove <david.holsgrove@xilinx.com>
Date: Wed, 8 May 2013 11:03:36 +1000
-Subject: [PATCH] Add wdc.ext.clear and wdc.ext.flush insns
+Subject: [PATCH 01/43] Add wdc.ext.clear and wdc.ext.flush insns
Added two new instructions, wdc.ext.clear and wdc.ext.flush,
to enable MicroBlaze to flush an external cache, which is
used with the new coherency support for multiprocessing.
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by:nagaraju <nmekala@xilix.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
-
---
opcodes/microblaze-opc.h | 5 ++++-
opcodes/microblaze-opcm.h | 4 ++--
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index 62ee3c9..865151f 100644
+index 62ee3c9a4d..865151f95b 100644
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -91,6 +91,7 @@
@@ -47,7 +46,7 @@
{"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
{"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index 5a2d3b0..42f3dd3 100644
+index 5a2d3b0c8b..42f3dd3be5 100644
--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
@@ -33,8 +33,8 @@ enum microblaze_instr
@@ -61,3 +60,6 @@
bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0002-Add-mlittle-endian-and-mbig-endian-flags.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0002-Add-mlittle-endian-and-mbig-endian-flags.patch
similarity index 89%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0002-Add-mlittle-endian-and-mbig-endian-flags.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0002-Add-mlittle-endian-and-mbig-endian-flags.patch
index f0df4b8..98e40c0 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0002-Add-mlittle-endian-and-mbig-endian-flags.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0002-Add-mlittle-endian-and-mbig-endian-flags.patch
@@ -1,7 +1,7 @@
-From cd4e233a38df5eee833c77f4393e710ad5383ac0 Mon Sep 17 00:00:00 2001
+From 7163824e07ade3ad2dc24e888265d27e0bc87869 Mon Sep 17 00:00:00 2001
From: nagaraju <nmekala@xilix.com>
Date: Tue, 19 Mar 2013 17:18:23 +0530
-Subject: [PATCH] Add mlittle-endian and mbig-endian flags
+Subject: [PATCH 02/43] Add mlittle-endian and mbig-endian flags
Added support in gas for mlittle-endian and mbig-endian flags
as options.
@@ -9,15 +9,14 @@
Updated show usage for MicroBlaze specific assembler options
to include new entries.
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Signed-off-by:nagaraju <nmekala@xilix.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
-
---
gas/config/tc-microblaze.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index ab90c6b..c92e9ce 100644
+index ab90c6b20f..c92e9ce563 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -37,6 +37,8 @@
@@ -60,3 +59,6 @@
}
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0003-Disable-the-warning-message-for-eh_frame_hdr.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
similarity index 78%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
index 64d27d9..445f5dd 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
@@ -1,17 +1,15 @@
-From a8cbf5f3e93150132f194cfa3008fe896457171f Mon Sep 17 00:00:00 2001
+From 2b9eec7fdfae66c5500baef444559976d1b20e0b Mon Sep 17 00:00:00 2001
From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Date: Fri, 22 Jun 2012 01:20:20 +0200
-Subject: [PATCH] Disable the warning message for eh_frame_hdr
+Subject: [PATCH 03/43] Disable the warning message for eh_frame_hdr
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
-
---
bfd/elf-eh-frame.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c
-index a13e81e..1824ba6 100644
+index a13e81ebb8..1824ba6e5b 100644
--- a/bfd/elf-eh-frame.c
+++ b/bfd/elf-eh-frame.c
@@ -1044,10 +1044,13 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info,
@@ -28,3 +26,6 @@
hdr_info->u.dwarf.table = FALSE;
if (sec_info)
free (sec_info);
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0004-Fix-relaxation-of-assembler-resolved-references.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0004-Fix-relaxation-of-assembler-resolved-references.patch
similarity index 90%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0004-Fix-relaxation-of-assembler-resolved-references.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0004-Fix-relaxation-of-assembler-resolved-references.patch
index 4cae439..d1b754c 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0004-Fix-relaxation-of-assembler-resolved-references.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0004-Fix-relaxation-of-assembler-resolved-references.patch
@@ -1,10 +1,7 @@
-From 2b87c5c4ec4a7d6285c0991c202aae3cf8401d99 Mon Sep 17 00:00:00 2001
+From ababe1df64146c616455eb1af4cf8fd21eb6f42c Mon Sep 17 00:00:00 2001
From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Date: Tue, 14 Feb 2012 01:00:22 +0100
-Subject: [PATCH] Fix relaxation of assembler resolved references
-
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Subject: [PATCH 04/43] Fix relaxation of assembler resolved references
---
bfd/elf32-microblaze.c | 38 ++++++++++++++++++++++++++++++++++++++
@@ -12,7 +9,7 @@
2 files changed, 39 insertions(+)
diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index e3c8027..359484d 100644
+index e3c8027248..359484dd5e 100644
--- a/bfd/elf32-microblaze.c
+++ b/bfd/elf32-microblaze.c
@@ -1973,6 +1973,44 @@ microblaze_elf_relax_section (bfd *abfd,
@@ -61,7 +58,7 @@
{
isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index c92e9ce..3e72840 100644
+index c92e9ce563..3e728400b7 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -2205,6 +2205,7 @@ md_apply_fix (fixS * fixP,
@@ -72,3 +69,6 @@
}
return;
}
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0005-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0005-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch
similarity index 89%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0005-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0005-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch
index a2954c9..ac13e6e 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0005-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0005-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch
@@ -1,32 +1,31 @@
-From 68a91eb7ac94f0e0c6e9ebd7ad148c80cbc227df Mon Sep 17 00:00:00 2001
+From e9837b5aec42b084c93868095b409f9a6a81b570 Mon Sep 17 00:00:00 2001
From: Nagaraju Mekala <nmekala@xilix.com>
Date: Mon, 6 Feb 2017 15:53:08 +0530
-Subject: [PATCH] Fixup debug_loc sections after linker relaxation Adds a new
- reloctype R_MICROBLAZE_32_NONE, used for passing reloc info from the
- assembler to the linker when the linker manages to fully resolve a local
- symbol reference.
+Subject: [PATCH 05/43] [LOCAL]: Fixup debug_loc sections after linker
+ relaxation Adds a new reloctype R_MICROBLAZE_32_NONE, used for passing reloc
+ info from the assembler to the linker when the linker manages to fully
+ resolve a local symbol reference.
This is a workaround for design flaws in the assembler to
linker interface with regards to linker relaxation.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
-
+Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com>
---
- bfd/bfd-in2.h | 9 ++++++--
- bfd/elf32-microblaze.c | 53 ++++++++++++++++++++++++++++++++++------------
+ bfd/bfd-in2.h | 9 +++++--
+ bfd/elf32-microblaze.c | 53 ++++++++++++++++++++++++++++----------
bfd/libbfd.h | 1 +
- bfd/reloc.c | 6 ++++++
- binutils/readelf.c | 4 ++++
- gas/config/tc-microblaze.c | 5 ++++-
+ bfd/reloc.c | 6 +++++
+ binutils/readelf.c | 4 +++
+ gas/config/tc-microblaze.c | 5 +++-
include/elf/microblaze.h | 2 ++
7 files changed, 64 insertions(+), 16 deletions(-)
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
-index e251d7e..fe6933a 100644
+index e25da50aaf..721531886a 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
-@@ -5867,10 +5867,15 @@ value relative to the read-write small data area anchor */
+@@ -5866,10 +5866,15 @@ value relative to the read-write small data area anchor */
expressions of the form "Symbol Op Symbol" */
BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
@@ -45,7 +44,7 @@
/* This is a 64 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). The relocation is
diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index 359484d..1c69c26 100644
+index 359484dd5e..1c69c269c7 100644
--- a/bfd/elf32-microblaze.c
+++ b/bfd/elf32-microblaze.c
@@ -176,7 +176,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
@@ -164,7 +163,7 @@
0,
sec);
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
-index 36284d7..feb9fad 100644
+index 36284d71a9..feb9fada1e 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -2901,6 +2901,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
@@ -176,27 +175,27 @@
"BFD_RELOC_MICROBLAZE_64_GOTPC",
"BFD_RELOC_MICROBLAZE_64_GOT",
diff --git a/bfd/reloc.c b/bfd/reloc.c
-index e6446a7..87753ae 100644
+index e6446a7809..87753ae4f0 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
-@@ -6796,6 +6796,12 @@ ENUMDOC
+@@ -6795,6 +6795,12 @@ ENUM
+ ENUMDOC
This is a 32 bit reloc for the microblaze to handle
expressions of the form "Symbol Op Symbol"
- ENUM
++ENUM
+ BFD_RELOC_MICROBLAZE_32_NONE
+ENUMDOC
+ This is a 32 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction). No relocation is
+ done here - only used for relaxing
-+ENUM
+ ENUM
BFD_RELOC_MICROBLAZE_64_NONE
ENUMDOC
- This is a 64 bit reloc that stores the 32 bit pc relative
diff --git a/binutils/readelf.c b/binutils/readelf.c
-index 9df3742..1bbc2d1 100644
+index b13eb6a43b..da6252c128 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
-@@ -13020,6 +13020,10 @@ is_none_reloc (Filedata * filedata, unsigned int reloc_type)
+@@ -13019,6 +13019,10 @@ is_none_reloc (Filedata * filedata, unsigned int reloc_type)
|| reloc_type == 32 /* R_AVR_DIFF32. */);
case EM_METAG:
return reloc_type == 3; /* R_METAG_NONE. */
@@ -208,7 +207,7 @@
return (reloc_type == 0 /* R_XTENSA_NONE. */
|| reloc_type == 204 /* R_NDS32_DIFF8. */
diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index 3e72840..fa665b4 100644
+index 3e728400b7..fa665b4e25 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -2201,7 +2201,9 @@ md_apply_fix (fixS * fixP,
@@ -231,7 +230,7 @@
case BFD_RELOC_32:
case BFD_RELOC_MICROBLAZE_32_LO:
diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
-index 830b5ad..6ee0966 100644
+index 830b5ad446..6ee0966444 100644
--- a/include/elf/microblaze.h
+++ b/include/elf/microblaze.h
@@ -61,6 +61,8 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
@@ -243,3 +242,6 @@
END_RELOC_NUMBERS (R_MICROBLAZE_max)
/* Global base address names. */
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0006-upstream-change-to-garbage-collection-sweep-causes-m.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0006-upstream-change-to-garbage-collection-sweep-causes-m.patch
similarity index 84%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0006-upstream-change-to-garbage-collection-sweep-causes-m.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0006-upstream-change-to-garbage-collection-sweep-causes-m.patch
index 8c72ecf..97d692c 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0006-upstream-change-to-garbage-collection-sweep-causes-m.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0006-upstream-change-to-garbage-collection-sweep-causes-m.patch
@@ -1,7 +1,7 @@
-From 0ee164f7e50d88e1cda4fdebd6f7bd182d0f27b3 Mon Sep 17 00:00:00 2001
+From 403d6e82742452be4e3f3010c8d9989f0a490c0b Mon Sep 17 00:00:00 2001
From: David Holsgrove <david.holsgrove@xilinx.com>
Date: Wed, 27 Feb 2013 13:56:11 +1000
-Subject: [PATCH] upstream change to garbage collection sweep causes mb
+Subject: [PATCH 06/43] upstream change to garbage collection sweep causes mb
regression
Upstream change for PR13177 now clears the def_regular during gc_sweep of a
@@ -18,14 +18,12 @@
relocations for a shared lib with garbage collection this occurs
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
-
---
bfd/elflink.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/bfd/elflink.c b/bfd/elflink.c
-index e50c0e4..09d43e3 100644
+index e50c0e4b38..09d43e3ca5 100644
--- a/bfd/elflink.c
+++ b/bfd/elflink.c
@@ -6187,7 +6187,6 @@ elf_gc_sweep_symbol (struct elf_link_hash_entry *h, void *data)
@@ -36,3 +34,6 @@
h->ref_regular = 0;
h->ref_regular_nonweak = 0;
}
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0007-Fix-bug-in-TLSTPREL-Relocation.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0007-Fix-bug-in-TLSTPREL-Relocation.patch
similarity index 84%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0007-Fix-bug-in-TLSTPREL-Relocation.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0007-Fix-bug-in-TLSTPREL-Relocation.patch
index 472aa0c..49534b4 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0007-Fix-bug-in-TLSTPREL-Relocation.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0007-Fix-bug-in-TLSTPREL-Relocation.patch
@@ -1,22 +1,19 @@
-From 1367d2933de24720fa24032947f784b72b54e974 Mon Sep 17 00:00:00 2001
+From 072a8968c50b2ebd93e225a6b959916f9d60b493 Mon Sep 17 00:00:00 2001
From: Nagaraju Mekala <nmekala@xilix.com>
Date: Mon, 15 Jun 2015 16:50:30 +0530
-Subject: [PATCH] Fix bug in TLSTPREL Relocation
+Subject: [PATCH 07/43] Fix bug in TLSTPREL Relocation
Fixed the problem related to the fixup/relocations TLSTPREL.
When the fixup is applied the addend is not added at the correct offset
of the instruction. The offset is hard coded considering its big endian
and it fails for Little endian. This patch allows support for both
big & little-endian compilers
-
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
-
---
bfd/elf32-microblaze.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index 1c69c26..d19a6dc 100644
+index 1c69c269c7..d19a6dca84 100644
--- a/bfd/elf32-microblaze.c
+++ b/bfd/elf32-microblaze.c
@@ -1451,9 +1451,9 @@ microblaze_elf_relocate_section (bfd *output_bfd,
@@ -31,3 +28,6 @@
break;
case (int) R_MICROBLAZE_TEXTREL_64:
case (int) R_MICROBLAZE_TEXTREL_32_LO:
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0008-Added-Address-extension-instructions.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0008-Added-Address-extension-instructions.patch
similarity index 97%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0008-Added-Address-extension-instructions.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0008-Added-Address-extension-instructions.patch
index 23d1793..51fcee9 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0008-Added-Address-extension-instructions.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0008-Added-Address-extension-instructions.patch
@@ -1,7 +1,7 @@
-From 57675e049d815f6fce100bd5effaea187abacf04 Mon Sep 17 00:00:00 2001
+From 4674056da6bafa8168c0a680498b958f3a39be94 Mon Sep 17 00:00:00 2001
From: Nagaraju Mekala <nmekala@xilix.com>
Date: Mon, 18 Jan 2016 12:28:21 +0530
-Subject: [PATCH] Added Address extension instructions
+Subject: [PATCH 08/43] Added Address extension instructions
This patch adds the support of new instructions which are required
for supporting Address extension feature.
@@ -15,14 +15,13 @@
Added new instructions
*microblaze-opcm.h (microblaze_instr): Update
Added new instructions
-
---
opcodes/microblaze-opc.h | 11 +++++++++++
opcodes/microblaze-opcm.h | 10 +++++-----
2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index 865151f..330f104 100644
+index 865151f95b..330f1040e7 100644
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -178,8 +178,11 @@ struct op_code_struct
@@ -72,7 +71,7 @@
{"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst },
{"", 0, 0, 0, 0, 0, 0, 0, 0},
diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index 42f3dd3..1c39dbf 100644
+index 42f3dd3be5..1c39dbf50b 100644
--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
@@ -33,13 +33,13 @@ enum microblaze_instr
@@ -94,3 +93,6 @@
sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
fint, fsqrt,
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0009-fixing-the-MAX_OPCODES-to-correct-value.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0009-fixing-the-MAX_OPCODES-to-correct-value.patch
similarity index 68%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0009-fixing-the-MAX_OPCODES-to-correct-value.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0009-fixing-the-MAX_OPCODES-to-correct-value.patch
index 0eaa699..d93ccd2 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0009-fixing-the-MAX_OPCODES-to-correct-value.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0009-fixing-the-MAX_OPCODES-to-correct-value.patch
@@ -1,16 +1,14 @@
-From 98b1a76e13ad32c979208a22e5b6b7cb260426b0 Mon Sep 17 00:00:00 2001
+From 7651a2f7ab486e26981cb5e032bf578d0951ff4a Mon Sep 17 00:00:00 2001
From: Nagaraju Mekala <nmekala@xilix.com>
Date: Thu, 28 Jan 2016 14:07:34 +0530
-Subject: [PATCH] fixing the MAX_OPCODES to correct value
-
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Subject: [PATCH 09/43] fixing the MAX_OPCODES to correct value
---
opcodes/microblaze-opc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index 330f104..2a6b841 100644
+index 330f1040e7..2a6b841232 100644
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -102,7 +102,7 @@
@@ -22,3 +20,6 @@
struct op_code_struct
{
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0010-Add-new-bit-field-instructions.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0010-Add-new-bit-field-instructions.patch
similarity index 94%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0010-Add-new-bit-field-instructions.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0010-Add-new-bit-field-instructions.patch
index ea288aa..901c53e 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0010-Add-new-bit-field-instructions.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0010-Add-new-bit-field-instructions.patch
@@ -1,7 +1,7 @@
-From 200359b776fbb19a1423ff4d0c46f5301af197c6 Mon Sep 17 00:00:00 2001
+From 7e9e123337f2d441b213ea9d0be07e9049241f64 Mon Sep 17 00:00:00 2001
From: Nagaraju Mekala <nmekala@xilix.com>
Date: Mon, 18 Jul 2016 12:24:28 +0530
-Subject: [PATCH] Add new bit-field instructions
+Subject: [PATCH 10/43] Add new bit-field instructions
This patches adds new bsefi and bsifi instructions.
BSEFI- The instruction shall extract a bit field from a
@@ -12,16 +12,15 @@
The rest of the bits in the destination register shall be unchanged
Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-
---
- gas/config/tc-microblaze.c | 71 +++++++++++++++++++++++++++++++++++++++++++++-
- opcodes/microblaze-dis.c | 16 +++++++++++
- opcodes/microblaze-opc.h | 12 +++++++-
+ gas/config/tc-microblaze.c | 71 +++++++++++++++++++++++++++++++++++++-
+ opcodes/microblaze-dis.c | 16 +++++++++
+ opcodes/microblaze-opc.h | 12 ++++++-
opcodes/microblaze-opcm.h | 6 +++-
4 files changed, 102 insertions(+), 3 deletions(-)
diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index fa665b4..71bb888 100644
+index fa665b4e25..71bb888ab8 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -917,7 +917,7 @@ md_assemble (char * str)
@@ -111,13 +110,14 @@
if (strcmp (op_end, ""))
op_end = parse_reg (op_end + 1, ®1); /* Get r1. */
diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
-index f691740..f8aaf27 100644
+index f691740dfd..f8aaf27873 100644
--- a/opcodes/microblaze-dis.c
+++ b/opcodes/microblaze-dis.c
-@@ -74,6 +74,18 @@ get_field_imm5_mbar (long instr)
+@@ -73,6 +73,18 @@ get_field_imm5_mbar (long instr)
+ return(strdup(tmpstr));
}
- static char *
++static char *
+get_field_imm5width (long instr)
+{
+ char tmpstr[25];
@@ -129,10 +129,9 @@
+ return (strdup (tmpstr));
+}
+
-+static char *
+ static char *
get_field_rfsl (long instr)
{
- char tmpstr[25];
@@ -396,6 +408,10 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
/* For mbar 16 or sleep insn. */
case INST_TYPE_NONE:
@@ -145,7 +144,7 @@
case INST_TYPE_RD:
print_func (stream, "\t%s", get_field_rd (inst));
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index 2a6b841..ce8ac35 100644
+index 2a6b841232..ce8ac351b5 100644
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -59,6 +59,9 @@
@@ -196,7 +195,7 @@
#endif /* MICROBLAZE_OPC */
diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index 1c39dbf..2866269 100644
+index 1c39dbf50b..28662694cd 100644
--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
@@ -29,7 +29,7 @@ enum microblaze_instr
@@ -226,3 +225,6 @@
/* FSL imm mask for get, put instructions. */
#define RFSL_MASK 0x000000F
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0011-fixing-the-imm-bug.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0011-fixing-the-imm-bug.patch
similarity index 70%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0011-fixing-the-imm-bug.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0011-fixing-the-imm-bug.patch
index 43d368c..4c1b0c2 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0011-fixing-the-imm-bug.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0011-fixing-the-imm-bug.patch
@@ -1,17 +1,15 @@
-From cb65478b8ec240b372a9da7fe33875a59e89a1fe Mon Sep 17 00:00:00 2001
+From 8b2e8fe916066bb1caa99abc67f8cde3ebd41c70 Mon Sep 17 00:00:00 2001
From: Nagaraju Mekala <nmekala@xilix.com>
Date: Mon, 10 Jul 2017 16:07:28 +0530
-Subject: [PATCH] fixing the imm bug. with relax option imm -1 is also getting
- removed this is corrected now.
-
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Subject: [PATCH 11/43] fixing the imm bug. with relax option imm -1 is also
+ getting removed this is corrected now.
---
bfd/elf32-microblaze.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index d19a6dc..d001437 100644
+index d19a6dca84..d001437b3f 100644
--- a/bfd/elf32-microblaze.c
+++ b/bfd/elf32-microblaze.c
@@ -1869,8 +1869,7 @@ microblaze_elf_relax_section (bfd *abfd,
@@ -24,3 +22,6 @@
{
/* We can delete this instruction. */
sec->relax[sec->relax_count].addr = irel->r_offset;
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0012-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0012-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch
similarity index 69%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0012-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0012-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch
index 9abed96..ad4db43 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0012-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0012-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch
@@ -1,18 +1,15 @@
-From 58271555959fcc3eadb1f23c8d31d793c979984b Mon Sep 17 00:00:00 2001
+From 2a7b66bbc0473c6cbe6653a48818962b5b411ef2 Mon Sep 17 00:00:00 2001
From: Mahesh Bodapati <mbodapat@xilinx.com>
Date: Fri, 29 Sep 2017 18:00:23 +0530
-Subject: [PATCH] fixed bug in GCC so that It will support .long 0U and .long
- 0u
-
-Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Subject: [PATCH 12/43] [Patch,Microblaze]: fixed bug in GCC so that It will
+ support .long 0U and .long 0u
---
gas/expr.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/gas/expr.c b/gas/expr.c
-index ee85bda..b502418 100644
+index ee85bda1cc..b502418b71 100644
--- a/gas/expr.c
+++ b/gas/expr.c
@@ -810,6 +810,15 @@ operand (expressionS *expressionP, enum expr_mode mode)
@@ -31,3 +28,6 @@
c = *input_line_pointer;
switch (c)
{
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0013-fixing-the-constant-range-check-issue.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0013-fixing-the-constant-range-check-issue.patch
similarity index 72%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0013-fixing-the-constant-range-check-issue.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0013-fixing-the-constant-range-check-issue.patch
index 4aef7c9..323b7bd 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0013-fixing-the-constant-range-check-issue.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0013-fixing-the-constant-range-check-issue.patch
@@ -1,17 +1,15 @@
-From 70ba2154c2261d5a9d35a765c29acc5fdcdeea38 Mon Sep 17 00:00:00 2001
+From 59a9a1a913b7dfa424792c907001413c1ddd320c Mon Sep 17 00:00:00 2001
From: Nagaraju Mekala <nmekala@xilix.com>
Date: Mon, 16 Oct 2017 15:44:23 +0530
-Subject: [PATCH] fixing the constant range check issue sample error: not in
- range ffffffff80000000..7fffffff, not ffffffff70000000
-
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Subject: [PATCH 13/43] fixing the constant range check issue sample error: not
+ in range ffffffff80000000..7fffffff, not ffffffff70000000
---
gas/config/tc-microblaze.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index 71bb888..16b10d0 100644
+index 71bb888ab8..16b10d00a9 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -757,7 +757,7 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max)
@@ -23,3 +21,6 @@
{
as_fatal (_("operand must be absolute in range %lx..%lx, not %lx"),
(long) min, (long) max, (long) e->X_add_number);
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0014-Patch-Microblaze-Compiler-will-give-error-messages-i.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0014-Patch-Microblaze-Compiler-will-give-error-messages-i.patch
similarity index 73%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0014-Patch-Microblaze-Compiler-will-give-error-messages-i.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0014-Patch-Microblaze-Compiler-will-give-error-messages-i.patch
index 2118256..1a3e013 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0014-Patch-Microblaze-Compiler-will-give-error-messages-i.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0014-Patch-Microblaze-Compiler-will-give-error-messages-i.patch
@@ -1,21 +1,18 @@
-From 1b8f6099c5f85d77ef666becff1c4edd0aa724ab Mon Sep 17 00:00:00 2001
+From 00b7561a868b08dab952b9b9f4a01118195aeb29 Mon Sep 17 00:00:00 2001
From: Mahesh Bodapati <mbodapat@xilinx.com>
Date: Wed, 21 Feb 2018 12:32:02 +0530
-Subject: [PATCH] Compiler will give error messages in more detail for
- mxl-gp-opt flag..
-
-Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Subject: [PATCH 14/43] [Patch,Microblaze]: Compiler will give error messages
+ in more detail for mxl-gp-opt flag..
---
ld/ldmain.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/ld/ldmain.c b/ld/ldmain.c
-index 725512f..2ed413a 100644
+index 77cdbd0dd2..517d85baef 100644
--- a/ld/ldmain.c
+++ b/ld/ldmain.c
-@@ -1448,6 +1448,18 @@ reloc_overflow (struct bfd_link_info *info,
+@@ -1446,6 +1446,18 @@ reloc_overflow (struct bfd_link_info *info,
break;
case bfd_link_hash_defined:
case bfd_link_hash_defweak:
@@ -34,3 +31,6 @@
einfo (_(" relocation truncated to fit: "
"%s against symbol `%pT' defined in %pA section in %pB"),
reloc_name, entry->root.string,
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0015-intial-commit-of-MB-64-bit.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0015-intial-commit-of-MB-64-bit.patch
similarity index 99%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0015-intial-commit-of-MB-64-bit.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0015-intial-commit-of-MB-64-bit.patch
index 1afe830..d0f96ec 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0015-intial-commit-of-MB-64-bit.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0015-intial-commit-of-MB-64-bit.patch
@@ -1,10 +1,7 @@
-From e0a7cf883ed02a73fda5f7d3e131afc8f1ebe416 Mon Sep 17 00:00:00 2001
+From 9aeae734291f8aaeb449c1403561b71de1ea3bea Mon Sep 17 00:00:00 2001
From: Nagaraju Mekala <nmekala@xilix.com>
Date: Sun, 30 Sep 2018 16:28:28 +0530
-Subject: [PATCH] intial commit of MB 64-bit
-
-Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Subject: [PATCH 15/43] intial commit of MB 64-bit
---
bfd/Makefile.am | 2 +
@@ -13,7 +10,7 @@
bfd/configure | 2 +
bfd/configure.ac | 2 +
bfd/cpu-microblaze.c | 52 +-
- bfd/elf64-microblaze.c | 3584 ++++++++++++++++++++++++++++++++++++
+ bfd/elf64-microblaze.c | 3584 ++++++++++++++++++++++++++++
bfd/targets.c | 6 +
gas/config/tc-microblaze.c | 274 ++-
gas/config/tc-microblaze.h | 4 +-
@@ -32,7 +29,7 @@
create mode 100644 ld/emulparams/elf64microblazeel.sh
diff --git a/bfd/Makefile.am b/bfd/Makefile.am
-index a919155..c5fd250 100644
+index a9191555ad..c5fd250812 100644
--- a/bfd/Makefile.am
+++ b/bfd/Makefile.am
@@ -570,6 +570,7 @@ BFD64_BACKENDS = \
@@ -52,7 +49,7 @@
elf64-tilegx.c \
elf64-x86-64.c \
diff --git a/bfd/Makefile.in b/bfd/Makefile.in
-index 896df52..fd457cb 100644
+index 896df52042..fd457cba1e 100644
--- a/bfd/Makefile.in
+++ b/bfd/Makefile.in
@@ -995,6 +995,7 @@ BFD64_BACKENDS = \
@@ -80,7 +77,7 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-tilegx.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-x86-64.Plo@am__quote@
diff --git a/bfd/config.bfd b/bfd/config.bfd
-index aef1448..8072c8a 100644
+index 0e1ddb659c..93d210643d 100644
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -850,11 +850,15 @@ case "${targ}" in
@@ -100,10 +97,10 @@
#ifdef BFD64
diff --git a/bfd/configure b/bfd/configure
-index e5bde48..5bf94d5 100755
+index 04786696dc..d455abe7c5 100755
--- a/bfd/configure
+++ b/bfd/configure
-@@ -15502,6 +15502,8 @@ do
+@@ -14847,6 +14847,8 @@ do
rx_elf32_linux_le_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;;
s390_elf32_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;;
s390_elf64_vec) tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;;
@@ -113,7 +110,7 @@
score_elf32_le_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64 ;;
sh_coff_vec) tb="$tb coff-sh.lo $coff" ;;
diff --git a/bfd/configure.ac b/bfd/configure.ac
-index 7cdf9c8..998a651 100644
+index eda38ea086..f01c3362fe 100644
--- a/bfd/configure.ac
+++ b/bfd/configure.ac
@@ -615,6 +615,8 @@ do
@@ -126,7 +123,7 @@
score_elf32_le_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64 ;;
sh_coff_vec) tb="$tb coff-sh.lo $coff" ;;
diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c
-index 9bc2eb3..c91ba46 100644
+index 9bc2eb3de9..c91ba46f75 100644
--- a/bfd/cpu-microblaze.c
+++ b/bfd/cpu-microblaze.c
@@ -23,7 +23,24 @@
@@ -195,7 +192,7 @@
};
diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
new file mode 100644
-index 0000000..0f43ae6
+index 0000000000..0f43ae6ea8
--- /dev/null
+++ b/bfd/elf64-microblaze.c
@@ -0,0 +1,3584 @@
@@ -3784,7 +3781,7 @@
+
+#include "elf64-target.h"
diff --git a/bfd/targets.c b/bfd/targets.c
-index 158168c..ef567a3 100644
+index 158168cb3b..ef567a30c8 100644
--- a/bfd/targets.c
+++ b/bfd/targets.c
@@ -706,6 +706,8 @@ extern const bfd_target mep_elf32_le_vec;
@@ -3808,7 +3805,7 @@
&mips_ecoff_be_vec,
diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index 16b10d0..c794347 100644
+index 16b10d00a9..c79434785a 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -35,10 +35,13 @@
@@ -4203,7 +4200,7 @@
diff --git a/gas/config/tc-microblaze.h b/gas/config/tc-microblaze.h
-index ca9dbb8..9d38d2c 100644
+index ca9dbb861f..9d38d2ced5 100644
--- a/gas/config/tc-microblaze.h
+++ b/gas/config/tc-microblaze.h
@@ -78,7 +78,9 @@ extern const struct relax_type md_relax_table[];
@@ -4218,7 +4215,7 @@
#define ELF_TC_SPECIAL_SECTIONS \
{ ".sdata", SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, \
diff --git a/include/elf/common.h b/include/elf/common.h
-index 996acf9..2f1e5be 100644
+index 996acf9703..2f1e5be366 100644
--- a/include/elf/common.h
+++ b/include/elf/common.h
@@ -339,6 +339,7 @@
@@ -4230,7 +4227,7 @@
#define EM_CSKY 252 /* C-SKY processor family. */
diff --git a/ld/Makefile.am b/ld/Makefile.am
-index d7faf19..f7b3b97 100644
+index c2c798b4fe..b272f537e4 100644
--- a/ld/Makefile.am
+++ b/ld/Makefile.am
@@ -422,6 +422,8 @@ ALL_64_EMULATION_SOURCES = \
@@ -4256,7 +4253,7 @@
$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
diff --git a/ld/Makefile.in b/ld/Makefile.in
-index 8b14f52..ffc9a3e 100644
+index fc687fc516..1a530ad729 100644
--- a/ld/Makefile.in
+++ b/ld/Makefile.in
@@ -907,6 +907,8 @@ ALL_64_EMULATION_SOURCES = \
@@ -4291,10 +4288,10 @@
$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
diff --git a/ld/configure.tgt b/ld/configure.tgt
-index 1e37d74..42f106d 100644
+index beba17ef51..5109799f2b 100644
--- a/ld/configure.tgt
+++ b/ld/configure.tgt
-@@ -424,6 +424,9 @@ microblaze*-linux*) targ_emul="elf32mb_linux"
+@@ -423,6 +423,9 @@ microblaze*-linux*) targ_emul="elf32mb_linux"
microblazeel*) targ_emul=elf32microblazeel
targ_extra_emuls=elf32microblaze
;;
@@ -4306,7 +4303,7 @@
;;
diff --git a/ld/emulparams/elf64microblaze.sh b/ld/emulparams/elf64microblaze.sh
new file mode 100644
-index 0000000..9c7b0eb
+index 0000000000..9c7b0eb708
--- /dev/null
+++ b/ld/emulparams/elf64microblaze.sh
@@ -0,0 +1,23 @@
@@ -4335,7 +4332,7 @@
+#GENERATE_SHLIB_SCRIPT=yes
diff --git a/ld/emulparams/elf64microblazeel.sh b/ld/emulparams/elf64microblazeel.sh
new file mode 100644
-index 0000000..9c7b0eb
+index 0000000000..9c7b0eb708
--- /dev/null
+++ b/ld/emulparams/elf64microblazeel.sh
@@ -0,0 +1,23 @@
@@ -4363,7 +4360,7 @@
+TEMPLATE_NAME=elf32
+#GENERATE_SHLIB_SCRIPT=yes
diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
-index f8aaf27..20ea6a8 100644
+index f8aaf27873..20ea6a885a 100644
--- a/opcodes/microblaze-dis.c
+++ b/opcodes/microblaze-dis.c
@@ -33,6 +33,7 @@
@@ -4457,7 +4454,7 @@
case INST_TYPE_RD:
print_func (stream, "\t%s", get_field_rd (inst));
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index ce8ac35..985834b 100644
+index ce8ac351b5..985834b8df 100644
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -40,7 +40,7 @@
@@ -4685,7 +4682,7 @@
#endif /* MICROBLAZE_OPC */
diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index 2866269..076dbcd 100644
+index 28662694cd..076dbcd0b3 100644
--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
@@ -25,6 +25,7 @@
@@ -4736,3 +4733,6 @@
/* FSL imm mask for get, put instructions. */
#define RFSL_MASK 0x000000F
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0016-MB-X-initial-commit.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0016-MB-X-initial-commit.patch
similarity index 96%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0016-MB-X-initial-commit.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0016-MB-X-initial-commit.patch
index 406d7bf..0c3da95 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0016-MB-X-initial-commit.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0016-MB-X-initial-commit.patch
@@ -1,51 +1,48 @@
-From 549bf1fafb7dfa2718e172a94ff68acb14320ed8 Mon Sep 17 00:00:00 2001
+From bcd4263219c9756b9c1c1df64c6fef1311057fac Mon Sep 17 00:00:00 2001
From: Nagaraju Mekala <nmekala@xilix.com>
Date: Sun, 30 Sep 2018 16:31:26 +0530
-Subject: [PATCH] MB-X initial commit code cleanup is needed.
-
-Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Subject: [PATCH 16/43] MB-X initial commit code cleanup is needed.
---
bfd/bfd-in2.h | 10 +++
- bfd/elf32-microblaze.c | 65 +++++++++++++++++--
- bfd/elf64-microblaze.c | 61 +++++++++++++++++-
+ bfd/elf32-microblaze.c | 65 +++++++++++++++-
+ bfd/elf64-microblaze.c | 61 ++++++++++++++-
bfd/libbfd.h | 2 +
- bfd/reloc.c | 12 ++++
- gas/config/tc-microblaze.c | 152 +++++++++++++++++++++++++++++++++++++--------
+ bfd/reloc.c | 12 +++
+ gas/config/tc-microblaze.c | 152 ++++++++++++++++++++++++++++++-------
include/elf/microblaze.h | 2 +
opcodes/microblaze-opc.h | 4 +-
opcodes/microblaze-opcm.h | 4 +-
9 files changed, 277 insertions(+), 35 deletions(-)
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
-index fe6933a..90645d1 100644
+index 721531886a..4f777059d8 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
-@@ -5878,11 +5878,21 @@ done here - only used for relaxing */
+@@ -5876,11 +5876,21 @@ done here - only used for relaxing */
+ * +done here - only used for relaxing */
BFD_RELOC_MICROBLAZE_64_NONE,
- /* This is a 64 bit reloc that stores the 32 bit pc relative
++/* This is a 64 bit reloc that stores the 32 bit pc relative
+ * +value in two words (with an imml instruction). No relocation is
+ * +done here - only used for relaxing */
+ BFD_RELOC_MICROBLAZE_64,
+
-+/* This is a 64 bit reloc that stores the 32 bit pc relative
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). The relocation is
PC-relative GOT offset */
BFD_RELOC_MICROBLAZE_64_GOTPC,
- /* This is a 64 bit reloc that stores the 32 bit pc relative
++/* This is a 64 bit reloc that stores the 32 bit pc relative
+value in two words (with an imml instruction). The relocation is
+PC-relative GOT offset */
+ BFD_RELOC_MICROBLAZE_64_GPC,
+
-+/* This is a 64 bit reloc that stores the 32 bit pc relative
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). The relocation is
GOT offset */
- BFD_RELOC_MICROBLAZE_64_GOT,
diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index d001437..035e71f 100644
+index d001437b3f..035e71f311 100644
--- a/bfd/elf32-microblaze.c
+++ b/bfd/elf32-microblaze.c
@@ -116,6 +116,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
@@ -159,13 +156,14 @@
/* Look at the reloc only if the value has been resolved. */
if (isym->st_shndx == shndx
diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index 0f43ae6..56a45f2 100644
+index 0f43ae6ea8..56a45f2a05 100644
--- a/bfd/elf64-microblaze.c
+++ b/bfd/elf64-microblaze.c
-@@ -117,6 +117,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+@@ -116,6 +116,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+ 0x0000ffff, /* Dest Mask. */
TRUE), /* PC relative offset? */
- /* A 64 bit relocation. Table entry not really used. */
++ /* A 64 bit relocation. Table entry not really used. */
+ HOWTO (R_MICROBLAZE_IMML_64, /* Type. */
+ 0, /* Rightshift. */
+ 4, /* Size (0 = byte, 1 = short, 2 = long). */
@@ -180,10 +178,9 @@
+ 0x0000ffff, /* Dest Mask. */
+ TRUE), /* PC relative offset? */
+
-+ /* A 64 bit relocation. Table entry not really used. */
+ /* A 64 bit relocation. Table entry not really used. */
HOWTO (R_MICROBLAZE_64, /* Type. */
0, /* Rightshift. */
- 2, /* Size (0 = byte, 1 = short, 2 = long). */
@@ -265,6 +280,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
0x0000ffff, /* Dest Mask. */
TRUE), /* PC relative offset? */
@@ -269,7 +266,7 @@
case R_MICROBLAZE_32_NONE:
{
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
-index feb9fad..450653f 100644
+index feb9fada1e..450653f2d8 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -2903,7 +2903,9 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
@@ -283,37 +280,36 @@
"BFD_RELOC_MICROBLAZE_64_PLT",
"BFD_RELOC_MICROBLAZE_64_GOTOFF",
diff --git a/bfd/reloc.c b/bfd/reloc.c
-index 87753ae..ccf29f5 100644
+index 87753ae4f0..ccf29f54cf 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
-@@ -6804,6 +6804,12 @@ ENUMDOC
+@@ -6803,12 +6803,24 @@ ENUMDOC
+ done here - only used for relaxing
ENUM
BFD_RELOC_MICROBLAZE_64_NONE
- ENUMDOC
++ENUMDOC
+ This is a 32 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imml instruction). No relocation is
+ done here - only used for relaxing
+ENUM
+ BFD_RELOC_MICROBLAZE_64
-+ENUMDOC
+ ENUMDOC
This is a 64 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). No relocation is
done here - only used for relaxing
-@@ -6811,6 +6817,12 @@ ENUM
+ ENUM
BFD_RELOC_MICROBLAZE_64_GOTPC
- ENUMDOC
- This is a 64 bit reloc that stores the 32 bit pc relative
++ENUMDOC
++ This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imml instruction). No relocation is
+ done here - only used for relaxing
+ENUM
+ BFD_RELOC_MICROBLAZE_64_GPC
-+ENUMDOC
-+ This is a 64 bit reloc that stores the 32 bit pc relative
+ ENUMDOC
+ This is a 64 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). The relocation is
- PC-relative GOT offset
- ENUM
diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index c794347..3f90b7c 100644
+index c79434785a..3f90b7c892 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -94,6 +94,7 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP";
@@ -648,7 +644,7 @@
default:
as_bad (_("unsupported BFD relocation size %u"), size);
diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
-index 6ee0966..16b2736 100644
+index 6ee0966444..16b2736577 100644
--- a/include/elf/microblaze.h
+++ b/include/elf/microblaze.h
@@ -62,6 +62,8 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
@@ -661,7 +657,7 @@
END_RELOC_NUMBERS (R_MICROBLAZE_max)
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index 985834b..9b6264b 100644
+index 985834b8df..9b6264b61c 100644
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -538,8 +538,8 @@ struct op_code_struct
@@ -676,7 +672,7 @@
{"dadd", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst },
{"drsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst },
diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index 076dbcd..5f2e190 100644
+index 076dbcd0b3..5f2e190d23 100644
--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
@@ -40,8 +40,8 @@ enum microblaze_instr
@@ -690,3 +686,6 @@
fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
fint, fsqrt,
tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch
similarity index 89%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch
index 062ee36..a642853 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch
@@ -1,18 +1,15 @@
-From 3735a1bb6174f15bde23dd2767675b49c9e8712f Mon Sep 17 00:00:00 2001
+From 7f6533a7c442b8966f30bbe7f0e872b1ef6a0d3f Mon Sep 17 00:00:00 2001
From: Mahesh Bodapati <mbodapat@xilinx.com>
Date: Tue, 11 Sep 2018 13:48:33 +0530
-Subject: [PATCH] negl instruction is overriding rsubl,fixed it by changing the
- instruction order...
-
-Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Subject: [PATCH 17/43] [Patch,Microblaze] : negl instruction is overriding
+ rsubl,fixed it by changing the instruction order...
---
opcodes/microblaze-opc.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index 9b6264b..824afc0 100644
+index 9b6264b61c..824afc0ab0 100644
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -275,9 +275,7 @@ struct op_code_struct
@@ -34,3 +31,6 @@
{"", 0, 0, 0, 0, 0, 0, 0, 0},
};
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0018-Added-relocations-for-MB-X.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0018-Added-relocations-for-MB-X.patch
similarity index 94%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0018-Added-relocations-for-MB-X.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0018-Added-relocations-for-MB-X.patch
index b98db22..99c5f62 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0018-Added-relocations-for-MB-X.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0018-Added-relocations-for-MB-X.patch
@@ -1,23 +1,20 @@
-From 6b6c4a67212ced3fe1593fb173cfc4bce8d7f922 Mon Sep 17 00:00:00 2001
+From 6d241a6865abf8196ba0cfa2aed7e847df087b6e Mon Sep 17 00:00:00 2001
From: Nagaraju Mekala <nmekala@xilix.com>
Date: Tue, 11 Sep 2018 17:30:17 +0530
-Subject: [PATCH] Added relocations for MB-X
-
-Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Subject: [PATCH 18/43] Added relocations for MB-X
---
- bfd/bfd-in2.h | 11 ++++--
- bfd/libbfd.h | 4 +--
- bfd/reloc.c | 26 +++++++-------
- gas/config/tc-microblaze.c | 90 ++++++++++++++++++++--------------------------
+ bfd/bfd-in2.h | 11 +++--
+ bfd/libbfd.h | 4 +-
+ bfd/reloc.c | 26 ++++++-----
+ gas/config/tc-microblaze.c | 90 ++++++++++++++++----------------------
4 files changed, 62 insertions(+), 69 deletions(-)
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
-index 90645d1..f74aac1 100644
+index 4f777059d8..de46e78902 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
-@@ -5873,16 +5873,21 @@ done here - only used for relaxing */
+@@ -5872,15 +5872,20 @@ done here - only used for relaxing */
BFD_RELOC_MICROBLAZE_32_NONE,
/* This is a 64 bit reloc that stores the 32 bit pc relative
@@ -33,17 +30,16 @@
* +done here - only used for relaxing */
BFD_RELOC_MICROBLAZE_64,
- /* This is a 64 bit reloc that stores the 32 bit pc relative
++/* This is a 64 bit reloc that stores the 32 bit pc relative
+ * +value in two words (with an imm instruction). No relocation is
+ * +done here - only used for relaxing */
+ BFD_RELOC_MICROBLAZE_64_NONE,
+
-+/* This is a 64 bit reloc that stores the 32 bit pc relative
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). The relocation is
PC-relative GOT offset */
- BFD_RELOC_MICROBLAZE_64_GOTPC,
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
-index 450653f..d87a183 100644
+index 450653f2d8..d87a183d5e 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -2903,14 +2903,14 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
@@ -64,35 +60,34 @@
"BFD_RELOC_MICROBLAZE_64_TLSGD",
"BFD_RELOC_MICROBLAZE_64_TLSLD",
diff --git a/bfd/reloc.c b/bfd/reloc.c
-index ccf29f5..861f2d4 100644
+index ccf29f54cf..861f2d48c0 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
-@@ -6804,12 +6804,6 @@ ENUMDOC
+@@ -6803,24 +6803,12 @@ ENUMDOC
+ done here - only used for relaxing
ENUM
BFD_RELOC_MICROBLAZE_64_NONE
- ENUMDOC
+-ENUMDOC
- This is a 32 bit reloc that stores the 32 bit pc relative
- value in two words (with an imml instruction). No relocation is
- done here - only used for relaxing
-ENUM
- BFD_RELOC_MICROBLAZE_64
--ENUMDOC
+ ENUMDOC
This is a 64 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). No relocation is
done here - only used for relaxing
-@@ -6817,12 +6811,6 @@ ENUM
+ ENUM
BFD_RELOC_MICROBLAZE_64_GOTPC
- ENUMDOC
- This is a 64 bit reloc that stores the 32 bit pc relative
+-ENUMDOC
+- This is a 64 bit reloc that stores the 32 bit pc relative
- value in two words (with an imml instruction). No relocation is
- done here - only used for relaxing
-ENUM
- BFD_RELOC_MICROBLAZE_64_GPC
--ENUMDOC
-- This is a 64 bit reloc that stores the 32 bit pc relative
+ ENUMDOC
+ This is a 64 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). The relocation is
- PC-relative GOT offset
- ENUM
@@ -6906,6 +6894,20 @@ ENUMDOC
value in two words (with an imm instruction). The relocation is
relative offset from start of TEXT.
@@ -115,7 +110,7 @@
BFD_RELOC_AARCH64_RELOC_START
ENUMDOC
diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index 3f90b7c..587a4d5 100644
+index 3f90b7c892..587a4d56ec 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -95,6 +95,7 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP";
@@ -346,3 +341,6 @@
case BFD_RELOC_MICROBLAZE_64_GOT:
case BFD_RELOC_MICROBLAZE_64_PLT:
case BFD_RELOC_MICROBLAZE_64_GOTOFF:
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0019-Fixed-MB-x-relocation-issues.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0019-Fixed-MB-x-relocation-issues.patch
similarity index 96%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0019-Fixed-MB-x-relocation-issues.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0019-Fixed-MB-x-relocation-issues.patch
index 55319ee..edbfac0 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0019-Fixed-MB-x-relocation-issues.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0019-Fixed-MB-x-relocation-issues.patch
@@ -1,20 +1,17 @@
-From 616031595c692c2181c3b1ce8c08678b68b2fe4e Mon Sep 17 00:00:00 2001
+From bb6c70cfa1402a685995103ac90e7ceeccdd0991 Mon Sep 17 00:00:00 2001
From: Nagaraju Mekala <nmekala@xilix.com>
Date: Fri, 28 Sep 2018 12:04:55 +0530
-Subject: [PATCH] -Fixed MB-x relocation issues -Added imml for required MB-x
- instructions
-
-Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Subject: [PATCH 19/43] -Fixed MB-x relocation issues -Added imml for required
+ MB-x instructions
---
- bfd/elf64-microblaze.c | 68 ++++++++++++++++----
- gas/config/tc-microblaze.c | 152 ++++++++++++++++++++++++++++++++-------------
+ bfd/elf64-microblaze.c | 68 ++++++++++++++---
+ gas/config/tc-microblaze.c | 152 +++++++++++++++++++++++++++----------
gas/tc.h | 2 +-
3 files changed, 167 insertions(+), 55 deletions(-)
diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index 56a45f2..54a2461 100644
+index 56a45f2a05..54a2461037 100644
--- a/bfd/elf64-microblaze.c
+++ b/bfd/elf64-microblaze.c
@@ -1476,8 +1476,17 @@ microblaze_elf_relocate_section (bfd *output_bfd,
@@ -116,7 +113,7 @@
instr_lo &= ~0x0000ffff;
instr_lo |= (val & 0x0000ffff);
diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index 587a4d5..fa437b6 100644
+index 587a4d56ec..fa437b6c98 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -392,7 +392,7 @@ microblaze_s_weakext (int ignore ATTRIBUTE_UNUSED)
@@ -359,7 +356,7 @@
default:
return 0;
diff --git a/gas/tc.h b/gas/tc.h
-index 0a50a69..529a73b 100644
+index 0a50a6985b..529a73b43b 100644
--- a/gas/tc.h
+++ b/gas/tc.h
@@ -22,7 +22,7 @@
@@ -371,3 +368,6 @@
const char * md_atof (int, char *, int *);
int md_parse_option (int, const char *);
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0020-Fixing-the-branch-related-issues.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0020-Fixing-the-branch-related-issues.patch
similarity index 67%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0020-Fixing-the-branch-related-issues.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0020-Fixing-the-branch-related-issues.patch
index 43a06d8..528c927 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0020-Fixing-the-branch-related-issues.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0020-Fixing-the-branch-related-issues.patch
@@ -1,17 +1,14 @@
-From 05cac23e0cdb94705c87cf9d94ffe00e7cba53f6 Mon Sep 17 00:00:00 2001
+From 8375ef893eb327ae4a5dc9207041ffc0e9bc6e2b Mon Sep 17 00:00:00 2001
From: Nagaraju Mekala <nmekala@xilix.com>
Date: Sun, 30 Sep 2018 17:06:58 +0530
-Subject: [PATCH] Fixing the branch related issues
-
-Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Subject: [PATCH 20/43] Fixing the branch related issues
---
bfd/elf64-microblaze.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index 54a2461..e9b3cf3 100644
+index 54a2461037..e9b3cf3a86 100644
--- a/bfd/elf64-microblaze.c
+++ b/bfd/elf64-microblaze.c
@@ -2532,7 +2532,7 @@ microblaze_elf_check_relocs (bfd * abfd,
@@ -23,3 +20,6 @@
}
switch (r_type)
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0021-Fixed-address-computation-issues-with-64bit-address.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0021-Fixed-address-computation-issues-with-64bit-address.patch
similarity index 92%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0021-Fixed-address-computation-issues-with-64bit-address.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0021-Fixed-address-computation-issues-with-64bit-address.patch
index b3aebb7..d62f0ed 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0021-Fixed-address-computation-issues-with-64bit-address.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0021-Fixed-address-computation-issues-with-64bit-address.patch
@@ -1,24 +1,21 @@
-From 8b98898add56667d28b7d6242c86603bb2f5946e Mon Sep 17 00:00:00 2001
+From 9f13e07180c09f814665676ac6c04cb7a2cd7c11 Mon Sep 17 00:00:00 2001
From: Nagaraju Mekala <nmekala@xilix.com>
Date: Tue, 9 Oct 2018 10:14:22 +0530
-Subject: [PATCH] - Fixed address computation issues with 64bit address - Fixed
- imml dissassamble issue
-
-Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Subject: [PATCH 21/43] - Fixed address computation issues with 64bit address -
+ Fixed imml dissassamble issue
---
- bfd/bfd-in2.h | 5 ++++
- bfd/elf64-microblaze.c | 14 ++++-----
- gas/config/tc-microblaze.c | 74 +++++++++++++++++++++++++++++++++++++++++-----
+ bfd/bfd-in2.h | 5 +++
+ bfd/elf64-microblaze.c | 14 ++++----
+ gas/config/tc-microblaze.c | 74 +++++++++++++++++++++++++++++++++-----
opcodes/microblaze-dis.c | 2 +-
4 files changed, 79 insertions(+), 16 deletions(-)
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
-index f74aac1..434b41c 100644
+index de46e78902..33c9cb62d9 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
-@@ -5882,6 +5882,11 @@ done here - only used for relaxing */
+@@ -5881,6 +5881,11 @@ done here - only used for relaxing */
* +done here - only used for relaxing */
BFD_RELOC_MICROBLAZE_64,
@@ -31,7 +28,7 @@
* +value in two words (with an imm instruction). No relocation is
* +done here - only used for relaxing */
diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index e9b3cf3..40f10aa 100644
+index e9b3cf3a86..40f10aac6d 100644
--- a/bfd/elf64-microblaze.c
+++ b/bfd/elf64-microblaze.c
@@ -121,15 +121,15 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
@@ -84,7 +81,7 @@
fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
}
diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index fa437b6..46df32e 100644
+index fa437b6c98..46df32e72f 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -402,7 +402,6 @@ pseudo_typeS md_pseudo_table[] =
@@ -95,10 +92,13 @@
{"weakext", microblaze_s_weakext, 0},
{"rodata", microblaze_s_rdata, 0},
{"sdata2", microblaze_s_rdata, 1},
-@@ -2482,15 +2481,71 @@ md_apply_fix (fixS * fixP,
- /* Don't do anything if the symbol is not defined. */
- if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
- {
+@@ -2479,18 +2478,74 @@ md_apply_fix (fixS * fixP,
+ case BFD_RELOC_RVA:
+ case BFD_RELOC_32_PCREL:
+ case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM:
++ /* Don't do anything if the symbol is not defined. */
++ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
++ {
+ if ((fixP->fx_r_type == BFD_RELOC_RVA) && (microblaze_arch_size == 64))
+ {
+ if (target_big_endian)
@@ -144,9 +144,9 @@
+ break;
+
+ case BFD_RELOC_MICROBLAZE_EA64:
-+ /* Don't do anything if the symbol is not defined. */
-+ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
-+ {
+ /* Don't do anything if the symbol is not defined. */
+ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
+ {
if (target_big_endian)
{
- buf[0] |= ((val >> 24) & 0xff);
@@ -203,7 +203,7 @@
default:
as_bad (_("unsupported BFD relocation size %u"), size);
diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
-index 20ea6a8..f679a43 100644
+index 20ea6a885a..f679a43606 100644
--- a/opcodes/microblaze-dis.c
+++ b/opcodes/microblaze-dis.c
@@ -61,7 +61,7 @@ get_field_imml (long instr)
@@ -215,3 +215,6 @@
return (strdup (tmpstr));
}
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0022-Adding-new-relocation-to-support-64bit-rodata.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0022-Adding-new-relocation-to-support-64bit-rodata.patch
similarity index 94%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0022-Adding-new-relocation-to-support-64bit-rodata.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0022-Adding-new-relocation-to-support-64bit-rodata.patch
index aec793d..ec82926 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0022-Adding-new-relocation-to-support-64bit-rodata.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0022-Adding-new-relocation-to-support-64bit-rodata.patch
@@ -1,18 +1,15 @@
-From 3eb0c068ad5a698007341b32c82d9e7ac6cabc49 Mon Sep 17 00:00:00 2001
+From beeceebb05a4eeaeca697f4ba7e214485b10369a Mon Sep 17 00:00:00 2001
From: Nagaraju Mekala <nmekala@xilix.com>
Date: Sat, 13 Oct 2018 21:17:01 +0530
-Subject: [PATCH] Adding new relocation to support 64bit rodata
-
-Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Subject: [PATCH 22/43] Adding new relocation to support 64bit rodata
---
- bfd/elf64-microblaze.c | 11 +++++++++--
- gas/config/tc-microblaze.c | 49 ++++++++++++++++++++++++++++++++++++++++++----
+ bfd/elf64-microblaze.c | 11 +++++++--
+ gas/config/tc-microblaze.c | 49 ++++++++++++++++++++++++++++++++++----
2 files changed, 54 insertions(+), 6 deletions(-)
diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index 40f10aa..4d9b906 100644
+index 40f10aac6d..4d9b90647f 100644
--- a/bfd/elf64-microblaze.c
+++ b/bfd/elf64-microblaze.c
@@ -1461,6 +1461,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
@@ -69,7 +66,7 @@
if (h != NULL && !bfd_link_pic (info))
{
diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index 46df32e..c6d2e4c 100644
+index 46df32e72f..c6d2e4c82d 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -1119,6 +1119,13 @@ md_assemble (char * str)
@@ -164,3 +161,6 @@
break;
default:
as_bad (_("unsupported BFD relocation size %u"), size);
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0023-fixing-the-.bss-relocation-issue.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0023-fixing-the-.bss-relocation-issue.patch
similarity index 92%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0023-fixing-the-.bss-relocation-issue.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0023-fixing-the-.bss-relocation-issue.patch
index cd54cae..d1ec5db 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0023-fixing-the-.bss-relocation-issue.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0023-fixing-the-.bss-relocation-issue.patch
@@ -1,17 +1,14 @@
-From 52f6c56353aad424dfdaf713e0192f8fc9c874f4 Mon Sep 17 00:00:00 2001
+From 3f031961082caec9e172ff0224a51c08ab6e19c3 Mon Sep 17 00:00:00 2001
From: Nagaraju Mekala <nmekala@xilix.com>
Date: Wed, 24 Oct 2018 12:34:37 +0530
-Subject: [PATCH] fixing the .bss relocation issue
-
-Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Subject: [PATCH 23/43] fixing the .bss relocation issue
---
bfd/elf64-microblaze.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index 4d9b906..184b7d5 100644
+index 4d9b90647f..184b7d560d 100644
--- a/bfd/elf64-microblaze.c
+++ b/bfd/elf64-microblaze.c
@@ -1480,7 +1480,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
@@ -74,3 +71,6 @@
immediate |= (instr_lo & 0x0000ffff);
target_address = immediate;
offset = calc_fixup (target_address, 0, sec);
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0024-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0024-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch
similarity index 80%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0024-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0024-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch
index a4f8257..2075293 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0024-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0024-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch
@@ -1,11 +1,8 @@
-From ed3e6fad3e2a626fc987e9c7477f51d03d2b4512 Mon Sep 17 00:00:00 2001
+From 843b73643718b0776462bce6aba6b2c6fdb33d85 Mon Sep 17 00:00:00 2001
From: Nagaraju Mekala <nmekala@xilix.com>
Date: Wed, 28 Nov 2018 14:00:29 +0530
-Subject: [PATCH] Fixed the bug in the R_MICROBLAZE_64_NONE relocation. It was
- adjusting only lower 16bits.
-
-Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Subject: [PATCH 24/43] Fixed the bug in the R_MICROBLAZE_64_NONE relocation.
+ It was adjusting only lower 16bits.
---
bfd/elf32-microblaze.c | 4 ++--
@@ -13,7 +10,7 @@
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index 035e71f..2d8c062 100644
+index 035e71f311..2d8c062a42 100644
--- a/bfd/elf32-microblaze.c
+++ b/bfd/elf32-microblaze.c
@@ -2022,8 +2022,8 @@ microblaze_elf_relax_section (bfd *abfd,
@@ -28,7 +25,7 @@
break;
}
diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index 184b7d5..ef6a870 100644
+index 184b7d560d..ef6a87062b 100644
--- a/bfd/elf64-microblaze.c
+++ b/bfd/elf64-microblaze.c
@@ -2017,8 +2017,8 @@ microblaze_elf_relax_section (bfd *abfd,
@@ -42,3 +39,6 @@
}
break;
}
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0025-Patch-MicroBlaze-fixed-Build-issue-which-are-due-to-.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0025-Patch-MicroBlaze-fixed-Build-issue-which-are-due-to-.patch
similarity index 88%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0025-Patch-MicroBlaze-fixed-Build-issue-which-are-due-to-.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0025-Patch-MicroBlaze-fixed-Build-issue-which-are-due-to-.patch
index fec19b6..5017978 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0025-Patch-MicroBlaze-fixed-Build-issue-which-are-due-to-.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0025-Patch-MicroBlaze-fixed-Build-issue-which-are-due-to-.patch
@@ -1,10 +1,8 @@
-From b8bd638f71649980e114548d8eeecba34683af42 Mon Sep 17 00:00:00 2001
+From 3a5e6a9c614c3f6abcf8bf853527ef07a5370f80 Mon Sep 17 00:00:00 2001
From: Mahesh Bodapati <mbodapat@xilinx.com>
Date: Sun, 2 Dec 2018 14:49:14 +0530
-Subject: [PATCH] fixed Build issue which are due to conflicts in patches.
-
-Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Subject: [PATCH 25/43] [Patch,MicroBlaze]: fixed Build issue which are due to
+ conflicts in patches.
---
bfd/elf32-microblaze.c | 1 +
@@ -13,7 +11,7 @@
3 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index 2d8c062..6a795c5 100644
+index 2d8c062a42..6a795c5069 100644
--- a/bfd/elf32-microblaze.c
+++ b/bfd/elf32-microblaze.c
@@ -1996,6 +1996,7 @@ microblaze_elf_relax_section (bfd *abfd,
@@ -25,7 +23,7 @@
target_address = irel->r_addend + irel->r_offset;
sfix = calc_fixup (irel->r_offset, 0, sec);
diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index ef6a870..bed534e 100644
+index ef6a87062b..bed534e7dd 100644
--- a/bfd/elf64-microblaze.c
+++ b/bfd/elf64-microblaze.c
@@ -2854,14 +2854,14 @@ microblaze_elf_adjust_dynamic_symbol (struct bfd_link_info *info,
@@ -50,7 +48,7 @@
/* This is a reference to a symbol defined by a dynamic object which
is not a function. */
diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index c6d2e4c..b3e49f0 100644
+index c6d2e4c82d..b3e49f0cf0 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -118,9 +118,9 @@ const relax_typeS md_relax_table[] =
@@ -65,3 +63,6 @@
{ 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE*2, 0 } /* 20: DEFINED_64_PC_OFFSET. */
};
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0026-Patch-Microblaze-changes-of-PR22458-failure-to-choos.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0026-Patch-Microblaze-changes-of-PR22458-failure-to-choos.patch
similarity index 65%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0026-Patch-Microblaze-changes-of-PR22458-failure-to-choos.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0026-Patch-Microblaze-changes-of-PR22458-failure-to-choos.patch
index cd6965d..aef46b3 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0026-Patch-Microblaze-changes-of-PR22458-failure-to-choos.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0026-Patch-Microblaze-changes-of-PR22458-failure-to-choos.patch
@@ -1,19 +1,16 @@
-From cbe98e5a0cbc2337bf25d6b3f9dabcae38b95952 Mon Sep 17 00:00:00 2001
+From e7f43c3afe90faa42c09f368671972c26c2b7b38 Mon Sep 17 00:00:00 2001
From: Mahesh Bodapati <mbodapat@xilinx.com>
Date: Tue, 26 Feb 2019 17:31:41 +0530
-Subject: [PATCH] changes of "PR22458, failure to choose a matching ELF target"
- is causing "Multiple Prevailing definition errors",added check for best_match
- elf.
-
-Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Subject: [PATCH 26/43] [Patch,Microblaze] : changes of "PR22458, failure to
+ choose a matching ELF target" is causing "Multiple Prevailing definition
+ errors",added check for best_match elf.
---
bfd/format.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/bfd/format.c b/bfd/format.c
-index 97a9229..3a74cc4 100644
+index 97a92291a8..3a74cc49d2 100644
--- a/bfd/format.c
+++ b/bfd/format.c
@@ -292,7 +292,12 @@ bfd_check_format_matches (bfd *abfd, bfd_format format, char ***matching)
@@ -29,3 +26,6 @@
continue;
/* If we already tried a match, the bfd is modified and may
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0027-Revert-ld-Remove-unused-expression-state.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0027-Revert-ld-Remove-unused-expression-state.patch
new file mode 100644
index 0000000..b0fe823
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0027-Revert-ld-Remove-unused-expression-state.patch
@@ -0,0 +1,76 @@
+From 69b77a73f4e609883cd7a0946b407becd46bf918 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 27 Feb 2019 15:12:32 +0530
+Subject: [PATCH 27/43] Revert "ld: Remove unused expression state"
+
+This reverts commit 65f14869fd3fbee8ed4c4ca49de8aaa86dbc66cb.
+
+Conflicts:
+ ld/ChangeLog
+---
+ ld/ldexp.c | 8 +++++---
+ ld/ldexp.h | 1 +
+ 2 files changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/ld/ldexp.c b/ld/ldexp.c
+index 60b17ef576..dac4b52450 100644
+--- a/ld/ldexp.c
++++ b/ld/ldexp.c
+@@ -1354,6 +1354,7 @@ static etree_type *
+ exp_assop (const char *dst,
+ etree_type *src,
+ enum node_tree_enum class,
++ bfd_boolean defsym,
+ bfd_boolean hidden)
+ {
+ etree_type *n;
+@@ -1365,6 +1366,7 @@ exp_assop (const char *dst,
+ n->assign.type.node_class = class;
+ n->assign.src = src;
+ n->assign.dst = dst;
++ n->assign.defsym = defsym;
+ n->assign.hidden = hidden;
+ return n;
+ }
+@@ -1374,7 +1376,7 @@ exp_assop (const char *dst,
+ etree_type *
+ exp_assign (const char *dst, etree_type *src, bfd_boolean hidden)
+ {
+- return exp_assop (dst, src, etree_assign, hidden);
++ return exp_assop (dst, src, etree_assign, FALSE, hidden);
+ }
+
+ /* Handle --defsym command-line option. */
+@@ -1382,7 +1384,7 @@ exp_assign (const char *dst, etree_type *src, bfd_boolean hidden)
+ etree_type *
+ exp_defsym (const char *dst, etree_type *src)
+ {
+- return exp_assop (dst, src, etree_assign, FALSE);
++ return exp_assop (dst, src, etree_assign, TRUE, FALSE);
+ }
+
+ /* Handle PROVIDE. */
+@@ -1390,7 +1392,7 @@ exp_defsym (const char *dst, etree_type *src)
+ etree_type *
+ exp_provide (const char *dst, etree_type *src, bfd_boolean hidden)
+ {
+- return exp_assop (dst, src, etree_provide, hidden);
++ return exp_assop (dst, src, etree_provide, FALSE, hidden);
+ }
+
+ /* Handle ASSERT. */
+diff --git a/ld/ldexp.h b/ld/ldexp.h
+index 71395bc6c4..f94b00aedb 100644
+--- a/ld/ldexp.h
++++ b/ld/ldexp.h
+@@ -66,6 +66,7 @@ typedef union etree_union {
+ node_type type;
+ const char *dst;
+ union etree_union *src;
++ bfd_boolean defsym;
+ bfd_boolean hidden;
+ } assign;
+ struct {
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0029-Patch-Microblaze-Binutils-security-check-is-causing-.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0028-Patch-Microblaze-Binutils-security-check-is-causing-.patch
similarity index 70%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0029-Patch-Microblaze-Binutils-security-check-is-causing-.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0028-Patch-Microblaze-Binutils-security-check-is-causing-.patch
index f293f5c..0fd14f6 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0029-Patch-Microblaze-Binutils-security-check-is-causing-.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0028-Patch-Microblaze-Binutils-security-check-is-causing-.patch
@@ -1,18 +1,15 @@
-From b1e425aed65150d7ce9ddb119f4b94969fe4043e Mon Sep 17 00:00:00 2001
+From 282a60ab92e6705853dac30fd38aaf298d7f02b0 Mon Sep 17 00:00:00 2001
From: Mahesh Bodapati <mbodapat@xilinx.com>
Date: Mon, 11 Mar 2019 14:23:58 +0530
-Subject: [PATCH] Binutils security check is causing build error for windows
- builds.commenting for now.
-
-Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Subject: [PATCH 28/43] [Patch,Microblaze] : Binutils security check is causing
+ build error for windows builds.commenting for now.
---
bfd/elf-attrs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/bfd/elf-attrs.c b/bfd/elf-attrs.c
-index bfe135e..feb5cb3 100644
+index bfe135e7fb..feb5cb37f5 100644
--- a/bfd/elf-attrs.c
+++ b/bfd/elf-attrs.c
@@ -440,6 +440,7 @@ _bfd_elf_parse_attributes (bfd *abfd, Elf_Internal_Shdr * hdr)
@@ -31,3 +28,6 @@
contents = (bfd_byte *) bfd_malloc (hdr->sh_size + 1);
if (!contents)
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0030-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0029-fixing-the-long-long-long-mingw-toolchain-issue.patch
similarity index 86%
rename from meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0030-fixing-the-long-long-long-mingw-toolchain-issue.patch
rename to meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0029-fixing-the-long-long-long-mingw-toolchain-issue.patch
index 7e3acca..dbafc78 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0030-fixing-the-long-long-long-mingw-toolchain-issue.patch
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0029-fixing-the-long-long-long-mingw-toolchain-issue.patch
@@ -1,10 +1,7 @@
-From 1eec84c155aeaeead673310f83293853f01b578d Mon Sep 17 00:00:00 2001
+From 26662110955e26c62629f4263a999216dac326ef Mon Sep 17 00:00:00 2001
From: Nagaraju Mekala <nmekala@xilix.com>
Date: Thu, 29 Nov 2018 17:59:25 +0530
-Subject: [PATCH] fixing the long & long long mingw toolchain issue
-
-Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
-Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Subject: [PATCH 29/43] fixing the long & long long mingw toolchain issue
---
gas/config/tc-microblaze.c | 10 +++++-----
@@ -12,7 +9,7 @@
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index b3e49f0..5b506d3 100644
+index b3e49f0cf0..5b506d3348 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -783,7 +783,7 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max)
@@ -41,7 +38,7 @@
if (atp)
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index 824afc0..d59ee0a 100644
+index 824afc0ab0..d59ee0a95f 100644
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -585,8 +585,8 @@ char pvr_register_prefix[] = "rpvr";
@@ -55,3 +52,6 @@
#endif /* MICROBLAZE_OPC */
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0030-Added-support-to-new-arithmetic-single-register-inst.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0030-Added-support-to-new-arithmetic-single-register-inst.patch
new file mode 100644
index 0000000..8141095
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0030-Added-support-to-new-arithmetic-single-register-inst.patch
@@ -0,0 +1,359 @@
+From 7b332d61cb3dbcae69021ce706f2c408c85af193 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Fri, 23 Aug 2019 16:18:43 +0530
+Subject: [PATCH 30/43] Added support to new arithmetic single register
+ instructions
+
+---
+ gas/config/tc-microblaze.c | 147 ++++++++++++++++++++++++++++++++++++-
+ opcodes/microblaze-dis.c | 12 +++
+ opcodes/microblaze-opc.h | 43 ++++++++++-
+ opcodes/microblaze-opcm.h | 5 +-
+ 4 files changed, 201 insertions(+), 6 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 5b506d3348..12eef24a29 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -423,12 +423,33 @@ void
+ md_begin (void)
+ {
+ struct op_code_struct * opcode;
++ const char *prev_name = "";
+
+ opcode_hash_control = hash_new ();
+
+ /* Insert unique names into hash table. */
+- for (opcode = opcodes; opcode->name; opcode ++)
+- hash_insert (opcode_hash_control, opcode->name, (char *) opcode);
++ for (opcode = (struct opcodes *)opcodes; opcode->name; opcode ++)
++ {
++ if (strcmp (prev_name, opcode->name))
++ {
++ prev_name = (char *) opcode->name;
++ hash_insert (opcode_hash_control, opcode->name, (char *) opcode);
++ }
++ }
++}
++
++static int
++is_reg (char * s)
++{
++ int is_reg = 0;
++ /* Strip leading whitespace. */
++ while (ISSPACE (* s))
++ ++ s;
++ if (TOLOWER (s[0]) == 'r')
++ {
++ is_reg =1;
++ }
++ return is_reg;
+ }
+
+ /* Try to parse a reg name. */
+@@ -986,6 +1007,7 @@ md_assemble (char * str)
+ {
+ char * op_start;
+ char * op_end;
++ char * temp_op_end;
+ struct op_code_struct * opcode, *opcode1;
+ char * output = NULL;
+ int nlen = 0;
+@@ -996,9 +1018,10 @@ md_assemble (char * str)
+ unsigned reg3;
+ unsigned isize;
+ unsigned long immed, immed2, temp;
+- expressionS exp;
++ expressionS exp,exp1;
+ char name[20];
+ long immedl;
++ int reg=0;
+
+ /* Drop leading whitespace. */
+ while (ISSPACE (* str))
+@@ -1029,7 +1052,78 @@ md_assemble (char * str)
+ as_bad (_("unknown opcode \"%s\""), name);
+ return;
+ }
+-
++
++ if ((microblaze_arch_size == 64) && (streq (name, "addli") || streq (name, "addlic") ||
++ streq (name, "addlik") || streq (name, "addlikc") || streq (name, "rsubli")
++ || streq (name, "rsublic") || streq (name, "rsublik") || streq (name, "rsublikc")
++ || streq (name, "andli") || streq (name, "andnli") || streq (name, "orli")
++ || streq (name, "xorli")))
++ {
++ temp_op_end = op_end;
++ if (strcmp (temp_op_end, ""))
++ temp_op_end = parse_reg (temp_op_end + 1, ®1); /* Get rd. */
++ if (strcmp (temp_op_end, ""))
++ reg = is_reg (temp_op_end + 1);
++ if (reg)
++ {
++
++ opcode->inst_type=INST_TYPE_RD_R1_IMML;
++ opcode->inst_offset_type = OPCODE_MASK_H;
++ if (streq (name, "addli"))
++ opcode->bit_sequence = ADDLI_MASK;
++ else if (streq (name, "addlic"))
++ opcode->bit_sequence = ADDLIC_MASK;
++ else if (streq (name, "addlik"))
++ opcode->bit_sequence = ADDLIK_MASK;
++ else if (streq (name, "addlikc"))
++ opcode->bit_sequence = ADDLIKC_MASK;
++ else if (streq (name, "rsubli"))
++ opcode->bit_sequence = RSUBLI_MASK;
++ else if (streq (name, "rsublic"))
++ opcode->bit_sequence = RSUBLIC_MASK;
++ else if (streq (name, "rsublik"))
++ opcode->bit_sequence = RSUBLIK_MASK;
++ else if (streq (name, "rsublikc"))
++ opcode->bit_sequence = RSUBLIKC_MASK;
++ else if (streq (name, "andli"))
++ opcode->bit_sequence = ANDLI_MASK;
++ else if (streq (name, "andnli"))
++ opcode->bit_sequence = ANDLNI_MASK;
++ else if (streq (name, "orli"))
++ opcode->bit_sequence = ORLI_MASK;
++ else if (streq (name, "xorli"))
++ opcode->bit_sequence = XORLI_MASK;
++ }
++ else
++ {
++ opcode->inst_type=INST_TYPE_RD_IMML;
++ opcode->inst_offset_type = OPCODE_MASK_LIMM;
++ if (streq (name, "addli"))
++ opcode->bit_sequence = ADDLI_ONE_REG_MASK;
++ else if (streq (name, "addlic"))
++ opcode->bit_sequence = ADDLIC_ONE_REG_MASK;
++ else if (streq (name, "addlik"))
++ opcode->bit_sequence = ADDLIK_ONE_REG_MASK;
++ else if (streq (name, "addlikc"))
++ opcode->bit_sequence = ADDLIKC_ONE_REG_MASK;
++ else if (streq (name, "rsubli"))
++ opcode->bit_sequence = RSUBLI_ONE_REG_MASK;
++ else if (streq (name, "rsublic"))
++ opcode->bit_sequence = RSUBLIC_ONE_REG_MASK;
++ else if (streq (name, "rsublik"))
++ opcode->bit_sequence = RSUBLIK_ONE_REG_MASK;
++ else if (streq (name, "rsublikc"))
++ opcode->bit_sequence = RSUBLIKC_ONE_REG_MASK;
++ else if (streq (name, "andli"))
++ opcode->bit_sequence = ANDLI_ONE_REG_MASK;
++ else if (streq (name, "andnli"))
++ opcode->bit_sequence = ANDLNI_ONE_REG_MASK;
++ else if (streq (name, "orli"))
++ opcode->bit_sequence = ORLI_ONE_REG_MASK;
++ else if (streq (name, "xorli"))
++ opcode->bit_sequence = XORLI_ONE_REG_MASK;
++ }
++ }
+ inst = opcode->bit_sequence;
+ isize = 4;
+
+@@ -1480,6 +1574,51 @@ md_assemble (char * str)
+ inst |= (immed << IMM_LOW) & IMM15_MASK;
+ break;
+
++ case INST_TYPE_RD_IMML:
++ if (strcmp (op_end, ""))
++ op_end = parse_reg (op_end + 1, ®1); /* Get rd. */
++ else
++ {
++ as_fatal (_("Error in statement syntax"));
++ reg1 = 0;
++ }
++
++ if (strcmp (op_end, ""))
++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
++ else
++ as_fatal (_("Error in statement syntax"));
++
++ /* Check for spl registers. */
++ if (check_spl_reg (®1))
++ as_fatal (_("Cannot use special register with this instruction"));
++ if (exp.X_op != O_constant)
++ {
++ char *opc = NULL;
++ relax_substateT subtype;
++
++ if (exp.X_md != 0)
++ subtype = get_imm_otype(exp.X_md);
++ else
++ subtype = opcode->inst_offset_type;
++
++ output = frag_var (rs_machine_dependent,
++ isize * 2,
++ isize * 2,
++ subtype,
++ exp.X_add_symbol,
++ exp.X_add_number,
++ (char *) opc);
++ immedl = 0L;
++ }
++ else
++ {
++ output = frag_more (isize);
++ immed = exp.X_add_number;
++ }
++ inst |= (reg1 << RD_LOW) & RD_MASK;
++ inst |= (immed << IMM_LOW) & IMM16_MASK;
++ break;
++
+ case INST_TYPE_R1_RFSL:
+ if (strcmp (op_end, ""))
+ op_end = parse_reg (op_end + 1, ®1); /* Get r1. */
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index f679a43606..e5e880cb1c 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -114,6 +114,15 @@ get_field_imm15 (long instr)
+ return (strdup (tmpstr));
+ }
+
++static char *
++get_field_imm16 (long instr)
++{
++ char tmpstr[25];
++
++ sprintf (tmpstr, "%d", (short)((instr & IMM16_MASK) >> IMM_LOW));
++ return (strdup (tmpstr));
++}
++
+ static char *
+ get_field_special (long instr, struct op_code_struct * op)
+ {
+@@ -419,6 +428,9 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+ case INST_TYPE_RD_IMM15:
+ print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_imm15 (inst));
+ break;
++ case INST_TYPE_RD_IMML:
++ print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_imm16 (inst));
++ break;
+ /* For mbar insn. */
+ case INST_TYPE_IMM5:
+ print_func (stream, "\t%s", get_field_imm5_mbar (inst));
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index d59ee0a95f..0774f70e08 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -69,6 +69,7 @@
+ #define INST_TYPE_RD_R1_IMMW_IMMS 21
+
+ #define INST_TYPE_NONE 25
++#define INST_TYPE_RD_IMML 26
+
+
+
+@@ -84,6 +85,7 @@
+ #define IMMVAL_MASK_MFS 0x0000
+
+ #define OPCODE_MASK_H 0xFC000000 /* High 6 bits only. */
++#define OPCODE_MASK_LIMM 0xFC1F0000 /* High 6 bits and 12-16 bits */
+ #define OPCODE_MASK_H1 0xFFE00000 /* High 11 bits. */
+ #define OPCODE_MASK_H2 0xFC1F0000 /* High 6 and bits 20-16. */
+ #define OPCODE_MASK_H12 0xFFFF0000 /* High 16. */
+@@ -106,6 +108,33 @@
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
+ #define OPCODE_MASK_H8 0xFF000000 /* High 8 bits only. */
+
++/*Defines to identify 64-bit single reg instructions */
++#define ADDLI_ONE_REG_MASK 0x68000000
++#define ADDLIC_ONE_REG_MASK 0x68020000
++#define ADDLIK_ONE_REG_MASK 0x68040000
++#define ADDLIKC_ONE_REG_MASK 0x68060000
++#define RSUBLI_ONE_REG_MASK 0x68010000
++#define RSUBLIC_ONE_REG_MASK 0x68030000
++#define RSUBLIK_ONE_REG_MASK 0x68050000
++#define RSUBLIKC_ONE_REG_MASK 0x68070000
++#define ORLI_ONE_REG_MASK 0x68100000
++#define ANDLI_ONE_REG_MASK 0x68110000
++#define XORLI_ONE_REG_MASK 0x68120000
++#define ANDLNI_ONE_REG_MASK 0x68130000
++#define ADDLI_MASK 0x20000000
++#define ADDLIC_MASK 0x28000000
++#define ADDLIK_MASK 0x30000000
++#define ADDLIKC_MASK 0x38000000
++#define RSUBLI_MASK 0x24000000
++#define RSUBLIC_MASK 0x2C000000
++#define RSUBLIK_MASK 0x34000000
++#define RSUBLIKC_MASK 0x3C000000
++#define ANDLI_MASK 0xA4000000
++#define ANDLNI_MASK 0xAC000000
++#define ORLI_MASK 0xA0000000
++#define XORLI_MASK 0xA8000000
++
++
+ /* New Mask for msrset, msrclr insns. */
+ #define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */
+ /* Mask for mbar insn. */
+@@ -114,7 +143,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+
+-#define MAX_OPCODES 412
++#define MAX_OPCODES 424
+
+ struct op_code_struct
+ {
+@@ -444,13 +473,21 @@ struct op_code_struct
+ {"cmpl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst },
+ {"cmplu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst },
+ {"addli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"addli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68000000, OPCODE_MASK_LIMM, addli, arithmetic_inst },
+ {"rsubli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"rsubli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68010000, OPCODE_MASK_LIMM, rsubli, arithmetic_inst },
+ {"addlic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"addlic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68020000, OPCODE_MASK_LIMM, addlic, arithmetic_inst },
+ {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"rsublic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68030000, OPCODE_MASK_LIMM, rsublic, arithmetic_inst },
+ {"addlik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"addlik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68040000, OPCODE_MASK_LIMM, addlik, arithmetic_inst },
+ {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"rsublik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68050000, OPCODE_MASK_LIMM, rsublik, arithmetic_inst },
+ {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"addlikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68060000, OPCODE_MASK_LIMM, addlikc, arithmetic_inst },
+ {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"rsublikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68070000, OPCODE_MASK_LIMM, rsublikc, arithmetic_inst },
+ {"mull", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst },
+ {"bslll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst },
+ {"bslra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst },
+@@ -501,9 +538,13 @@ struct op_code_struct
+ {"beaged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst },
+ {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst },
+ {"orli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
++ {"orli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68100000, OPCODE_MASK_LIMM, orli, arithmetic_inst },
+ {"andli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
++ {"andli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68110000, OPCODE_MASK_LIMM, andli, arithmetic_inst },
+ {"xorli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
++ {"xorli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68120000, OPCODE_MASK_LIMM, xorli, arithmetic_inst },
+ {"andnli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
++ {"andnli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68130000, OPCODE_MASK_LIMM, andnli, arithmetic_inst },
+ {"imml", INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst },
+ {"breai", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst },
+ {"breaid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 5f2e190d23..4d2ee2dd0d 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -61,7 +61,9 @@ enum microblaze_instr
+ eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
+
+ /* 64-bit instructions */
+- addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
++ addl, addli, addlic, addlik, addlikc, rsubl, rsubli, rsublic, rsublik, rsublikc,
++ addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
++ andli, andnli, orli, xorli,
+ bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl,
+ andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32,
+ brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned,
+@@ -166,5 +168,6 @@ enum microblaze_instr_type
+
+ /* Imm mask for msrset, msrclr instructions. */
+ #define IMM15_MASK 0x00007FFF
++#define IMM16_MASK 0x0000FFFF
+
+ #endif /* MICROBLAZE-OPCM */
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0031-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0031-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch
new file mode 100644
index 0000000..f9f0fc5
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0031-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch
@@ -0,0 +1,551 @@
+From 213df2cac38d404619614939de0c9d3dcbf7557d Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 26 Aug 2019 15:29:42 +0530
+Subject: [PATCH 31/43] [Patch,MicroBlaze] : double imml generation for 64 bit
+ values.
+
+---
+ gas/config/tc-microblaze.c | 322 ++++++++++++++++++++++++++++++-------
+ opcodes/microblaze-opc.h | 4 +-
+ 2 files changed, 263 insertions(+), 63 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 12eef24a29..3ff6a14baf 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -1008,7 +1008,7 @@ md_assemble (char * str)
+ char * op_start;
+ char * op_end;
+ char * temp_op_end;
+- struct op_code_struct * opcode, *opcode1;
++ struct op_code_struct * opcode, *opcode1, *opcode2;
+ char * output = NULL;
+ int nlen = 0;
+ int i;
+@@ -1192,7 +1192,12 @@ md_assemble (char * str)
+ reg2 = 0;
+ }
+ if (strcmp (op_end, ""))
++ {
++ if(microblaze_arch_size == 64)
++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
++ else
+ op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM);
++ }
+ else
+ as_fatal (_("Error in statement syntax"));
+
+@@ -1288,24 +1293,51 @@ md_assemble (char * str)
+ || streq (name, "lwi") || streq (name, "sbi")
+ || streq (name, "shi") || streq (name, "swi"))))
+ {
+- temp = immed & 0xFFFFFF8000;
+- if (temp != 0 && temp != 0xFFFFFF8000)
++ temp = ((long long)immed) & 0xFFFFFFFFFFFF8000;
++ if (temp != 0 && temp != 0xFFFFFFFFFFFF8000)
+ {
+ /* Needs an immediate inst. */
+- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
+- if (opcode1 == NULL)
++ if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887)
++ {
++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ if (opcode1 == NULL)
++ {
++ as_bad (_("unknown opcode \"%s\""), "imml");
++ return;
++ }
++ inst1 = opcode1->bit_sequence;
++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++ output[0] = INST_BYTE0 (inst1);
++ output[1] = INST_BYTE1 (inst1);
++ output[2] = INST_BYTE2 (inst1);
++ output[3] = INST_BYTE3 (inst1);
++ output = frag_more (isize);
++ }
++ else
++ {
++ opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ if (opcode1 == NULL || opcode2 == NULL)
+ {
+ as_bad (_("unknown opcode \"%s\""), "imml");
+ return;
+ }
++ inst1 = opcode2->bit_sequence;
++ inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
++ output[0] = INST_BYTE0 (inst1);
++ output[1] = INST_BYTE1 (inst1);
++ output[2] = INST_BYTE2 (inst1);
++ output[3] = INST_BYTE3 (inst1);
++ output = frag_more (isize);
+ inst1 = opcode1->bit_sequence;
+- inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
+ output[0] = INST_BYTE0 (inst1);
+ output[1] = INST_BYTE1 (inst1);
+ output[2] = INST_BYTE2 (inst1);
+ output[3] = INST_BYTE3 (inst1);
+ output = frag_more (isize);
+ }
++ }
+ inst |= (reg1 << RD_LOW) & RD_MASK;
+ inst |= (reg2 << RA_LOW) & RA_MASK;
+ inst |= (immed << IMM_LOW) & IMM_MASK;
+@@ -1316,14 +1348,13 @@ md_assemble (char * str)
+ if ((temp != 0) && (temp != 0xFFFF8000))
+ {
+ /* Needs an immediate inst. */
+- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
+ if (opcode1 == NULL)
+ {
+ as_bad (_("unknown opcode \"%s\""), "imm");
+ return;
+ }
+-
+- inst1 = opcode1->bit_sequence;
++ inst1 = opcode1->bit_sequence;
+ inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
+ output[0] = INST_BYTE0 (inst1);
+ output[1] = INST_BYTE1 (inst1);
+@@ -1564,7 +1595,7 @@ md_assemble (char * str)
+ as_fatal (_("Cannot use special register with this instruction"));
+
+ if (exp.X_op != O_constant)
+- as_fatal (_("Symbol used as immediate value for msrset/msrclr instructions"));
++ as_fatal (_("Symbol used as immediate value for arithmetic long instructions"));
+ else
+ {
+ output = frag_more (isize);
+@@ -1898,8 +1929,9 @@ md_assemble (char * str)
+ temp = immed & 0xFFFF8000;
+ if ((temp != 0) && (temp != 0xFFFF8000))
+ {
++
+ /* Needs an immediate inst. */
+- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
+ if (opcode1 == NULL)
+ {
+ as_bad (_("unknown opcode \"%s\""), "imm");
+@@ -1928,7 +1960,12 @@ md_assemble (char * str)
+ reg1 = 0;
+ }
+ if (strcmp (op_end, ""))
++ {
++ if(microblaze_arch_size == 64)
++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
++ else
+ op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM);
++ }
+ else
+ as_fatal (_("Error in statement syntax"));
+
+@@ -1967,30 +2004,55 @@ md_assemble (char * str)
+ }
+ if (streq (name, "brealid") || streq (name, "breaid") || streq (name, "breai"))
+ {
+- temp = immed & 0xFFFFFF8000;
+- if (temp != 0 && temp != 0xFFFFFF8000)
++ temp = ((long long)immed) & 0xFFFFFFFFFFFF8000;
++ if (temp != 0 && temp != 0xFFFFFFFFFFFF8000)
+ {
+ /* Needs an immediate inst. */
+- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887)
++ {
++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
+ if (opcode1 == NULL)
+ {
+ as_bad (_("unknown opcode \"%s\""), "imml");
+ return;
+ }
+ inst1 = opcode1->bit_sequence;
+- inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
+ output[0] = INST_BYTE0 (inst1);
+ output[1] = INST_BYTE1 (inst1);
+ output[2] = INST_BYTE2 (inst1);
+ output[3] = INST_BYTE3 (inst1);
+ output = frag_more (isize);
+ }
++ else {
++ opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ if (opcode1 == NULL || opcode2 == NULL)
++ {
++ as_bad (_("unknown opcode \"%s\""), "imml");
++ return;
++ }
++ inst1 = opcode2->bit_sequence;
++ inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
++ output[0] = INST_BYTE0 (inst1);
++ output[1] = INST_BYTE1 (inst1);
++ output[2] = INST_BYTE2 (inst1);
++ output[3] = INST_BYTE3 (inst1);
++ output = frag_more (isize);
++ inst1 = opcode1->bit_sequence;
++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++ output[0] = INST_BYTE0 (inst1);
++ output[1] = INST_BYTE1 (inst1);
++ output[2] = INST_BYTE2 (inst1);
++ output[3] = INST_BYTE3 (inst1);
++ output = frag_more (isize);
++ }
++ }
+ inst |= (reg1 << RD_LOW) & RD_MASK;
+ inst |= (immed << IMM_LOW) & IMM_MASK;
+ }
+ else
+ {
+-
+ temp = immed & 0xFFFF8000;
+ if ((temp != 0) && (temp != 0xFFFF8000))
+ {
+@@ -2076,25 +2138,50 @@ md_assemble (char * str)
+ streq (name, "breaid") ||
+ streq (name, "brai") || streq (name, "braid")))
+ {
+- temp = immed & 0xFFFFFF8000;
++ temp = immed & 0xFFFFFFFFFFFF8000;
+ if (temp != 0)
+ {
+ /* Needs an immediate inst. */
+- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887)
++ {
++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
+ if (opcode1 == NULL)
+ {
+ as_bad (_("unknown opcode \"%s\""), "imml");
+ return;
+ }
+-
+ inst1 = opcode1->bit_sequence;
+- inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++ output[0] = INST_BYTE0 (inst1);
++ output[1] = INST_BYTE1 (inst1);
++ output[2] = INST_BYTE2 (inst1);
++ output[3] = INST_BYTE3 (inst1);
++ output = frag_more (isize);
++ }
++ else {
++ opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ if (opcode1 == NULL || opcode2 == NULL)
++ {
++ as_bad (_("unknown opcode \"%s\""), "imml");
++ return;
++ }
++ inst1 = opcode2->bit_sequence;
++ inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
++ output[0] = INST_BYTE0 (inst1);
++ output[1] = INST_BYTE1 (inst1);
++ output[2] = INST_BYTE2 (inst1);
++ output[3] = INST_BYTE3 (inst1);
++ output = frag_more (isize);
++ inst1 = opcode1->bit_sequence;
++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
+ output[0] = INST_BYTE0 (inst1);
+ output[1] = INST_BYTE1 (inst1);
+ output[2] = INST_BYTE2 (inst1);
+ output[3] = INST_BYTE3 (inst1);
+ output = frag_more (isize);
+ }
++ }
+ inst |= (immed << IMM_LOW) & IMM_MASK;
+ }
+ else
+@@ -2194,21 +2281,45 @@ md_assemble (char * str)
+ {
+ output = frag_more (isize);
+ immedl = exp.X_add_number;
+-
+- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
+- if (opcode1 == NULL)
+- {
+- as_bad (_("unknown opcode \"%s\""), "imml");
+- return;
+- }
+-
+- inst1 = opcode1->bit_sequence;
+- inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
+- output[0] = INST_BYTE0 (inst1);
+- output[1] = INST_BYTE1 (inst1);
+- output[2] = INST_BYTE2 (inst1);
+- output[3] = INST_BYTE3 (inst1);
+- output = frag_more (isize);
++ if (((long long)immedl) > (long long)-549755813888 && ((long long)immedl) < (long long)549755813887)
++ {
++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ if (opcode1 == NULL)
++ {
++ as_bad (_("unknown opcode \"%s\""), "imml");
++ return;
++ }
++ inst1 = opcode1->bit_sequence;
++ inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++ output[0] = INST_BYTE0 (inst1);
++ output[1] = INST_BYTE1 (inst1);
++ output[2] = INST_BYTE2 (inst1);
++ output[3] = INST_BYTE3 (inst1);
++ output = frag_more (isize);
++ }
++ else {
++ opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ if (opcode2 == NULL || opcode1 == NULL)
++ {
++ as_bad (_("unknown opcode \"%s\""), "imml");
++ return;
++ }
++ inst1 = opcode2->bit_sequence;
++ inst1 |= ((immedl & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
++ output[0] = INST_BYTE0 (inst1);
++ output[1] = INST_BYTE1 (inst1);
++ output[2] = INST_BYTE2 (inst1);
++ output[3] = INST_BYTE3 (inst1);
++ output = frag_more (isize);
++ inst1 = opcode1->bit_sequence;
++ inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++ output[0] = INST_BYTE0 (inst1);
++ output[1] = INST_BYTE1 (inst1);
++ output[2] = INST_BYTE2 (inst1);
++ output[3] = INST_BYTE3 (inst1);
++ output = frag_more (isize);
++ }
+ }
+
+ inst |= (reg1 << RD_LOW) & RD_MASK;
+@@ -2257,21 +2368,46 @@ md_assemble (char * str)
+ {
+ output = frag_more (isize);
+ immedl = exp.X_add_number;
+- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
+- if (opcode1 == NULL)
+- {
+- as_bad (_("unknown opcode \"%s\""), "imml");
+- return;
+- }
+-
++ if (((long long)immedl) > (long long)-549755813888 && ((long long)immedl) < (long long)549755813887)
++ {
++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ if (opcode1 == NULL)
++ {
++ as_bad (_("unknown opcode \"%s\""), "imml");
++ return;
++ }
++ inst1 = opcode1->bit_sequence;
++ inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++ output[0] = INST_BYTE0 (inst1);
++ output[1] = INST_BYTE1 (inst1);
++ output[2] = INST_BYTE2 (inst1);
++ output[3] = INST_BYTE3 (inst1);
++ output = frag_more (isize);
++ }
++ else {
++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ if (opcode2 == NULL || opcode1 == NULL)
++ {
++ as_bad (_("unknown opcode \"%s\""), "imml");
++ return;
++ }
++ inst1 = opcode2->bit_sequence;
++ inst1 |= ((immedl & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
++ output[0] = INST_BYTE0 (inst1);
++ output[1] = INST_BYTE1 (inst1);
++ output[2] = INST_BYTE2 (inst1);
++ output[3] = INST_BYTE3 (inst1);
++ output = frag_more (isize);
+ inst1 = opcode1->bit_sequence;
+- inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++ inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
+ output[0] = INST_BYTE0 (inst1);
+ output[1] = INST_BYTE1 (inst1);
+ output[2] = INST_BYTE2 (inst1);
+ output[3] = INST_BYTE3 (inst1);
+ output = frag_more (isize);
+ }
++ }
+
+ inst |= (reg1 << RA_LOW) & RA_MASK;
+ inst |= (immedl << IMM_LOW) & IMM_MASK;
+@@ -2554,8 +2690,8 @@ md_apply_fix (fixS * fixP,
+ /* Note: use offsetT because it is signed, valueT is unsigned. */
+ offsetT val = (offsetT) * valp;
+ int i;
+- struct op_code_struct * opcode1;
+- unsigned long inst1;
++ struct op_code_struct * opcode1, * opcode2;
++ unsigned long inst1,inst2;
+
+ symname = fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : _("<unknown>");
+
+@@ -2739,30 +2875,75 @@ md_apply_fix (fixS * fixP,
+ case BFD_RELOC_MICROBLAZE_64_TEXTREL:
+ case BFD_RELOC_MICROBLAZE_64:
+ case BFD_RELOC_MICROBLAZE_64_PCREL:
+- /* Add an imm instruction. First save the current instruction. */
+- for (i = 0; i < INST_WORD_SIZE; i++)
+- buf[i + INST_WORD_SIZE] = buf[i];
+ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64
+ || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
+ {
+ /* Generate the imm instruction. */
++ if (((long long)val) > (long long)-549755813888 && ((long long)val) < (long long)549755813887)
++ {
++ /* Add an imm instruction. First save the current instruction. */
++ for (i = 0; i < INST_WORD_SIZE; i++)
++ buf[i + INST_WORD_SIZE] = buf[i];
+ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
+ if (opcode1 == NULL)
+- {
+- as_bad (_("unknown opcode \"%s\""), "imml");
+- return;
+- }
++ {
++ as_bad (_("unknown opcode \"%s\""), "imml");
++ return;
++ }
+
+ inst1 = opcode1->bit_sequence;
+ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
+- inst1 |= ((val & 0xFFFFFF0000L) >> 16) & IMML_MASK;
++ inst1 |= ((val & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
++ fixP->fx_r_type = BFD_RELOC_64;
++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
++ fixP->fx_r_type = BFD_RELOC_64_PCREL;
++ buf[0] = INST_BYTE0 (inst1);
++ buf[1] = INST_BYTE1 (inst1);
++ buf[2] = INST_BYTE2 (inst1);
++ buf[3] = INST_BYTE3 (inst1);
++ }
++ else {
++ /* Add an imm instruction. First save the current instruction. */
++ for (i = 0; i < INST_WORD_SIZE; i++)
++ buf[i + INST_WORD_SIZE + 4] = buf[i];
++
++ opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ if (opcode1 == NULL || opcode2 ==NULL)
++ {
++ as_bad (_("unknown opcode \"%s\""), "imml");
++ return;
++ }
++ inst1 = opcode2->bit_sequence;
++ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
++ inst1 |= ((val & 0x000000FFFFFF0000L) >> 40) & IMML_MASK;
++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
++ fixP->fx_r_type = BFD_RELOC_64;
++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
++ fixP->fx_r_type = BFD_RELOC_64_PCREL;
++ inst2 = opcode1->bit_sequence;
++ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
++ inst1 |= ((val & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
+ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
+- fixP->fx_r_type = BFD_RELOC_64;
++ fixP->fx_r_type = BFD_RELOC_64;
+ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
+- fixP->fx_r_type = BFD_RELOC_64_PCREL;
++ fixP->fx_r_type = BFD_RELOC_64_PCREL;
++ buf[0] = INST_BYTE0 (inst1);
++ buf[1] = INST_BYTE1 (inst1);
++ buf[2] = INST_BYTE2 (inst1);
++ buf[3] = INST_BYTE3 (inst1);
++ buf[4] = INST_BYTE0 (inst2);
++ buf[5] = INST_BYTE1 (inst2);
++ buf[6] = INST_BYTE2 (inst2);
++ buf[7] = INST_BYTE3 (inst2);
++ }
+ }
+ else
+ {
++ /* Add an imm instruction. First save the current instruction. */
++ for (i = 0; i < INST_WORD_SIZE; i++)
++ buf[i + INST_WORD_SIZE] = buf[i];
+ /* Generate the imm instruction. */
+ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
+ if (opcode1 == NULL)
+@@ -2774,12 +2955,11 @@ md_apply_fix (fixS * fixP,
+ inst1 = opcode1->bit_sequence;
+ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
+ inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK;
+- }
+ buf[0] = INST_BYTE0 (inst1);
+ buf[1] = INST_BYTE1 (inst1);
+ buf[2] = INST_BYTE2 (inst1);
+ buf[3] = INST_BYTE3 (inst1);
+-
++ }
+ /* Add the value only if the symbol is defined. */
+ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
+ {
+@@ -2811,21 +2991,41 @@ md_apply_fix (fixS * fixP,
+ /* Add an imm instruction. First save the current instruction. */
+ for (i = 0; i < INST_WORD_SIZE; i++)
+ buf[i + INST_WORD_SIZE] = buf[i];
+- if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC)
+- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC) {
++ if (((long long)val) > (long long)-549755813888 && ((long long)val) < (long long)549755813887)
++ {
++ for (i = 0; i < INST_WORD_SIZE; i++)
++ buf[i + INST_WORD_SIZE] = buf[i];
++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ }
++ else {
++ for (i = 0; i < INST_WORD_SIZE; i++)
++ buf[i + INST_WORD_SIZE + 4] = buf[i];
++ opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ inst2 = opcode2->bit_sequence;
++
++ /* We can fixup call to a defined non-global address
++ * within the same section only. */
++ buf[4] = INST_BYTE0 (inst2);
++ buf[5] = INST_BYTE1 (inst2);
++ buf[6] = INST_BYTE2 (inst2);
++ buf[7] = INST_BYTE3 (inst2);
++ }
++ }
+ else
+ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
+ if (opcode1 == NULL)
+ {
++ for (i = 0; i < INST_WORD_SIZE; i++)
++ buf[i + INST_WORD_SIZE] = buf[i];
+ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC)
+ as_bad (_("unknown opcode \"%s\""), "imml");
+ else
+ as_bad (_("unknown opcode \"%s\""), "imm");
+ return;
+ }
+-
+ inst1 = opcode1->bit_sequence;
+-
+ /* We can fixup call to a defined non-global address
+ within the same section only. */
+ buf[0] = INST_BYTE0 (inst1);
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 0774f70e08..bd9d91cd57 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -626,8 +626,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM6_WIDTH ((int) 0x00000001)
+ #define MAX_IMM6_WIDTH ((int) 0x00000040)
+
+-#define MIN_IMML ((long long) 0xffffff8000000000L)
+-#define MAX_IMML ((long long) 0x0000007fffffffffL)
++#define MIN_IMML ((long long) -9223372036854775808)
++#define MAX_IMML ((long long) 9223372036854775807)
+
+ #endif /* MICROBLAZE_OPC */
+
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0032-Add-initial-port-of-linux-gdbserver.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0032-Add-initial-port-of-linux-gdbserver.patch
new file mode 100644
index 0000000..7ac89d2
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0032-Add-initial-port-of-linux-gdbserver.patch
@@ -0,0 +1,435 @@
+From c347f9727cc86bb0174dc001446c0670e7306692 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 23 Jan 2017 19:07:44 +0530
+Subject: [PATCH 32/43] Add initial port of linux gdbserver add
+ gdb_proc_service_h to gdbserver microblaze-linux
+
+gdbserver needs to initialise the microblaze registers
+
+other archs use this step to run a *_arch_setup() to carry out all
+architecture specific setup - may need to add in future
+
+ * add linux-ptrace.o to gdbserver configure
+ * Update breakpoint opcode
+ * fix segfault on connecting gdbserver
+ * add microblaze_linux_memory_remove_breakpoint
+ * add set_solib_svr4_fetch_link_map_offsets
+ * add set_gdbarch_fetch_tls_load_module_address
+ * Force reading of r0 as 0, prevent stores
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+---
+ gdb/configure.host | 3 +
+ gdb/gdbserver/linux-microblaze-low.c | 189 +++++++++++++++++++++++++++
+ gdb/microblaze-linux-tdep.c | 29 +++-
+ gdb/microblaze-tdep.c | 35 ++++-
+ gdb/microblaze-tdep.h | 4 +-
+ gdb/regformats/reg-microblaze.dat | 41 ++++++
+ 6 files changed, 298 insertions(+), 3 deletions(-)
+ create mode 100644 gdb/gdbserver/linux-microblaze-low.c
+ create mode 100644 gdb/regformats/reg-microblaze.dat
+
+diff --git a/gdb/configure.host b/gdb/configure.host
+index c87f997abc..de8d6b00f3 100644
+--- a/gdb/configure.host
++++ b/gdb/configure.host
+@@ -65,6 +65,7 @@ hppa*) gdb_host_cpu=pa ;;
+ i[34567]86*) gdb_host_cpu=i386 ;;
+ m68*) gdb_host_cpu=m68k ;;
+ mips*) gdb_host_cpu=mips ;;
++microblaze*) gdb_host_cpu=microblaze ;;
+ powerpc* | rs6000) gdb_host_cpu=powerpc ;;
+ sparcv9 | sparc64) gdb_host_cpu=sparc ;;
+ s390*) gdb_host_cpu=s390 ;;
+@@ -133,6 +134,8 @@ mips*-*-netbsd* | mips*-*-knetbsd*-gnu)
+ mips*-*-freebsd*) gdb_host=fbsd ;;
+ mips64*-*-openbsd*) gdb_host=obsd64 ;;
+
++microblaze*-*linux*) gdb_host=linux ;;
++
+ powerpc-*-aix* | rs6000-*-* | powerpc64-*-aix*)
+ gdb_host=aix ;;
+ powerpc*-*-freebsd*) gdb_host=fbsd ;;
+diff --git a/gdb/gdbserver/linux-microblaze-low.c b/gdb/gdbserver/linux-microblaze-low.c
+new file mode 100644
+index 0000000000..cba5d6fc58
+--- /dev/null
++++ b/gdb/gdbserver/linux-microblaze-low.c
+@@ -0,0 +1,189 @@
++/* GNU/Linux/Microblaze specific low level interface, for the remote server for
++ GDB.
++ Copyright (C) 1995-2013 Free Software Foundation, Inc.
++
++ This file is part of GDB.
++
++ This program is free software; you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 3 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program. If not, see <http://www.gnu.org/licenses/>. */
++
++#include "server.h"
++#include "linux-low.h"
++
++#include <asm/ptrace.h>
++#include <sys/procfs.h>
++#include <sys/ptrace.h>
++
++#include "gdb_proc_service.h"
++
++static int microblaze_regmap[] =
++ {PT_GPR(0), PT_GPR(1), PT_GPR(2), PT_GPR(3),
++ PT_GPR(4), PT_GPR(5), PT_GPR(6), PT_GPR(7),
++ PT_GPR(8), PT_GPR(9), PT_GPR(10), PT_GPR(11),
++ PT_GPR(12), PT_GPR(13), PT_GPR(14), PT_GPR(15),
++ PT_GPR(16), PT_GPR(17), PT_GPR(18), PT_GPR(19),
++ PT_GPR(20), PT_GPR(21), PT_GPR(22), PT_GPR(23),
++ PT_GPR(24), PT_GPR(25), PT_GPR(26), PT_GPR(27),
++ PT_GPR(28), PT_GPR(29), PT_GPR(30), PT_GPR(31),
++ PT_PC, PT_MSR, PT_EAR, PT_ESR,
++ PT_FSR
++ };
++
++#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0])
++
++/* Defined in auto-generated file microblaze-linux.c. */
++void init_registers_microblaze (void);
++
++static int
++microblaze_cannot_store_register (int regno)
++{
++ if (microblaze_regmap[regno] == -1 || regno == 0)
++ return 1;
++
++ return 0;
++}
++
++static int
++microblaze_cannot_fetch_register (int regno)
++{
++ return 0;
++}
++
++static CORE_ADDR
++microblaze_get_pc (struct regcache *regcache)
++{
++ unsigned long pc;
++
++ collect_register_by_name (regcache, "pc", &pc);
++ return (CORE_ADDR) pc;
++}
++
++static void
++microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc)
++{
++ unsigned long newpc = pc;
++
++ supply_register_by_name (regcache, "pc", &newpc);
++}
++
++/* dbtrap insn */
++/* brki r16, 0x18; */
++static const unsigned long microblaze_breakpoint = 0xba0c0018;
++#define microblaze_breakpoint_len 4
++
++static int
++microblaze_breakpoint_at (CORE_ADDR where)
++{
++ unsigned long insn;
++
++ (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
++ if (insn == microblaze_breakpoint)
++ return 1;
++ /* If necessary, recognize more trap instructions here. GDB only uses the
++ one. */
++ return 0;
++}
++
++static CORE_ADDR
++microblaze_reinsert_addr (struct regcache *regcache)
++{
++ unsigned long pc;
++ collect_register_by_name (regcache, "r15", &pc);
++ return pc;
++}
++
++#ifdef HAVE_PTRACE_GETREGS
++
++static void
++microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
++{
++ int size = register_size (regno);
++
++ memset (buf, 0, sizeof (long));
++
++ if (size < sizeof (long))
++ collect_register (regcache, regno, buf + sizeof (long) - size);
++ else
++ collect_register (regcache, regno, buf);
++}
++
++static void
++microblaze_supply_ptrace_register (struct regcache *regcache,
++ int regno, const char *buf)
++{
++ int size = register_size (regno);
++
++ if (regno == 0) {
++ unsigned long regbuf_0 = 0;
++ /* clobbering r0 so that it is always 0 as enforced by hardware */
++ supply_register (regcache, regno, (const char*)®buf_0);
++ } else {
++ if (size < sizeof (long))
++ supply_register (regcache, regno, buf + sizeof (long) - size);
++ else
++ supply_register (regcache, regno, buf);
++ }
++}
++
++/* Provide only a fill function for the general register set. ps_lgetregs
++ will use this for NPTL support. */
++
++static void microblaze_fill_gregset (struct regcache *regcache, void *buf)
++{
++ int i;
++
++ for (i = 0; i < 32; i++)
++ microblaze_collect_ptrace_register (regcache, i, (char *) buf + microblaze_regmap[i]);
++}
++
++static void
++microblaze_store_gregset (struct regcache *regcache, const void *buf)
++{
++ int i;
++
++ for (i = 0; i < 32; i++)
++ supply_register (regcache, i, (char *) buf + microblaze_regmap[i]);
++}
++
++#endif /* HAVE_PTRACE_GETREGS */
++
++struct regset_info target_regsets[] = {
++#ifdef HAVE_PTRACE_GETREGS
++ { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset },
++ { 0, 0, 0, -1, -1, NULL, NULL },
++#endif /* HAVE_PTRACE_GETREGS */
++ { 0, 0, 0, -1, -1, NULL, NULL }
++};
++
++struct linux_target_ops the_low_target = {
++ init_registers_microblaze,
++ microblaze_num_regs,
++ microblaze_regmap,
++ NULL,
++ microblaze_cannot_fetch_register,
++ microblaze_cannot_store_register,
++ NULL, /* fetch_register */
++ microblaze_get_pc,
++ microblaze_set_pc,
++ (const unsigned char *) µblaze_breakpoint,
++ microblaze_breakpoint_len,
++ microblaze_reinsert_addr,
++ 0,
++ microblaze_breakpoint_at,
++ NULL,
++ NULL,
++ NULL,
++ NULL,
++ microblaze_collect_ptrace_register,
++ microblaze_supply_ptrace_register,
++};
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index 4e5f60cd4e..7ab650a1cc 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -37,6 +37,22 @@
+ #include "tramp-frame.h"
+ #include "linux-tdep.h"
+
++static int microblaze_debug_flag = 0;
++
++static void
++microblaze_debug (const char *fmt, ...)
++{
++ if (microblaze_debug_flag)
++ {
++ va_list args;
++
++ va_start (args, fmt);
++ printf_unfiltered ("MICROBLAZE LINUX: ");
++ vprintf_unfiltered (fmt, args);
++ va_end (args);
++ }
++}
++
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ struct bp_target_info *bp_tgt)
+@@ -46,18 +62,25 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ int val;
+ int bplen;
+ gdb_byte old_contents[BREAKPOINT_MAX];
++ struct cleanup *cleanup;
+
+ /* Determine appropriate breakpoint contents and size for this address. */
+ bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
+
++ /* Make sure we see the memory breakpoints. */
++ cleanup = make_show_memory_breakpoints_cleanup (1);
+ val = target_read_memory (addr, old_contents, bplen);
+
+ /* If our breakpoint is no longer at the address, this means that the
+ program modified the code on us, so it is wrong to put back the
+ old value. */
+ if (val == 0 && memcmp (bp, old_contents, bplen) == 0)
+- val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++ {
++ val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++ microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr);
++ }
+
++ do_cleanups (cleanup);
+ return val;
+ }
+
+@@ -129,6 +152,10 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+ /* Trampolines. */
+ tramp_frame_prepend_unwinder (gdbarch,
+ µblaze_linux_sighandler_tramp_frame);
++
++ /* Enable TLS support. */
++ set_gdbarch_fetch_tls_load_module_address (gdbarch,
++ svr4_fetch_objfile_link_map);
+ }
+
+ void
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 1248acbdc9..730a2b281f 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -137,7 +137,38 @@ microblaze_fetch_instruction (CORE_ADDR pc)
+ constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT;
+
+ typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint;
+-
++static int
++microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
++ struct bp_target_info *bp_tgt)
++{
++ CORE_ADDR addr = bp_tgt->placed_address;
++ const unsigned char *bp;
++ int val;
++ int bplen;
++ gdb_byte old_contents[BREAKPOINT_MAX];
++ struct cleanup *cleanup;
++
++ /* Determine appropriate breakpoint contents and size for this address. */
++ bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
++ if (bp == NULL)
++ error (_("Software breakpoints not implemented for this target."));
++
++ /* Make sure we see the memory breakpoints. */
++ cleanup = make_show_memory_breakpoints_cleanup (1);
++ val = target_read_memory (addr, old_contents, bplen);
++
++ /* If our breakpoint is no longer at the address, this means that the
++ program modified the code on us, so it is wrong to put back the
++ old value. */
++ if (val == 0 && memcmp (bp, old_contents, bplen) == 0)
++ {
++ val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++ microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr);
++ }
++
++ do_cleanups (cleanup);
++ return val;
++}
+
+ /* Allocate and initialize a frame cache. */
+
+@@ -731,6 +762,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ microblaze_breakpoint::kind_from_pc);
+ set_gdbarch_sw_breakpoint_from_kind (gdbarch,
+ microblaze_breakpoint::bp_from_kind);
++ set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
+
+ set_gdbarch_frame_args_skip (gdbarch, 8);
+
+@@ -770,4 +802,5 @@ When non-zero, microblaze specific debugging is enabled."),
+ NULL,
+ &setdebuglist, &showdebuglist);
+
++
+ }
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index a0048148e4..63aab84ef6 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -117,6 +117,8 @@ struct microblaze_frame_cache
+
+ /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used.
+ Only used for native debugging. */
+-#define MICROBLAZE_BREAKPOINT {0xb9, 0xcc, 0x00, 0x60}
++#define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18}
++#define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba}
++
+
+ #endif /* microblaze-tdep.h */
+diff --git a/gdb/regformats/reg-microblaze.dat b/gdb/regformats/reg-microblaze.dat
+new file mode 100644
+index 0000000000..bd8a438442
+--- /dev/null
++++ b/gdb/regformats/reg-microblaze.dat
+@@ -0,0 +1,41 @@
++name:microblaze
++expedite:r1,pc
++32:r0
++32:r1
++32:r2
++32:r3
++32:r4
++32:r5
++32:r6
++32:r7
++32:r8
++32:r9
++32:r10
++32:r11
++32:r12
++32:r13
++32:r14
++32:r15
++32:r16
++32:r17
++32:r18
++32:r19
++32:r20
++32:r21
++32:r22
++32:r23
++32:r24
++32:r25
++32:r26
++32:r27
++32:r28
++32:r29
++32:r30
++32:r31
++32:pc
++32:msr
++32:ear
++32:esr
++32:fsr
++32:slr
++32:shr
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0033-Initial-port-of-core-reading-support.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0033-Initial-port-of-core-reading-support.patch
new file mode 100644
index 0000000..e6bbf2b
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0033-Initial-port-of-core-reading-support.patch
@@ -0,0 +1,388 @@
+From 0fd864ff792d7bcbbcbed5ee0ae9f429f1fd2353 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 24 Jan 2017 14:55:56 +0530
+Subject: [PATCH 33/43] Initial port of core reading support Added support for
+ reading notes in linux core dumps Support for reading of PRSTATUS and PSINFO
+ information for rebuilding ".reg" sections of core dumps at run time.
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+---
+ bfd/elf32-microblaze.c | 84 ++++++++++++++++++++++++++++++++++
+ gdb/configure.tgt | 2 +-
+ gdb/microblaze-linux-tdep.c | 57 +++++++++++++++++++++++
+ gdb/microblaze-tdep.c | 90 +++++++++++++++++++++++++++++++++++++
+ gdb/microblaze-tdep.h | 27 +++++++++++
+ 5 files changed, 259 insertions(+), 1 deletion(-)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index 6a795c5069..c280431df6 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -767,6 +767,87 @@ microblaze_elf_is_local_label_name (bfd *abfd, const char *name)
+ return _bfd_elf_is_local_label_name (abfd, name);
+ }
+
++/* Support for core dump NOTE sections. */
++static bfd_boolean
++microblaze_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
++{
++ int offset;
++ unsigned int size;
++
++ switch (note->descsz)
++ {
++ default:
++ return FALSE;
++
++ case 228: /* Linux/MicroBlaze */
++ /* pr_cursig */
++ elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
++
++ /* pr_pid */
++ elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24);
++
++ /* pr_reg */
++ offset = 72;
++ size = 50 * 4;
++
++ break;
++ }
++
++ /* Make a ".reg/999" section. */
++ return _bfd_elfcore_make_pseudosection (abfd, ".reg",
++ size, note->descpos + offset);
++}
++
++static bfd_boolean
++microblaze_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
++{
++ switch (note->descsz)
++ {
++ default:
++ return FALSE;
++
++ case 128: /* Linux/MicroBlaze elf_prpsinfo */
++ elf_tdata (abfd)->core->program
++ = _bfd_elfcore_strndup (abfd, note->descdata + 32, 16);
++ elf_tdata (abfd)->core->command
++ = _bfd_elfcore_strndup (abfd, note->descdata + 48, 80);
++ }
++
++ /* Note that for some reason, a spurious space is tacked
++ onto the end of the args in some (at least one anyway)
++ implementations, so strip it off if it exists. */
++
++ {
++ char *command = elf_tdata (abfd)->core->command;
++ int n = strlen (command);
++
++ if (0 < n && command[n - 1] == ' ')
++ command[n - 1] = '\0';
++ }
++
++ return TRUE;
++}
++
++/* The microblaze linker (like many others) needs to keep track of
++ the number of relocs that it decides to copy as dynamic relocs in
++ check_relocs for each symbol. This is so that it can later discard
++ them if they are found to be unnecessary. We store the information
++ in a field extending the regular ELF linker hash table. */
++
++struct elf32_mb_dyn_relocs
++{
++ struct elf32_mb_dyn_relocs *next;
++
++ /* The input section of the reloc. */
++ asection *sec;
++
++ /* Total number of relocs copied for the input section. */
++ bfd_size_type count;
++
++ /* Number of pc-relative relocs copied for the input section. */
++ bfd_size_type pc_count;
++};
++
+ /* ELF linker hash entry. */
+
+ struct elf32_mb_link_hash_entry
+@@ -3672,4 +3753,7 @@ microblaze_elf_add_symbol_hook (bfd *abfd,
+ #define elf_backend_size_dynamic_sections microblaze_elf_size_dynamic_sections
+ #define elf_backend_add_symbol_hook microblaze_elf_add_symbol_hook
+
++#define elf_backend_grok_prstatus microblaze_elf_grok_prstatus
++#define elf_backend_grok_psinfo microblaze_elf_grok_psinfo
++
+ #include "elf32-target.h"
+diff --git a/gdb/configure.tgt b/gdb/configure.tgt
+index 27f122ad04..622bd486b3 100644
+--- a/gdb/configure.tgt
++++ b/gdb/configure.tgt
+@@ -397,7 +397,7 @@ mep-*-*)
+
+ microblaze*-linux-*|microblaze*-*-linux*)
+ # Target: Xilinx MicroBlaze running Linux
+- gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o \
++ gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o glibc-tdep.o \
+ symfile-mem.o linux-tdep.o"
+ gdb_sim=../sim/microblaze/libsim.a
+ ;;
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index 7ab650a1cc..e2225d778a 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -135,11 +135,54 @@ static struct tramp_frame microblaze_linux_sighandler_tramp_frame =
+ microblaze_linux_sighandler_cache_init
+ };
+
++const struct microblaze_gregset microblaze_linux_core_gregset;
++
++static void
++microblaze_linux_supply_core_gregset (const struct regset *regset,
++ struct regcache *regcache,
++ int regnum, const void *gregs, size_t len)
++{
++ microblaze_supply_gregset (µblaze_linux_core_gregset, regcache,
++ regnum, gregs);
++}
++
++static void
++microblaze_linux_collect_core_gregset (const struct regset *regset,
++ const struct regcache *regcache,
++ int regnum, void *gregs, size_t len)
++{
++ microblaze_collect_gregset (µblaze_linux_core_gregset, regcache,
++ regnum, gregs);
++}
++
++static void
++microblaze_linux_supply_core_fpregset (const struct regset *regset,
++ struct regcache *regcache,
++ int regnum, const void *fpregs, size_t len)
++{
++ /* FIXME. */
++ microblaze_supply_fpregset (regcache, regnum, fpregs);
++}
++
++static void
++microblaze_linux_collect_core_fpregset (const struct regset *regset,
++ const struct regcache *regcache,
++ int regnum, void *fpregs, size_t len)
++{
++ /* FIXME. */
++ microblaze_collect_fpregset (regcache, regnum, fpregs);
++}
+
+ static void
+ microblaze_linux_init_abi (struct gdbarch_info info,
+ struct gdbarch *gdbarch)
+ {
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++
++ tdep->gregset = regset_alloc (gdbarch, microblaze_linux_supply_core_gregset,
++ microblaze_linux_collect_core_gregset);
++ tdep->sizeof_gregset = 200;
++
+ linux_init_abi (info, gdbarch);
+
+ set_gdbarch_memory_remove_breakpoint (gdbarch,
+@@ -153,6 +196,20 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+ tramp_frame_prepend_unwinder (gdbarch,
+ µblaze_linux_sighandler_tramp_frame);
+
++ /* BFD target for core files. */
++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++ else
++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++
++
++ /* Shared library handling. */
++ set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
++ set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
++
++ set_gdbarch_regset_from_core_section (gdbarch,
++ microblaze_regset_from_core_section);
++
+ /* Enable TLS support. */
+ set_gdbarch_fetch_tls_load_module_address (gdbarch,
+ svr4_fetch_objfile_link_map);
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 730a2b281f..49713ea9b1 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -137,6 +137,14 @@ microblaze_fetch_instruction (CORE_ADDR pc)
+ constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT;
+
+ typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint;
++static CORE_ADDR
++microblaze_store_arguments (struct regcache *regcache, int nargs,
++ struct value **args, CORE_ADDR sp,
++ int struct_return, CORE_ADDR struct_addr)
++{
++ error (_("store_arguments not implemented"));
++ return sp;
++}
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ struct bp_target_info *bp_tgt)
+@@ -541,6 +549,12 @@ microblaze_frame_base_address (struct frame_info *next_frame,
+ return cache->base;
+ }
+
++static const struct frame_unwind *
++microblaze_frame_sniffer (struct frame_info *next_frame)
++{
++ return µblaze_frame_unwind;
++}
++
+ static const struct frame_base microblaze_frame_base =
+ {
+ µblaze_frame_unwind,
+@@ -677,6 +691,71 @@ microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
+ tdesc_microblaze_with_stack_protect);
+ }
+
++void
++microblaze_supply_gregset (const struct microblaze_gregset *gregset,
++ struct regcache *regcache,
++ int regnum, const void *gregs)
++{
++ unsigned int *regs = gregs;
++ if (regnum >= 0)
++ regcache_raw_supply (regcache, regnum, regs + regnum);
++
++ if (regnum == -1) {
++ int i;
++
++ for (i = 0; i < 50; i++) {
++ regcache_raw_supply (regcache, i, regs + i);
++ }
++ }
++}
++
++
++void
++microblaze_collect_gregset (const struct microblaze_gregset *gregset,
++ const struct regcache *regcache,
++ int regnum, void *gregs)
++{
++ /* FIXME. */
++}
++
++void
++microblaze_supply_fpregset (struct regcache *regcache,
++ int regnum, const void *fpregs)
++{
++ /* FIXME. */
++}
++
++void
++microblaze_collect_fpregset (const struct regcache *regcache,
++ int regnum, void *fpregs)
++{
++ /* FIXME. */
++}
++
++
++/* Return the appropriate register set for the core section identified
++ by SECT_NAME and SECT_SIZE. */
++
++const struct regset *
++microblaze_regset_from_core_section (struct gdbarch *gdbarch,
++ const char *sect_name, size_t sect_size)
++{
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++
++ microblaze_debug ("microblaze_regset_from_core_section, sect_name = %s\n", sect_name);
++
++ if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset)
++ return tdep->gregset;
++
++ if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset)
++ return tdep->fpregset;
++
++ microblaze_debug ("microblaze_regset_from_core_section returning null :-( \n");
++ return NULL;
++}
++
++
++
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ {
+@@ -733,6 +812,10 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ tdep = XCNEW (struct gdbarch_tdep);
+ gdbarch = gdbarch_alloc (&info, tdep);
+
++ tdep->gregset = NULL;
++ tdep->sizeof_gregset = 0;
++ tdep->fpregset = NULL;
++ tdep->sizeof_fpregset = 0;
+ set_gdbarch_long_double_bit (gdbarch, 128);
+
+ set_gdbarch_num_regs (gdbarch, MICROBLAZE_NUM_REGS);
+@@ -781,6 +864,13 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
+ if (tdesc_data != NULL)
+ tdesc_use_registers (gdbarch, tdesc, tdesc_data);
++ //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer);
++
++ /* If we have register sets, enable the generic core file support. */
++ if (tdep->gregset) {
++ set_gdbarch_regset_from_core_section (gdbarch,
++ microblaze_regset_from_core_section);
++ }
+
+ return gdbarch;
+ }
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index 63aab84ef6..02650f61d9 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -22,8 +22,22 @@
+
+
+ /* Microblaze architecture-specific information. */
++struct microblaze_gregset
++{
++ unsigned int gregs[32];
++ unsigned int fpregs[32];
++ unsigned int pregs[16];
++};
++
+ struct gdbarch_tdep
+ {
++ int dummy; // declare something.
++
++ /* Register sets. */
++ struct regset *gregset;
++ size_t sizeof_gregset;
++ struct regset *fpregset;
++ size_t sizeof_fpregset;
+ };
+
+ /* Register numbers. */
+@@ -120,5 +134,18 @@ struct microblaze_frame_cache
+ #define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18}
+ #define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba}
+
++extern void microblaze_supply_gregset (const struct microblaze_gregset *gregset,
++ struct regcache *regcache,
++ int regnum, const void *gregs);
++extern void microblaze_collect_gregset (const struct microblaze_gregset *gregset,
++ const struct regcache *regcache,
++ int regnum, void *gregs);
++extern void microblaze_supply_fpregset (struct regcache *regcache,
++ int regnum, const void *fpregs);
++extern void microblaze_collect_fpregset (const struct regcache *regcache,
++ int regnum, void *fpregs);
++
++extern const struct regset * microblaze_regset_from_core_section (struct gdbarch *gdbarch,
++ const char *sect_name, size_t sect_size);
+
+ #endif /* microblaze-tdep.h */
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0034-Fix-debug-message-when-register-is-unavailable.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0034-Fix-debug-message-when-register-is-unavailable.patch
new file mode 100644
index 0000000..df5b3db
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0034-Fix-debug-message-when-register-is-unavailable.patch
@@ -0,0 +1,40 @@
+From e44a27432ce56bb48eb9785ffaae14bc3a12bd27 Mon Sep 17 00:00:00 2001
+From: Nathan Rossi <nathan.rossi@petalogix.com>
+Date: Tue, 8 May 2012 18:11:17 +1000
+Subject: [PATCH 34/43] Fix debug message when register is unavailable
+
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+---
+ gdb/frame.c | 13 ++++++++++---
+ 1 file changed, 10 insertions(+), 3 deletions(-)
+
+diff --git a/gdb/frame.c b/gdb/frame.c
+index d8b5f819f1..49706dc97c 100644
+--- a/gdb/frame.c
++++ b/gdb/frame.c
+@@ -1227,12 +1227,19 @@ frame_unwind_register_value (frame_info *next_frame, int regnum)
+ else
+ {
+ int i;
+- const gdb_byte *buf = value_contents (value);
++ const gdb_byte *buf = NULL;
++ if (value_entirely_available(value)) {
++ buf = value_contents (value);
++ }
+
+ fprintf_unfiltered (gdb_stdlog, " bytes=");
+ fprintf_unfiltered (gdb_stdlog, "[");
+- for (i = 0; i < register_size (gdbarch, regnum); i++)
+- fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]);
++ if (buf != NULL) {
++ for (i = 0; i < register_size (gdbarch, regnum); i++)
++ fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]);
++ } else {
++ fprintf_unfiltered (gdb_stdlog, "unavailable");
++ }
+ fprintf_unfiltered (gdb_stdlog, "]");
+ }
+ }
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0035-revert-master-rebase-changes-to-gdbserver.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0035-revert-master-rebase-changes-to-gdbserver.patch
new file mode 100644
index 0000000..ddb53a0
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0035-revert-master-rebase-changes-to-gdbserver.patch
@@ -0,0 +1,31 @@
+From 1c5dbbd272854e6e7912e2602bdfd78b64399319 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Mon, 22 Jul 2013 11:16:05 +1000
+Subject: [PATCH 35/43] revert master-rebase changes to gdbserver
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gdb/gdbserver/configure.srv | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
+index d19d22b3a3..7a0be5b072 100644
+--- a/gdb/gdbserver/configure.srv
++++ b/gdb/gdbserver/configure.srv
+@@ -210,6 +210,13 @@ case "${target}" in
+ srv_linux_usrregs=yes
+ srv_linux_thread_db=yes
+ ;;
++ microblaze*-*-linux*) srv_regobj=microblaze-linux.o
++ srv_tgtobj="linux-low.o linux-osdata.o linux-microblaze-low.o "
++ srv_tgtobj="${srv_tgtobj} linux-procfs.o linux-ptrace.o"
++ srv_linux_regsets=yes
++ srv_linux_usrregs=yes
++ srv_linux_thread_db=yes
++ ;;
+ powerpc*-*-linux*) srv_regobj="powerpc-32l.o"
+ srv_regobj="${srv_regobj} powerpc-altivec32l.o"
+ srv_regobj="${srv_regobj} powerpc-cell32l.o"
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0036-revert-master-rebase-changes-to-gdbserver-previous-c.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0036-revert-master-rebase-changes-to-gdbserver-previous-c.patch
new file mode 100644
index 0000000..f2e5e95
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0036-revert-master-rebase-changes-to-gdbserver-previous-c.patch
@@ -0,0 +1,33 @@
+From bd55e11af18006afb87a8b0fbd93bb0920354e0e Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 30 Apr 2018 17:09:55 +0530
+Subject: [PATCH 36/43] revert master-rebase changes to gdbserver , previous
+ commit typo's
+
+---
+ gdb/gdbserver/Makefile.in | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/gdb/gdbserver/Makefile.in b/gdb/gdbserver/Makefile.in
+index 4ae13692a2..45d95e6cab 100644
+--- a/gdb/gdbserver/Makefile.in
++++ b/gdb/gdbserver/Makefile.in
+@@ -169,6 +169,7 @@ SFILES = \
+ $(srcdir)/linux-low.c \
+ $(srcdir)/linux-m32r-low.c \
+ $(srcdir)/linux-m68k-low.c \
++ $(srcdir)/linux-microblaze-low.c \
+ $(srcdir)/linux-mips-low.c \
+ $(srcdir)/linux-nios2-low.c \
+ $(srcdir)/linux-ppc-low.c \
+@@ -226,6 +227,7 @@ SFILES = \
+ $(srcdir)/nat/linux-osdata.c \
+ $(srcdir)/nat/linux-personality.c \
+ $(srcdir)/nat/mips-linux-watch.c \
++ $(srcdir)/nat/microblaze-linux.c \
+ $(srcdir)/nat/ppc-linux.c \
+ $(srcdir)/nat/fork-inferior.c \
+ $(srcdir)/target/waitstatus.c
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch
new file mode 100644
index 0000000..e2b601b
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch
@@ -0,0 +1,32 @@
+From 988a9a41ac91ce3293af8708c1c88c51c48a2a72 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Mon, 16 Dec 2013 16:37:32 +1000
+Subject: [PATCH 37/43] microblaze: Add build_gdbserver=yes to top level
+ configure.tgt
+
+For Microblaze linux toolchains, set the build_gdbserver=yes
+to allow driving gdbserver configuration from the upper level
+
+This patch has been absorbed into the original patch to add
+linux gdbserver support for Microblaze.
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gdb/configure.tgt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/gdb/configure.tgt b/gdb/configure.tgt
+index 622bd486b3..989523735b 100644
+--- a/gdb/configure.tgt
++++ b/gdb/configure.tgt
+@@ -405,6 +405,7 @@ microblaze*-*-*)
+ # Target: Xilinx MicroBlaze running standalone
+ gdb_target_obs="microblaze-tdep.o"
+ gdb_sim=../sim/microblaze/libsim.a
++ build_gdbserver=yes
+ ;;
+
+ mips*-*-linux*)
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0038-Initial-support-for-native-gdb.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0038-Initial-support-for-native-gdb.patch
new file mode 100644
index 0000000..1a50f0a
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0038-Initial-support-for-native-gdb.patch
@@ -0,0 +1,511 @@
+From aa9cb6db79c663dc944cb67928d16e63f2a69f74 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@petalogix.com>
+Date: Fri, 20 Jul 2012 15:18:35 +1000
+Subject: [PATCH 38/43] Initial support for native gdb
+
+microblaze: Follow PPC method of getting setting registers
+using PTRACE PEEK/POKE
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+
+Conflicts:
+ gdb/Makefile.in
+---
+ gdb/Makefile.in | 4 +-
+ gdb/config/microblaze/linux.mh | 9 +
+ gdb/microblaze-linux-nat.c | 431 +++++++++++++++++++++++++++++++++
+ 3 files changed, 443 insertions(+), 1 deletion(-)
+ create mode 100644 gdb/config/microblaze/linux.mh
+ create mode 100644 gdb/microblaze-linux-nat.c
+
+diff --git a/gdb/Makefile.in b/gdb/Makefile.in
+index 215ef7933c..8c9a3c07c0 100644
+--- a/gdb/Makefile.in
++++ b/gdb/Makefile.in
+@@ -1316,6 +1316,7 @@ HFILES_NO_SRCDIR = \
+ memory-map.h \
+ memrange.h \
+ microblaze-tdep.h \
++ microblaze-linux-tdep.h \
+ mips-linux-tdep.h \
+ mips-nbsd-tdep.h \
+ mips-tdep.h \
+@@ -1349,6 +1350,7 @@ HFILES_NO_SRCDIR = \
+ prologue-value.h \
+ psympriv.h \
+ psymtab.h \
++ ia64-hpux-tdep.h \
+ ravenscar-thread.h \
+ record.h \
+ record-full.h \
+@@ -2263,6 +2265,7 @@ ALLDEPFILES = \
+ m68k-tdep.c \
+ microblaze-linux-tdep.c \
+ microblaze-tdep.c \
++ microblaze-linux-nat.c \
+ mingw-hdep.c \
+ mips-fbsd-nat.c \
+ mips-fbsd-tdep.c \
+@@ -2365,7 +2368,6 @@ ALLDEPFILES = \
+ xtensa-linux-tdep.c \
+ xtensa-tdep.c \
+ xtensa-xtregs.c \
+- common/mingw-strerror.c \
+ common/posix-strerror.c
+
+ # Some files need explicit build rules (due to -Werror problems) or due
+diff --git a/gdb/config/microblaze/linux.mh b/gdb/config/microblaze/linux.mh
+new file mode 100644
+index 0000000000..a4eaf540e1
+--- /dev/null
++++ b/gdb/config/microblaze/linux.mh
+@@ -0,0 +1,9 @@
++# Host: Microblaze, running Linux
++
++NAT_FILE= config/nm-linux.h
++NATDEPFILES= inf-ptrace.o fork-child.o \
++ microblaze-linux-nat.o proc-service.o linux-thread-db.o \
++ linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o
++NAT_CDEPS = $(srcdir)/proc-service.list
++
++LOADLIBES = -ldl $(RDYNAMIC)
+diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c
+new file mode 100644
+index 0000000000..e9b8c9c522
+--- /dev/null
++++ b/gdb/microblaze-linux-nat.c
+@@ -0,0 +1,431 @@
++/* Microblaze GNU/Linux native support.
++
++ Copyright (C) 1988-1989, 1991-1992, 1994, 1996, 2000-2012 Free
++ Software Foundation, Inc.
++
++ This file is part of GDB.
++
++ This program is free software; you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 3 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program. If not, see <http://www.gnu.org/licenses/>. */
++
++#include "defs.h"
++#include "arch-utils.h"
++#include "dis-asm.h"
++#include "frame.h"
++#include "trad-frame.h"
++#include "symtab.h"
++#include "value.h"
++#include "gdbcmd.h"
++#include "breakpoint.h"
++#include "inferior.h"
++#include "regcache.h"
++#include "target.h"
++#include "frame.h"
++#include "frame-base.h"
++#include "frame-unwind.h"
++#include "dwarf2-frame.h"
++#include "osabi.h"
++
++#include "gdb_assert.h"
++#include "gdb_string.h"
++#include "target-descriptions.h"
++#include "opcodes/microblaze-opcm.h"
++#include "opcodes/microblaze-dis.h"
++
++#include "linux-nat.h"
++#include "target-descriptions.h"
++
++#include <sys/user.h>
++#include <sys/utsname.h>
++#include <sys/procfs.h>
++#include <sys/ptrace.h>
++
++/* Prototypes for supply_gregset etc. */
++#include "gregset.h"
++
++#include "microblaze-tdep.h"
++
++#include <elf/common.h>
++#include "auxv.h"
++
++/* Defines ps_err_e, struct ps_prochandle. */
++#include "gdb_proc_service.h"
++
++/* On GNU/Linux, threads are implemented as pseudo-processes, in which
++ case we may be tracing more than one process at a time. In that
++ case, inferior_ptid will contain the main process ID and the
++ individual thread (process) ID. get_thread_id () is used to get
++ the thread id if it's available, and the process id otherwise. */
++
++int
++get_thread_id (ptid_t ptid)
++{
++ int tid = TIDGET (ptid);
++ if (0 == tid)
++ tid = PIDGET (ptid);
++ return tid;
++}
++
++#define GET_THREAD_ID(PTID) get_thread_id (PTID)
++
++/* Non-zero if our kernel may support the PTRACE_GETREGS and
++ PTRACE_SETREGS requests, for reading and writing the
++ general-purpose registers. Zero if we've tried one of
++ them and gotten an error. */
++int have_ptrace_getsetregs = 1;
++
++static int
++microblaze_register_u_addr (struct gdbarch *gdbarch, int regno)
++{
++ int u_addr = -1;
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
++ interface, and not the wordsize of the program's ABI. */
++ int wordsize = sizeof (long);
++
++ /* General purpose registers occupy 1 slot each in the buffer. */
++ if (regno >= MICROBLAZE_R0_REGNUM
++ && regno <= MICROBLAZE_FSR_REGNUM)
++ u_addr = (regno * wordsize);
++
++ return u_addr;
++}
++
++
++static void
++fetch_register (struct regcache *regcache, int tid, int regno)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ /* This isn't really an address. But ptrace thinks of it as one. */
++ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
++ int bytes_transferred;
++ unsigned int offset; /* Offset of registers within the u area. */
++ char buf[MAX_REGISTER_SIZE];
++
++ if (regaddr == -1)
++ {
++ memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */
++ regcache_raw_supply (regcache, regno, buf);
++ return;
++ }
++
++ /* Read the raw register using sizeof(long) sized chunks. On a
++ 32-bit platform, 64-bit floating-point registers will require two
++ transfers. */
++ for (bytes_transferred = 0;
++ bytes_transferred < register_size (gdbarch, regno);
++ bytes_transferred += sizeof (long))
++ {
++ long l;
++
++ errno = 0;
++ l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
++ regaddr += sizeof (long);
++ if (errno != 0)
++ {
++ char message[128];
++ sprintf (message, "reading register %s (#%d)",
++ gdbarch_register_name (gdbarch, regno), regno);
++ perror_with_name (message);
++ }
++ memcpy (&buf[bytes_transferred], &l, sizeof (l));
++ }
++
++ /* Now supply the register. Keep in mind that the regcache's idea
++ of the register's size may not be a multiple of sizeof
++ (long). */
++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
++ {
++ /* Little-endian values are always found at the left end of the
++ bytes transferred. */
++ regcache_raw_supply (regcache, regno, buf);
++ }
++ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++ {
++ /* Big-endian values are found at the right end of the bytes
++ transferred. */
++ size_t padding = (bytes_transferred - register_size (gdbarch, regno));
++ regcache_raw_supply (regcache, regno, buf + padding);
++ }
++ else
++ internal_error (__FILE__, __LINE__,
++ _("fetch_register: unexpected byte order: %d"),
++ gdbarch_byte_order (gdbarch));
++}
++
++/* This function actually issues the request to ptrace, telling
++ it to get all general-purpose registers and put them into the
++ specified regset.
++
++ If the ptrace request does not exist, this function returns 0
++ and properly sets the have_ptrace_* flag. If the request fails,
++ this function calls perror_with_name. Otherwise, if the request
++ succeeds, then the regcache gets filled and 1 is returned. */
++static int
++fetch_all_gp_regs (struct regcache *regcache, int tid)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ gdb_gregset_t gregset;
++
++ if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
++ {
++ if (errno == EIO)
++ {
++ have_ptrace_getsetregs = 0;
++ return 0;
++ }
++ perror_with_name (_("Couldn't get general-purpose registers."));
++ }
++
++ supply_gregset (regcache, (const gdb_gregset_t *) &gregset);
++
++ return 1;
++}
++
++
++/* This is a wrapper for the fetch_all_gp_regs function. It is
++ responsible for verifying if this target has the ptrace request
++ that can be used to fetch all general-purpose registers at one
++ shot. If it doesn't, then we should fetch them using the
++ old-fashioned way, which is to iterate over the registers and
++ request them one by one. */
++static void
++fetch_gp_regs (struct regcache *regcache, int tid)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ int i;
++
++ if (have_ptrace_getsetregs)
++ if (fetch_all_gp_regs (regcache, tid))
++ return;
++
++ /* If we've hit this point, it doesn't really matter which
++ architecture we are using. We just need to read the
++ registers in the "old-fashioned way". */
++ for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)
++ fetch_register (regcache, tid, i);
++}
++
++
++static void
++store_register (const struct regcache *regcache, int tid, int regno)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ /* This isn't really an address. But ptrace thinks of it as one. */
++ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
++ int i;
++ size_t bytes_to_transfer;
++ char buf[MAX_REGISTER_SIZE];
++
++ if (regaddr == -1)
++ return;
++
++ /* First collect the register. Keep in mind that the regcache's
++ idea of the register's size may not be a multiple of sizeof
++ (long). */
++ memset (buf, 0, sizeof buf);
++ bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
++ {
++ /* Little-endian values always sit at the left end of the buffer. */
++ regcache_raw_collect (regcache, regno, buf);
++ }
++ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++ {
++ /* Big-endian values sit at the right end of the buffer. */
++ size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
++ regcache_raw_collect (regcache, regno, buf + padding);
++ }
++
++ for (i = 0; i < bytes_to_transfer; i += sizeof (long))
++ {
++ long l;
++
++ memcpy (&l, &buf[i], sizeof (l));
++ errno = 0;
++ ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l);
++ regaddr += sizeof (long);
++
++ if (errno != 0)
++ {
++ char message[128];
++ sprintf (message, "writing register %s (#%d)",
++ gdbarch_register_name (gdbarch, regno), regno);
++ perror_with_name (message);
++ }
++ }
++}
++
++/* This function actually issues the request to ptrace, telling
++ it to store all general-purpose registers present in the specified
++ regset.
++
++ If the ptrace request does not exist, this function returns 0
++ and properly sets the have_ptrace_* flag. If the request fails,
++ this function calls perror_with_name. Otherwise, if the request
++ succeeds, then the regcache is stored and 1 is returned. */
++static int
++store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ gdb_gregset_t gregset;
++
++ if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
++ {
++ if (errno == EIO)
++ {
++ have_ptrace_getsetregs = 0;
++ return 0;
++ }
++ perror_with_name (_("Couldn't get general-purpose registers."));
++ }
++
++ fill_gregset (regcache, &gregset, regno);
++
++ if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0)
++ {
++ if (errno == EIO)
++ {
++ have_ptrace_getsetregs = 0;
++ return 0;
++ }
++ perror_with_name (_("Couldn't set general-purpose registers."));
++ }
++
++ return 1;
++}
++
++/* This is a wrapper for the store_all_gp_regs function. It is
++ responsible for verifying if this target has the ptrace request
++ that can be used to store all general-purpose registers at one
++ shot. If it doesn't, then we should store them using the
++ old-fashioned way, which is to iterate over the registers and
++ store them one by one. */
++static void
++store_gp_regs (const struct regcache *regcache, int tid, int regno)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ int i;
++
++ if (have_ptrace_getsetregs)
++ if (store_all_gp_regs (regcache, tid, regno))
++ return;
++
++ /* If we hit this point, it doesn't really matter which
++ architecture we are using. We just need to store the
++ registers in the "old-fashioned way". */
++ for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)
++ store_register (regcache, tid, i);
++}
++
++
++/* Fetch registers from the child process. Fetch all registers if
++ regno == -1, otherwise fetch all general registers or all floating
++ point registers depending upon the value of regno. */
++
++static void
++microblaze_linux_fetch_inferior_registers (struct target_ops *ops,
++ struct regcache *regcache, int regno)
++{
++ /* Get the thread id for the ptrace call. */
++ int tid = GET_THREAD_ID (inferior_ptid);
++
++ if (regno == -1)
++ fetch_gp_regs (regcache, tid);
++ else
++ fetch_register (regcache, tid, regno);
++}
++
++/* Store registers back into the inferior. Store all registers if
++ regno == -1, otherwise store all general registers or all floating
++ point registers depending upon the value of regno. */
++
++static void
++microblaze_linux_store_inferior_registers (struct target_ops *ops,
++ struct regcache *regcache, int regno)
++{
++ /* Get the thread id for the ptrace call. */
++ int tid = GET_THREAD_ID (inferior_ptid);
++
++ if (regno >= 0)
++ store_register (regcache, tid, regno);
++ else
++ store_gp_regs (regcache, tid, -1);
++}
++
++/* Wrapper functions for the standard regset handling, used by
++ thread debugging. */
++
++void
++fill_gregset (const struct regcache *regcache,
++ gdb_gregset_t *gregsetp, int regno)
++{
++ microblaze_collect_gregset (NULL, regcache, regno, gregsetp);
++}
++
++void
++supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
++{
++ microblaze_supply_gregset (NULL, regcache, -1, gregsetp);
++}
++
++void
++fill_fpregset (const struct regcache *regcache,
++ gdb_fpregset_t *fpregsetp, int regno)
++{
++ /* FIXME. */
++}
++
++void
++supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
++{
++ /* FIXME. */
++}
++
++static const struct target_desc *
++microblaze_linux_read_description (struct target_ops *ops)
++{
++ CORE_ADDR microblaze_hwcap = 0;
++
++ if (target_auxv_search (ops, AT_HWCAP, µblaze_hwcap) != 1)
++ return NULL;
++
++ return NULL;
++}
++
++
++void _initialize_microblaze_linux_nat (void);
++
++void
++_initialize_microblaze_linux_nat (void)
++{
++ struct target_ops *t;
++
++ /* Fill in the generic GNU/Linux methods. */
++ t = linux_target ();
++
++ /* Add our register access methods. */
++ t->to_fetch_registers = microblaze_linux_fetch_inferior_registers;
++ t->to_store_registers = microblaze_linux_store_inferior_registers;
++
++ t->to_read_description = microblaze_linux_read_description;
++
++ /* Register the target. */
++ linux_nat_add_target (t);
++}
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0039-Fixing-the-issues-related-to-GDB-7.12.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0039-Fixing-the-issues-related-to-GDB-7.12.patch
new file mode 100644
index 0000000..0b1475a
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0039-Fixing-the-issues-related-to-GDB-7.12.patch
@@ -0,0 +1,309 @@
+From 0b5b76d6c9757ebb1c9677772c24272957190345 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Fri, 17 Feb 2017 14:09:40 +0530
+Subject: [PATCH 39/43] Fixing the issues related to GDB-7.12 added all the
+ required function which are new in 7.12 and removed few deprecated functions
+ from 7.6
+
+---
+ gdb/config/microblaze/linux.mh | 4 +-
+ gdb/gdbserver/configure.srv | 3 +-
+ gdb/gdbserver/linux-microblaze-low.c | 97 ++++++++++++++++++++++++----
+ gdb/microblaze-linux-tdep.c | 68 +++++++++++++++++--
+ gdb/microblaze-tdep.h | 1 +
+ 5 files changed, 153 insertions(+), 20 deletions(-)
+
+diff --git a/gdb/config/microblaze/linux.mh b/gdb/config/microblaze/linux.mh
+index a4eaf540e1..74a53b854a 100644
+--- a/gdb/config/microblaze/linux.mh
++++ b/gdb/config/microblaze/linux.mh
+@@ -1,9 +1,11 @@
+ # Host: Microblaze, running Linux
+
++#linux-nat.o linux-waitpid.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o
+ NAT_FILE= config/nm-linux.h
+ NATDEPFILES= inf-ptrace.o fork-child.o \
+ microblaze-linux-nat.o proc-service.o linux-thread-db.o \
+- linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o
++ linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o \
++ linux-waitpid.o linux-personality.o linux-namespaces.o
+ NAT_CDEPS = $(srcdir)/proc-service.list
+
+ LOADLIBES = -ldl $(RDYNAMIC)
+diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
+index 7a0be5b072..c421790bd0 100644
+--- a/gdb/gdbserver/configure.srv
++++ b/gdb/gdbserver/configure.srv
+@@ -211,8 +211,7 @@ case "${target}" in
+ srv_linux_thread_db=yes
+ ;;
+ microblaze*-*-linux*) srv_regobj=microblaze-linux.o
+- srv_tgtobj="linux-low.o linux-osdata.o linux-microblaze-low.o "
+- srv_tgtobj="${srv_tgtobj} linux-procfs.o linux-ptrace.o"
++ srv_tgtobj="$srv_linux_obj linux-microblaze-low.o "
+ srv_linux_regsets=yes
+ srv_linux_usrregs=yes
+ srv_linux_thread_db=yes
+diff --git a/gdb/gdbserver/linux-microblaze-low.c b/gdb/gdbserver/linux-microblaze-low.c
+index cba5d6fc58..a2733f3c21 100644
+--- a/gdb/gdbserver/linux-microblaze-low.c
++++ b/gdb/gdbserver/linux-microblaze-low.c
+@@ -39,10 +39,11 @@ static int microblaze_regmap[] =
+ PT_FSR
+ };
+
+-#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0])
++#define microblaze_num_regs (sizeof (microblaze_regmap) / sizeof (microblaze_regmap[0]))
+
+ /* Defined in auto-generated file microblaze-linux.c. */
+ void init_registers_microblaze (void);
++extern const struct target_desc *tdesc_microblaze;
+
+ static int
+ microblaze_cannot_store_register (int regno)
+@@ -81,6 +82,15 @@ microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc)
+ static const unsigned long microblaze_breakpoint = 0xba0c0018;
+ #define microblaze_breakpoint_len 4
+
++/* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
++
++static const gdb_byte *
++microblaze_sw_breakpoint_from_kind (int kind, int *size)
++{
++ *size = microblaze_breakpoint_len;
++ return (const gdb_byte *) µblaze_breakpoint;
++}
++
+ static int
+ microblaze_breakpoint_at (CORE_ADDR where)
+ {
+@@ -107,7 +117,7 @@ microblaze_reinsert_addr (struct regcache *regcache)
+ static void
+ microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
+ {
+- int size = register_size (regno);
++ int size = register_size (regcache->tdesc, regno);
+
+ memset (buf, 0, sizeof (long));
+
+@@ -121,7 +131,7 @@ static void
+ microblaze_supply_ptrace_register (struct regcache *regcache,
+ int regno, const char *buf)
+ {
+- int size = register_size (regno);
++ int size = register_size (regcache->tdesc, regno);
+
+ if (regno == 0) {
+ unsigned long regbuf_0 = 0;
+@@ -157,33 +167,94 @@ microblaze_store_gregset (struct regcache *regcache, const void *buf)
+
+ #endif /* HAVE_PTRACE_GETREGS */
+
+-struct regset_info target_regsets[] = {
++static struct regset_info microblaze_regsets[] = {
+ #ifdef HAVE_PTRACE_GETREGS
+ { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset },
+- { 0, 0, 0, -1, -1, NULL, NULL },
++ { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL },
+ #endif /* HAVE_PTRACE_GETREGS */
+- { 0, 0, 0, -1, -1, NULL, NULL }
++ { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL },
++ NULL_REGSET
+ };
+
++static struct usrregs_info microblaze_usrregs_info =
++ {
++ microblaze_num_regs,
++ microblaze_regmap,
++ };
++
++static struct regsets_info microblaze_regsets_info =
++ {
++ microblaze_regsets, /* regsets */
++ 0, /* num_regsets */
++ NULL, /* disabled_regsets */
++ };
++
++static struct regs_info regs_info =
++ {
++ NULL, /* regset_bitmap */
++ µblaze_usrregs_info,
++ µblaze_regsets_info
++ };
++
++static const struct regs_info *
++microblaze_regs_info (void)
++{
++ return ®s_info;
++}
++
++/* Support for hardware single step. */
++
++static int
++microblaze_supports_hardware_single_step (void)
++{
++ return 1;
++}
++
++
++static void
++microblaze_arch_setup (void)
++{
++ current_process ()->tdesc = tdesc_microblaze;
++}
++
+ struct linux_target_ops the_low_target = {
+- init_registers_microblaze,
+- microblaze_num_regs,
+- microblaze_regmap,
+- NULL,
++ microblaze_arch_setup,
++ microblaze_regs_info,
+ microblaze_cannot_fetch_register,
+ microblaze_cannot_store_register,
+ NULL, /* fetch_register */
+ microblaze_get_pc,
+ microblaze_set_pc,
+- (const unsigned char *) µblaze_breakpoint,
+- microblaze_breakpoint_len,
+- microblaze_reinsert_addr,
++ NULL,
++ microblaze_sw_breakpoint_from_kind,
++ NULL,
+ 0,
+ microblaze_breakpoint_at,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
++ NULL,
+ microblaze_collect_ptrace_register,
+ microblaze_supply_ptrace_register,
++ NULL, /* siginfo_fixup */
++ NULL, /* new_process */
++ NULL, /* new_thread */
++ NULL, /* new_fork */
++ NULL, /* prepare_to_resume */
++ NULL, /* process_qsupported */
++ NULL, /* supports_tracepoints */
++ NULL, /* get_thread_area */
++ NULL, /* install_fast_tracepoint_jump_pad */
++ NULL, /* emit_ops */
++ NULL, /* get_min_fast_tracepoint_insn_len */
++ NULL, /* supports_range_stepping */
++ NULL, /* breakpoint_kind_from_current_state */
++ microblaze_supports_hardware_single_step,
+ };
++
++void
++initialize_low_arch (void)
++{
++ init_registers_microblaze ();
++}
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index e2225d778a..011e513941 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -29,13 +29,76 @@
+ #include "regcache.h"
+ #include "value.h"
+ #include "osabi.h"
+-#include "regset.h"
+ #include "solib-svr4.h"
+ #include "microblaze-tdep.h"
+ #include "trad-frame.h"
+ #include "frame-unwind.h"
+ #include "tramp-frame.h"
+ #include "linux-tdep.h"
++#include "glibc-tdep.h"
++
++#include "gdb_assert.h"
++
++#ifndef REGSET_H
++#define REGSET_H 1
++
++struct gdbarch;
++struct regcache;
++
++/* Data structure for the supported register notes in a core file. */
++struct core_regset_section
++{
++ const char *sect_name;
++ int size;
++ const char *human_name;
++};
++
++/* Data structure describing a register set. */
++
++typedef void (supply_regset_ftype) (const struct regset *, struct regcache *,
++ int, const void *, size_t);
++typedef void (collect_regset_ftype) (const struct regset *,
++ const struct regcache *,
++ int, void *, size_t);
++
++struct regset
++{
++ /* Data pointer for private use by the methods below, presumably
++ providing some sort of description of the register set. */
++ const void *descr;
++
++ /* Function supplying values in a register set to a register cache. */
++ supply_regset_ftype *supply_regset;
++
++ /* Function collecting values in a register set from a register cache. */
++ collect_regset_ftype *collect_regset;
++
++ /* Architecture associated with the register set. */
++ struct gdbarch *arch;
++};
++
++#endif
++
++/* Allocate a fresh 'struct regset' whose supply_regset function is
++ SUPPLY_REGSET, and whose collect_regset function is COLLECT_REGSET.
++ If the regset has no collect_regset function, pass NULL for
++ COLLECT_REGSET.
++
++ The object returned is allocated on ARCH's obstack. */
++
++struct regset *
++regset_alloc (struct gdbarch *arch,
++ supply_regset_ftype *supply_regset,
++ collect_regset_ftype *collect_regset)
++{
++ struct regset *regset = GDBARCH_OBSTACK_ZALLOC (arch, struct regset);
++
++ regset->arch = arch;
++ regset->supply_regset = supply_regset;
++ regset->collect_regset = collect_regset;
++
++ return regset;
++}
+
+ static int microblaze_debug_flag = 0;
+
+@@ -207,9 +270,6 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+ set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
+ set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
+
+- set_gdbarch_regset_from_core_section (gdbarch,
+- microblaze_regset_from_core_section);
+-
+ /* Enable TLS support. */
+ set_gdbarch_fetch_tls_load_module_address (gdbarch,
+ svr4_fetch_objfile_link_map);
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index 02650f61d9..3777cbb6a8 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -24,6 +24,7 @@
+ /* Microblaze architecture-specific information. */
+ struct microblaze_gregset
+ {
++ microblaze_gregset() {}
+ unsigned int gregs[32];
+ unsigned int fpregs[32];
+ unsigned int pregs[16];
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0040-Patch-microblaze-Adding-64-bit-MB-support.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0040-Patch-microblaze-Adding-64-bit-MB-support.patch
new file mode 100644
index 0000000..6582af0
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0040-Patch-microblaze-Adding-64-bit-MB-support.patch
@@ -0,0 +1,1168 @@
+From 34e572e123b166122cc54a8d8e66676c36515711 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Thu, 31 Jan 2019 14:36:00 +0530
+Subject: [PATCH 40/43] [Patch, microblaze]: Adding 64 bit MB support Added new
+ architecture to Microblaze 64-bit support to GDB Signed-off-by :Nagaraju
+ Mekala <nmekala@xilix.com>
+
+Merged on top of binutils work.
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+---
+ bfd/archures.c | 2 +
+ bfd/bfd-in2.h | 2 +
+ bfd/cpu-microblaze.c | 12 +-
+ bfd/elf32-microblaze.c | 93 +-------
+ gas/config/tc-microblaze.c | 16 +-
+ gas/config/tc-microblaze.h | 4 +
+ gdb/Makefile.in | 2 +-
+ gdb/features/Makefile | 3 +
+ gdb/features/microblaze-core.xml | 6 +-
+ gdb/features/microblaze-stack-protect.xml | 4 +-
+ gdb/features/microblaze-with-stack-protect.c | 8 +-
+ gdb/features/microblaze.c | 6 +-
+ gdb/features/microblaze64-core.xml | 69 ++++++
+ gdb/features/microblaze64-stack-protect.xml | 12 +
+ .../microblaze64-with-stack-protect.c | 79 +++++++
+ .../microblaze64-with-stack-protect.xml | 12 +
+ gdb/features/microblaze64.c | 77 +++++++
+ gdb/features/microblaze64.xml | 11 +
+ gdb/microblaze-tdep.c | 207 ++++++++++++++++--
+ gdb/microblaze-tdep.h | 8 +-
+ .../microblaze-with-stack-protect.dat | 4 +-
+ opcodes/microblaze-opc.h | 1 -
+ 22 files changed, 504 insertions(+), 134 deletions(-)
+ create mode 100644 gdb/features/microblaze64-core.xml
+ create mode 100644 gdb/features/microblaze64-stack-protect.xml
+ create mode 100644 gdb/features/microblaze64-with-stack-protect.c
+ create mode 100644 gdb/features/microblaze64-with-stack-protect.xml
+ create mode 100644 gdb/features/microblaze64.c
+ create mode 100644 gdb/features/microblaze64.xml
+
+diff --git a/bfd/archures.c b/bfd/archures.c
+index 647cf0d8d4..3fdf7c3c0e 100644
+--- a/bfd/archures.c
++++ b/bfd/archures.c
+@@ -512,6 +512,8 @@ DESCRIPTION
+ . bfd_arch_lm32, {* Lattice Mico32. *}
+ .#define bfd_mach_lm32 1
+ . bfd_arch_microblaze,{* Xilinx MicroBlaze. *}
++.#define bfd_mach_microblaze 1
++.#define bfd_mach_microblaze64 2
+ . bfd_arch_tilepro, {* Tilera TILEPro. *}
+ . bfd_arch_tilegx, {* Tilera TILE-Gx. *}
+ .#define bfd_mach_tilepro 1
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 33c9cb62d9..db624c62b9 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -2411,6 +2411,8 @@ enum bfd_architecture
+ bfd_arch_lm32, /* Lattice Mico32. */
+ #define bfd_mach_lm32 1
+ bfd_arch_microblaze,/* Xilinx MicroBlaze. */
++#define bfd_mach_microblaze 1
++#define bfd_mach_microblaze64 2
+ bfd_arch_tilepro, /* Tilera TILEPro. */
+ bfd_arch_tilegx, /* Tilera TILE-Gx. */
+ #define bfd_mach_tilepro 1
+diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c
+index c91ba46f75..8e7bcead28 100644
+--- a/bfd/cpu-microblaze.c
++++ b/bfd/cpu-microblaze.c
+@@ -30,8 +30,8 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
+ 64, /* 32 bits in a word. */
+ 64, /* 32 bits in an address. */
+ 8, /* 8 bits in a byte. */
+- bfd_arch_microblaze, /* Architecture. */
+- 0, /* Machine number - 0 for now. */
++ bfd_arch_microblaze, /* Architecture. */
++ bfd_mach_microblaze64, /* 64 bit Machine */
+ "microblaze", /* Architecture name. */
+ "MicroBlaze", /* Printable name. */
+ 3, /* Section align power. */
+@@ -46,7 +46,7 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
+ 32, /* 32 bits in an address. */
+ 8, /* 8 bits in a byte. */
+ bfd_arch_microblaze, /* Architecture. */
+- 0, /* Machine number - 0 for now. */
++ bfd_mach_microblaze, /* 32 bit Machine */
+ "microblaze", /* Architecture name. */
+ "MicroBlaze", /* Printable name. */
+ 3, /* Section align power. */
+@@ -62,7 +62,7 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
+ 32, /* 32 bits in an address. */
+ 8, /* 8 bits in a byte. */
+ bfd_arch_microblaze, /* Architecture. */
+- 0, /* Machine number - 0 for now. */
++ bfd_mach_microblaze, /* 32 bit Machine */
+ "microblaze", /* Architecture name. */
+ "MicroBlaze", /* Printable name. */
+ 3, /* Section align power. */
+@@ -76,8 +76,8 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
+ 64, /* 32 bits in a word. */
+ 64, /* 32 bits in an address. */
+ 8, /* 8 bits in a byte. */
+- bfd_arch_microblaze, /* Architecture. */
+- 0, /* Machine number - 0 for now. */
++ bfd_arch_microblaze, /* Architecture. */
++ bfd_mach_microblaze64, /* 64 bit Machine */
+ "microblaze", /* Architecture name. */
+ "MicroBlaze", /* Printable name. */
+ 3, /* Section align power. */
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index c280431df6..f9996eae12 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -767,87 +767,6 @@ microblaze_elf_is_local_label_name (bfd *abfd, const char *name)
+ return _bfd_elf_is_local_label_name (abfd, name);
+ }
+
+-/* Support for core dump NOTE sections. */
+-static bfd_boolean
+-microblaze_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
+-{
+- int offset;
+- unsigned int size;
+-
+- switch (note->descsz)
+- {
+- default:
+- return FALSE;
+-
+- case 228: /* Linux/MicroBlaze */
+- /* pr_cursig */
+- elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
+-
+- /* pr_pid */
+- elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24);
+-
+- /* pr_reg */
+- offset = 72;
+- size = 50 * 4;
+-
+- break;
+- }
+-
+- /* Make a ".reg/999" section. */
+- return _bfd_elfcore_make_pseudosection (abfd, ".reg",
+- size, note->descpos + offset);
+-}
+-
+-static bfd_boolean
+-microblaze_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
+-{
+- switch (note->descsz)
+- {
+- default:
+- return FALSE;
+-
+- case 128: /* Linux/MicroBlaze elf_prpsinfo */
+- elf_tdata (abfd)->core->program
+- = _bfd_elfcore_strndup (abfd, note->descdata + 32, 16);
+- elf_tdata (abfd)->core->command
+- = _bfd_elfcore_strndup (abfd, note->descdata + 48, 80);
+- }
+-
+- /* Note that for some reason, a spurious space is tacked
+- onto the end of the args in some (at least one anyway)
+- implementations, so strip it off if it exists. */
+-
+- {
+- char *command = elf_tdata (abfd)->core->command;
+- int n = strlen (command);
+-
+- if (0 < n && command[n - 1] == ' ')
+- command[n - 1] = '\0';
+- }
+-
+- return TRUE;
+-}
+-
+-/* The microblaze linker (like many others) needs to keep track of
+- the number of relocs that it decides to copy as dynamic relocs in
+- check_relocs for each symbol. This is so that it can later discard
+- them if they are found to be unnecessary. We store the information
+- in a field extending the regular ELF linker hash table. */
+-
+-struct elf32_mb_dyn_relocs
+-{
+- struct elf32_mb_dyn_relocs *next;
+-
+- /* The input section of the reloc. */
+- asection *sec;
+-
+- /* Total number of relocs copied for the input section. */
+- bfd_size_type count;
+-
+- /* Number of pc-relative relocs copied for the input section. */
+- bfd_size_type pc_count;
+-};
+-
+ /* ELF linker hash entry. */
+
+ struct elf32_mb_link_hash_entry
+@@ -3683,6 +3602,14 @@ microblaze_elf_finish_dynamic_sections (bfd *output_bfd,
+ return TRUE;
+ }
+
++
++static bfd_boolean
++elf_microblaze_object_p (bfd *abfd)
++{
++ /* Set the right machine number for an s390 elf32 file. */
++ return bfd_default_set_arch_mach (abfd, bfd_arch_microblaze, bfd_mach_microblaze);
++}
++
+ /* Hook called by the linker routine which adds symbols from an object
+ file. We use it to put .comm items in .sbss, and not .bss. */
+
+@@ -3752,8 +3679,6 @@ microblaze_elf_add_symbol_hook (bfd *abfd,
+ #define elf_backend_finish_dynamic_symbol microblaze_elf_finish_dynamic_symbol
+ #define elf_backend_size_dynamic_sections microblaze_elf_size_dynamic_sections
+ #define elf_backend_add_symbol_hook microblaze_elf_add_symbol_hook
+-
+-#define elf_backend_grok_prstatus microblaze_elf_grok_prstatus
+-#define elf_backend_grok_psinfo microblaze_elf_grok_psinfo
++#define elf_backend_object_p elf_microblaze_object_p
+
+ #include "elf32-target.h"
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 3ff6a14baf..95a1e69729 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -426,7 +426,10 @@ md_begin (void)
+ const char *prev_name = "";
+
+ opcode_hash_control = hash_new ();
+-
++ if (microblaze_arch_size == 64)
++ bfd_set_arch_mach (stdoutput, bfd_arch_microblaze, bfd_mach_microblaze64);
++ else
++ bfd_set_arch_mach (stdoutput, bfd_arch_microblaze, bfd_mach_microblaze);
+ /* Insert unique names into hash table. */
+ for (opcode = (struct opcodes *)opcodes; opcode->name; opcode ++)
+ {
+@@ -1348,7 +1351,7 @@ md_assemble (char * str)
+ if ((temp != 0) && (temp != 0xFFFF8000))
+ {
+ /* Needs an immediate inst. */
+- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
+ if (opcode1 == NULL)
+ {
+ as_bad (_("unknown opcode \"%s\""), "imm");
+@@ -3431,6 +3434,15 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
+ }
+
+
++unsigned long
++microblaze_mach (void)
++{
++ if (microblaze_arch_size == 64)
++ return bfd_mach_microblaze64;
++ else
++ return bfd_mach_microblaze;
++}
++
+ /* Create a fixup for a cons expression. If parse_cons_expression_microblaze
+ found a machine specific op in an expression,
+ then we create relocs accordingly. */
+diff --git a/gas/config/tc-microblaze.h b/gas/config/tc-microblaze.h
+index 9d38d2ced5..13f58917e7 100644
+--- a/gas/config/tc-microblaze.h
++++ b/gas/config/tc-microblaze.h
+@@ -23,6 +23,10 @@
+ #define TC_MICROBLAZE 1
+
+ #define TARGET_ARCH bfd_arch_microblaze
++#define TARGET_MACH (microblaze_mach ())
++#define DEFAULT_MACHINE bfd_mach_microblaze64
++extern unsigned long microblaze_mach (void);
++
+ #ifndef TARGET_BYTES_BIG_ENDIAN
+ /* Used to initialise target_big_endian. */
+ #define TARGET_BYTES_BIG_ENDIAN 1
+diff --git a/gdb/Makefile.in b/gdb/Makefile.in
+index 8c9a3c07c0..15387197c7 100644
+--- a/gdb/Makefile.in
++++ b/gdb/Makefile.in
+@@ -2265,7 +2265,7 @@ ALLDEPFILES = \
+ m68k-tdep.c \
+ microblaze-linux-tdep.c \
+ microblaze-tdep.c \
+- microblaze-linux-nat.c \
++ microblaze-linux-nat.c \
+ mingw-hdep.c \
+ mips-fbsd-nat.c \
+ mips-fbsd-tdep.c \
+diff --git a/gdb/features/Makefile b/gdb/features/Makefile
+index 3d84ca09a1..fdeec19753 100644
+--- a/gdb/features/Makefile
++++ b/gdb/features/Makefile
+@@ -64,6 +64,7 @@ WHICH = aarch64 \
+ i386/x32-avx-avx512-linux \
+ mips-linux mips-dsp-linux \
+ microblaze-with-stack-protect \
++ microblaze64-with-stack-protect \
+ mips64-linux mips64-dsp-linux \
+ nios2-linux \
+ rs6000/powerpc-32 \
+@@ -135,7 +136,9 @@ XMLTOC = \
+ arm/arm-with-vfpv2.xml \
+ arm/arm-with-vfpv3.xml \
+ microblaze-with-stack-protect.xml \
++ microblaze64-with-stack-protect.xml \
+ microblaze.xml \
++ microblaze64.xml \
+ mips-dsp-linux.xml \
+ mips-linux.xml \
+ mips64-dsp-linux.xml \
+diff --git a/gdb/features/microblaze-core.xml b/gdb/features/microblaze-core.xml
+index 88c93e5d66..5bc3e49f84 100644
+--- a/gdb/features/microblaze-core.xml
++++ b/gdb/features/microblaze-core.xml
+@@ -8,7 +8,7 @@
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <feature name="org.gnu.gdb.microblaze.core">
+ <reg name="r0" bitsize="32" regnum="0"/>
+- <reg name="r1" bitsize="32" type="data_ptr"/>
++ <reg name="r1" bitsize="32"/>
+ <reg name="r2" bitsize="32"/>
+ <reg name="r3" bitsize="32"/>
+ <reg name="r4" bitsize="32"/>
+@@ -39,7 +39,7 @@
+ <reg name="r29" bitsize="32"/>
+ <reg name="r30" bitsize="32"/>
+ <reg name="r31" bitsize="32"/>
+- <reg name="rpc" bitsize="32" type="code_ptr"/>
++ <reg name="rpc" bitsize="32"/>
+ <reg name="rmsr" bitsize="32"/>
+ <reg name="rear" bitsize="32"/>
+ <reg name="resr" bitsize="32"/>
+@@ -64,4 +64,6 @@
+ <reg name="rtlbsx" bitsize="32"/>
+ <reg name="rtlblo" bitsize="32"/>
+ <reg name="rtlbhi" bitsize="32"/>
++ <reg name="slr" bitsize="32"/>
++ <reg name="shr" bitsize="32"/>
+ </feature>
+diff --git a/gdb/features/microblaze-stack-protect.xml b/gdb/features/microblaze-stack-protect.xml
+index 870c148bb0..a7f27b903c 100644
+--- a/gdb/features/microblaze-stack-protect.xml
++++ b/gdb/features/microblaze-stack-protect.xml
+@@ -7,6 +7,6 @@
+
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <feature name="org.gnu.gdb.microblaze.stack-protect">
+- <reg name="rslr" bitsize="32"/>
+- <reg name="rshr" bitsize="32"/>
++ <reg name="slr" bitsize="32"/>
++ <reg name="shr" bitsize="32"/>
+ </feature>
+diff --git a/gdb/features/microblaze-with-stack-protect.c b/gdb/features/microblaze-with-stack-protect.c
+index b39aa19887..609934e2b4 100644
+--- a/gdb/features/microblaze-with-stack-protect.c
++++ b/gdb/features/microblaze-with-stack-protect.c
+@@ -14,7 +14,7 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.core");
+ tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
+- tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
+@@ -45,7 +45,7 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+ tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
+- tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
+@@ -72,8 +72,8 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.stack-protect");
+- tdesc_create_reg (feature, "rslr", 57, 1, NULL, 32, "int");
+- tdesc_create_reg (feature, "rshr", 58, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int");
+
+ tdesc_microblaze_with_stack_protect = result;
+ }
+diff --git a/gdb/features/microblaze.c b/gdb/features/microblaze.c
+index 6c86fc0770..ceb98ca8b8 100644
+--- a/gdb/features/microblaze.c
++++ b/gdb/features/microblaze.c
+@@ -14,7 +14,7 @@ initialize_tdesc_microblaze (void)
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.core");
+ tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
+- tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
+@@ -45,7 +45,7 @@ initialize_tdesc_microblaze (void)
+ tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
+- tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
+@@ -70,6 +70,8 @@ initialize_tdesc_microblaze (void)
+ tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
+
+ tdesc_microblaze = result;
+ }
+diff --git a/gdb/features/microblaze64-core.xml b/gdb/features/microblaze64-core.xml
+new file mode 100644
+index 0000000000..96e99e2fb2
+--- /dev/null
++++ b/gdb/features/microblaze64-core.xml
+@@ -0,0 +1,69 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++ Copying and distribution of this file, with or without modification,
++ are permitted in any medium without royalty provided the copyright
++ notice and this notice are preserved. -->
++
++<!DOCTYPE feature SYSTEM "gdb-target.dtd">
++<feature name="org.gnu.gdb.microblaze64.core">
++ <reg name="r0" bitsize="64" regnum="0"/>
++ <reg name="r1" bitsize="64"/>
++ <reg name="r2" bitsize="64"/>
++ <reg name="r3" bitsize="64"/>
++ <reg name="r4" bitsize="64"/>
++ <reg name="r5" bitsize="64"/>
++ <reg name="r6" bitsize="64"/>
++ <reg name="r7" bitsize="64"/>
++ <reg name="r8" bitsize="64"/>
++ <reg name="r9" bitsize="64"/>
++ <reg name="r10" bitsize="64"/>
++ <reg name="r11" bitsize="64"/>
++ <reg name="r12" bitsize="64"/>
++ <reg name="r13" bitsize="64"/>
++ <reg name="r14" bitsize="64"/>
++ <reg name="r15" bitsize="64"/>
++ <reg name="r16" bitsize="64"/>
++ <reg name="r17" bitsize="64"/>
++ <reg name="r18" bitsize="64"/>
++ <reg name="r19" bitsize="64"/>
++ <reg name="r20" bitsize="64"/>
++ <reg name="r21" bitsize="64"/>
++ <reg name="r22" bitsize="64"/>
++ <reg name="r23" bitsize="64"/>
++ <reg name="r24" bitsize="64"/>
++ <reg name="r25" bitsize="64"/>
++ <reg name="r26" bitsize="64"/>
++ <reg name="r27" bitsize="64"/>
++ <reg name="r28" bitsize="64"/>
++ <reg name="r29" bitsize="64"/>
++ <reg name="r30" bitsize="64"/>
++ <reg name="r31" bitsize="64"/>
++ <reg name="rpc" bitsize="64"/>
++ <reg name="rmsr" bitsize="32"/>
++ <reg name="rear" bitsize="64"/>
++ <reg name="resr" bitsize="32"/>
++ <reg name="rfsr" bitsize="32"/>
++ <reg name="rbtr" bitsize="64"/>
++ <reg name="rpvr0" bitsize="32"/>
++ <reg name="rpvr1" bitsize="32"/>
++ <reg name="rpvr2" bitsize="32"/>
++ <reg name="rpvr3" bitsize="32"/>
++ <reg name="rpvr4" bitsize="32"/>
++ <reg name="rpvr5" bitsize="32"/>
++ <reg name="rpvr6" bitsize="32"/>
++ <reg name="rpvr7" bitsize="32"/>
++ <reg name="rpvr8" bitsize="64"/>
++ <reg name="rpvr9" bitsize="64"/>
++ <reg name="rpvr10" bitsize="32"/>
++ <reg name="rpvr11" bitsize="32"/>
++ <reg name="redr" bitsize="32"/>
++ <reg name="rpid" bitsize="32"/>
++ <reg name="rzpr" bitsize="32"/>
++ <reg name="rtlbx" bitsize="32"/>
++ <reg name="rtlbsx" bitsize="32"/>
++ <reg name="rtlblo" bitsize="32"/>
++ <reg name="rtlbhi" bitsize="32"/>
++ <reg name="slr" bitsize="64"/>
++ <reg name="shr" bitsize="64"/>
++</feature>
+diff --git a/gdb/features/microblaze64-stack-protect.xml b/gdb/features/microblaze64-stack-protect.xml
+new file mode 100644
+index 0000000000..1bbf5fc3ce
+--- /dev/null
++++ b/gdb/features/microblaze64-stack-protect.xml
+@@ -0,0 +1,12 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++ Copying and distribution of this file, with or without modification,
++ are permitted in any medium without royalty provided the copyright
++ notice and this notice are preserved. -->
++
++<!DOCTYPE feature SYSTEM "gdb-target.dtd">
++<feature name="org.gnu.gdb.microblaze64.stack-protect">
++ <reg name="slr" bitsize="64"/>
++ <reg name="shr" bitsize="64"/>
++</feature>
+diff --git a/gdb/features/microblaze64-with-stack-protect.c b/gdb/features/microblaze64-with-stack-protect.c
+new file mode 100644
+index 0000000000..f448c9a749
+--- /dev/null
++++ b/gdb/features/microblaze64-with-stack-protect.c
+@@ -0,0 +1,79 @@
++/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
++ Original: microblaze-with-stack-protect.xml */
++
++#include "defs.h"
++#include "osabi.h"
++#include "target-descriptions.h"
++
++struct target_desc *tdesc_microblaze64_with_stack_protect;
++static void
++initialize_tdesc_microblaze64_with_stack_protect (void)
++{
++ struct target_desc *result = allocate_target_description ();
++ struct tdesc_feature *feature;
++
++ feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.core");
++ tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "int");
++ tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
++
++ feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.stack-protect");
++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++
++ tdesc_microblaze64_with_stack_protect = result;
++}
+diff --git a/gdb/features/microblaze64-with-stack-protect.xml b/gdb/features/microblaze64-with-stack-protect.xml
+new file mode 100644
+index 0000000000..0e9f01611f
+--- /dev/null
++++ b/gdb/features/microblaze64-with-stack-protect.xml
+@@ -0,0 +1,12 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++ Copying and distribution of this file, with or without modification,
++ are permitted in any medium without royalty provided the copyright
++ notice and this notice are preserved. -->
++
++<!DOCTYPE target SYSTEM "gdb-target.dtd">
++<target>
++ <xi:include href="microblaze64-core.xml"/>
++ <xi:include href="microblaze64-stack-protect.xml"/>
++</target>
+diff --git a/gdb/features/microblaze64.c b/gdb/features/microblaze64.c
+new file mode 100644
+index 0000000000..1aa37c4512
+--- /dev/null
++++ b/gdb/features/microblaze64.c
+@@ -0,0 +1,77 @@
++/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
++ Original: microblaze.xml */
++
++#include "defs.h"
++#include "osabi.h"
++#include "target-descriptions.h"
++
++struct target_desc *tdesc_microblaze64;
++static void
++initialize_tdesc_microblaze64 (void)
++{
++ struct target_desc *result = allocate_target_description ();
++ struct tdesc_feature *feature;
++
++ feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.core");
++ tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++
++ tdesc_microblaze64 = result;
++}
+diff --git a/gdb/features/microblaze64.xml b/gdb/features/microblaze64.xml
+new file mode 100644
+index 0000000000..515d18e65c
+--- /dev/null
++++ b/gdb/features/microblaze64.xml
+@@ -0,0 +1,11 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++ Copying and distribution of this file, with or without modification,
++ are permitted in any medium without royalty provided the copyright
++ notice and this notice are preserved. -->
++
++<!DOCTYPE target SYSTEM "gdb-target.dtd">
++<target>
++ <xi:include href="microblaze64-core.xml"/>
++</target>
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 49713ea9b1..0605283c9e 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -40,7 +40,9 @@
+ #include "remote.h"
+
+ #include "features/microblaze-with-stack-protect.c"
++#include "features/microblaze64-with-stack-protect.c"
+ #include "features/microblaze.c"
++#include "features/microblaze64.c"
+
+ /* Instruction macros used for analyzing the prologue. */
+ /* This set of instruction macros need to be changed whenever the
+@@ -75,12 +77,13 @@ static const char *microblaze_register_names[] =
+ "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6",
+ "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11",
+ "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi",
+- "rslr", "rshr"
++ "slr", "shr"
+ };
+
+ #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names)
+
+ static unsigned int microblaze_debug_flag = 0;
++int reg_size = 4;
+
+ static void ATTRIBUTE_PRINTF (1, 2)
+ microblaze_debug (const char *fmt, ...)
+@@ -145,6 +148,7 @@ microblaze_store_arguments (struct regcache *regcache, int nargs,
+ error (_("store_arguments not implemented"));
+ return sp;
+ }
++#if 0
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ struct bp_target_info *bp_tgt)
+@@ -154,7 +158,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ int val;
+ int bplen;
+ gdb_byte old_contents[BREAKPOINT_MAX];
+- struct cleanup *cleanup;
++ //struct cleanup *cleanup;
+
+ /* Determine appropriate breakpoint contents and size for this address. */
+ bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
+@@ -162,7 +166,8 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ error (_("Software breakpoints not implemented for this target."));
+
+ /* Make sure we see the memory breakpoints. */
+- cleanup = make_show_memory_breakpoints_cleanup (1);
++ scoped_restore
++ cleanup = make_scoped_restore_show_memory_breakpoints (1);
+ val = target_read_memory (addr, old_contents, bplen);
+
+ /* If our breakpoint is no longer at the address, this means that the
+@@ -178,6 +183,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ return val;
+ }
+
++#endif
+ /* Allocate and initialize a frame cache. */
+
+ static struct microblaze_frame_cache *
+@@ -570,17 +576,16 @@ microblaze_extract_return_value (struct type *type, struct regcache *regcache,
+ gdb_byte *valbuf)
+ {
+ gdb_byte buf[8];
+-
+ /* Copy the return value (starting) in RETVAL_REGNUM to VALBUF. */
+ switch (TYPE_LENGTH (type))
+ {
+ case 1: /* return last byte in the register. */
+ regcache->cooked_read (MICROBLAZE_RETVAL_REGNUM, buf);
+- memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 1, 1);
++ memcpy(valbuf, buf + reg_size - 1, 1);
+ return;
+ case 2: /* return last 2 bytes in register. */
+ regcache->cooked_read (MICROBLAZE_RETVAL_REGNUM, buf);
+- memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 2, 2);
++ memcpy(valbuf, buf + reg_size - 2, 2);
+ return;
+ case 4: /* for sizes 4 or 8, copy the required length. */
+ case 8:
+@@ -647,7 +652,119 @@ microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
+ return (TYPE_LENGTH (type) == 16);
+ }
+
+-
++#if 0
++static std::vector<CORE_ADDR>
++microblaze_software_single_step (struct regcache *regcache)
++{
++// struct gdbarch *arch = get_frame_arch(frame);
++ struct gdbarch *arch = get_regcache_arch (regcache);
++ struct address_space *aspace = get_regcache_aspace (regcache);
++// struct address_space *aspace = get_frame_address_space (frame);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
++ static char le_breakp[] = MICROBLAZE_BREAKPOINT_LE;
++ static char be_breakp[] = MICROBLAZE_BREAKPOINT;
++ enum bfd_endian byte_order = gdbarch_byte_order (arch);
++ char *breakp = byte_order == BFD_ENDIAN_BIG ? be_breakp : le_breakp;
++ std::vector<CORE_ADDR> ret = 0;
++
++ /* Save the address and the values of the next_pc and the target */
++ static struct sstep_breaks
++ {
++ CORE_ADDR address;
++ bfd_boolean valid;
++ /* Shadow contents. */
++ char data[INST_WORD_SIZE];
++ } stepbreaks[2];
++ int ii;
++
++ if (1)
++ {
++ CORE_ADDR pc;
++ std::vector<CORE_ADDR> *next_pcs = NULL;
++ long insn;
++ enum microblaze_instr minstr;
++ bfd_boolean isunsignednum;
++ enum microblaze_instr_type insn_type;
++ short delay_slots;
++ int imm;
++ bfd_boolean immfound = FALSE;
++
++ /* Set a breakpoint at the next instruction */
++ /* If the current instruction is an imm, set it at the inst after */
++ /* If the instruction has a delay slot, skip the delay slot */
++ pc = regcache_read_pc (regcache);
++ insn = microblaze_fetch_instruction (pc);
++ minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots);
++ if (insn_type == immediate_inst)
++ {
++ int rd, ra, rb;
++ immfound = TRUE;
++ minstr = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
++ pc = pc + INST_WORD_SIZE;
++ insn = microblaze_fetch_instruction (pc);
++ minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots);
++ }
++ stepbreaks[0].address = pc + (delay_slots * INST_WORD_SIZE) + INST_WORD_SIZE;
++ if (insn_type != return_inst) {
++ stepbreaks[0].valid = TRUE;
++ } else {
++ stepbreaks[0].valid = FALSE;
++ }
++
++ microblaze_debug ("single-step insn_type=%x insn=%x\n", insn_type, insn);
++ /* Now check for branch or return instructions */
++ if (insn_type == branch_inst || insn_type == return_inst) {
++ int limm;
++ int lrd, lra, lrb;
++ int ra, rb;
++ bfd_boolean targetvalid;
++ bfd_boolean unconditionalbranch;
++ microblaze_decode_insn(insn, &lrd, &lra, &lrb, &limm);
++ if (lra >= 0 && lra < MICROBLAZE_NUM_REGS)
++ ra = regcache_raw_get_unsigned(regcache, lra);
++ else
++ ra = 0;
++ if (lrb >= 0 && lrb < MICROBLAZE_NUM_REGS)
++ rb = regcache_raw_get_unsigned(regcache, lrb);
++ else
++ rb = 0;
++ stepbreaks[1].address = microblaze_get_target_address (insn, immfound, imm, pc, ra, rb, &targetvalid, &unconditionalbranch);
++ microblaze_debug ("single-step uncondbr=%d targetvalid=%d target=%x\n", unconditionalbranch, targetvalid, stepbreaks[1].address);
++ if (unconditionalbranch)
++ stepbreaks[0].valid = FALSE; /* This is a unconditional branch: will not come to the next address */
++ if (targetvalid && (stepbreaks[0].valid == FALSE ||
++ (stepbreaks[0].address != stepbreaks[1].address))
++ && (stepbreaks[1].address != pc)) {
++ stepbreaks[1].valid = TRUE;
++ } else {
++ stepbreaks[1].valid = FALSE;
++ }
++ } else {
++ stepbreaks[1].valid = FALSE;
++ }
++
++ /* Insert the breakpoints */
++ for (ii = 0; ii < 2; ++ii)
++ {
++
++ /* ignore invalid breakpoint. */
++ if (stepbreaks[ii].valid) {
++ VEC_safe_push (CORE_ADDR, next_pcs, stepbreaks[ii].address);;
++// insert_single_step_breakpoint (arch, aspace, stepbreaks[ii].address);
++ ret = next_pcs;
++ }
++ }
++ }
++ return ret;
++}
++#endif
++
++static void
++microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc)
++{
++ regcache_cooked_write_unsigned (regcache, MICROBLAZE_PC_REGNUM, pc);
++}
++
+ static int dwarf2_to_reg_map[78] =
+ { 0 /* r0 */, 1 /* r1 */, 2 /* r2 */, 3 /* r3 */, /* 0- 3 */
+ 4 /* r4 */, 5 /* r5 */, 6 /* r6 */, 7 /* r7 */, /* 4- 7 */
+@@ -682,13 +799,14 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
+ static void
+ microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
+ {
++
+ register_remote_g_packet_guess (gdbarch,
+- 4 * MICROBLAZE_NUM_CORE_REGS,
+- tdesc_microblaze);
++ 4 * MICROBLAZE_NUM_REGS,
++ tdesc_microblaze64);
+
+ register_remote_g_packet_guess (gdbarch,
+ 4 * MICROBLAZE_NUM_REGS,
+- tdesc_microblaze_with_stack_protect);
++ tdesc_microblaze64_with_stack_protect);
+ }
+
+ void
+@@ -696,15 +814,15 @@ microblaze_supply_gregset (const struct microblaze_gregset *gregset,
+ struct regcache *regcache,
+ int regnum, const void *gregs)
+ {
+- unsigned int *regs = gregs;
++ const gdb_byte *regs = (const gdb_byte *) gregs;
+ if (regnum >= 0)
+- regcache_raw_supply (regcache, regnum, regs + regnum);
++ regcache->raw_supply (regnum, regs + regnum);
+
+ if (regnum == -1) {
+ int i;
+
+ for (i = 0; i < 50; i++) {
+- regcache_raw_supply (regcache, i, regs + i);
++ regcache->raw_supply (regnum, regs + i);
+ }
+ }
+ }
+@@ -755,6 +873,17 @@ microblaze_regset_from_core_section (struct gdbarch *gdbarch,
+ }
+
+
++static void
++make_regs (struct gdbarch *arch)
++{
++ struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
++ int mach = gdbarch_bfd_arch_info (arch)->mach;
++
++ if (mach == bfd_mach_microblaze64)
++ {
++ set_gdbarch_ptr_bit (arch, 64);
++ }
++}
+
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+@@ -769,8 +898,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ if (arches != NULL)
+ return arches->gdbarch;
+ if (tdesc == NULL)
+- tdesc = tdesc_microblaze;
+-
++ {
++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
++ {
++ tdesc = tdesc_microblaze64;
++ reg_size = 8;
++ }
++ else
++ tdesc = tdesc_microblaze;
++ }
+ /* Check any target description for validity. */
+ if (tdesc_has_registers (tdesc))
+ {
+@@ -778,27 +914,35 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ int valid_p;
+ int i;
+
+- feature = tdesc_find_feature (tdesc,
++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
++ feature = tdesc_find_feature (tdesc,
++ "org.gnu.gdb.microblaze64.core");
++ else
++ feature = tdesc_find_feature (tdesc,
+ "org.gnu.gdb.microblaze.core");
+ if (feature == NULL)
+ return NULL;
+ tdesc_data = tdesc_data_alloc ();
+
+ valid_p = 1;
+- for (i = 0; i < MICROBLAZE_NUM_CORE_REGS; i++)
++ for (i = 0; i < MICROBLAZE_NUM_REGS; i++)
+ valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
+ microblaze_register_names[i]);
+- feature = tdesc_find_feature (tdesc,
++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
++ feature = tdesc_find_feature (tdesc,
++ "org.gnu.gdb.microblaze64.stack-protect");
++ else
++ feature = tdesc_find_feature (tdesc,
+ "org.gnu.gdb.microblaze.stack-protect");
+ if (feature != NULL)
+ {
+ valid_p = 1;
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ MICROBLAZE_SLR_REGNUM,
+- "rslr");
++ "slr");
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ MICROBLAZE_SHR_REGNUM,
+- "rshr");
++ "shr");
+ }
+
+ if (!valid_p)
+@@ -806,6 +950,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ tdesc_data_cleanup (tdesc_data);
+ return NULL;
+ }
++
+ }
+
+ /* Allocate space for the new architecture. */
+@@ -825,7 +970,17 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ /* Register numbers of various important registers. */
+ set_gdbarch_sp_regnum (gdbarch, MICROBLAZE_SP_REGNUM);
+ set_gdbarch_pc_regnum (gdbarch, MICROBLAZE_PC_REGNUM);
++
++ /* Register set.
++ make_regs (gdbarch); */
++ switch (info.bfd_arch_info->mach)
++ {
++ case bfd_mach_microblaze64:
++ set_gdbarch_ptr_bit (gdbarch, 64);
++ break;
++ }
+
++
+ /* Map Dwarf2 registers to GDB registers. */
+ set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum);
+
+@@ -845,13 +1000,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ microblaze_breakpoint::kind_from_pc);
+ set_gdbarch_sw_breakpoint_from_kind (gdbarch,
+ microblaze_breakpoint::bp_from_kind);
+- set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
++// set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
++
++// set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
+
+ set_gdbarch_frame_args_skip (gdbarch, 8);
+
+ set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc);
+
+- microblaze_register_g_packet_guesses (gdbarch);
++ //microblaze_register_g_packet_guesses (gdbarch);
+
+ frame_base_set_default (gdbarch, µblaze_frame_base);
+
+@@ -866,11 +1023,11 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ tdesc_use_registers (gdbarch, tdesc, tdesc_data);
+ //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer);
+
+- /* If we have register sets, enable the generic core file support. */
++ /* If we have register sets, enable the generic core file support.
+ if (tdep->gregset) {
+ set_gdbarch_regset_from_core_section (gdbarch,
+ microblaze_regset_from_core_section);
+- }
++ }*/
+
+ return gdbarch;
+ }
+@@ -882,6 +1039,8 @@ _initialize_microblaze_tdep (void)
+
+ initialize_tdesc_microblaze_with_stack_protect ();
+ initialize_tdesc_microblaze ();
++ initialize_tdesc_microblaze64_with_stack_protect ();
++ initialize_tdesc_microblaze64 ();
+ /* Debug this files internals. */
+ add_setshow_zuinteger_cmd ("microblaze", class_maintenance,
+ µblaze_debug_flag, _("\
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index 3777cbb6a8..55f5dd1962 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -27,7 +27,7 @@ struct microblaze_gregset
+ microblaze_gregset() {}
+ unsigned int gregs[32];
+ unsigned int fpregs[32];
+- unsigned int pregs[16];
++ unsigned int pregs[18];
+ };
+
+ struct gdbarch_tdep
+@@ -101,9 +101,9 @@ enum microblaze_regnum
+ MICROBLAZE_RTLBSX_REGNUM,
+ MICROBLAZE_RTLBLO_REGNUM,
+ MICROBLAZE_RTLBHI_REGNUM,
+- MICROBLAZE_SLR_REGNUM, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_SLR_REGNUM,
++ MICROBLAZE_SLR_REGNUM,
+ MICROBLAZE_SHR_REGNUM,
+- MICROBLAZE_NUM_REGS
++ MICROBLAZE_NUM_REGS, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_NUM_REGS
+ };
+
+ struct microblaze_frame_cache
+@@ -128,7 +128,7 @@ struct microblaze_frame_cache
+ struct trad_frame_saved_reg *saved_regs;
+ };
+ /* All registers are 32 bits. */
+-#define MICROBLAZE_REGISTER_SIZE 4
++//#define MICROBLAZE_REGISTER_SIZE 8
+
+ /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used.
+ Only used for native debugging. */
+diff --git a/gdb/regformats/microblaze-with-stack-protect.dat b/gdb/regformats/microblaze-with-stack-protect.dat
+index 8040a7b3fd..450e321d49 100644
+--- a/gdb/regformats/microblaze-with-stack-protect.dat
++++ b/gdb/regformats/microblaze-with-stack-protect.dat
+@@ -60,5 +60,5 @@ expedite:r1,rpc
+ 32:rtlbsx
+ 32:rtlblo
+ 32:rtlbhi
+-32:rslr
+-32:rshr
++32:slr
++32:shr
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index bd9d91cd57..12d4456bc2 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -134,7 +134,6 @@
+ #define ORLI_MASK 0xA0000000
+ #define XORLI_MASK 0xA8000000
+
+-
+ /* New Mask for msrset, msrclr insns. */
+ #define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */
+ /* Mask for mbar insn. */
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0041-patch-MicroBlaze-porting-GDB-for-linux.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0041-patch-MicroBlaze-porting-GDB-for-linux.patch
new file mode 100644
index 0000000..1a0153b
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0041-patch-MicroBlaze-porting-GDB-for-linux.patch
@@ -0,0 +1,155 @@
+From 07757f455d343beb50ac04815c77b04075bf9534 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 12 Dec 2019 14:56:17 +0530
+Subject: [PATCH 41/43] [patch,MicroBlaze] : porting GDB for linux
+
+---
+ gdb/features/microblaze-linux.xml | 12 ++++++++++
+ gdb/gdbserver/Makefile.in | 2 ++
+ gdb/gdbserver/configure.srv | 3 ++-
+ gdb/microblaze-linux-tdep.c | 39 ++++++++++++++++++++++++-------
+ 4 files changed, 47 insertions(+), 9 deletions(-)
+ create mode 100644 gdb/features/microblaze-linux.xml
+
+diff --git a/gdb/features/microblaze-linux.xml b/gdb/features/microblaze-linux.xml
+new file mode 100644
+index 0000000000..8983e66eb3
+--- /dev/null
++++ b/gdb/features/microblaze-linux.xml
+@@ -0,0 +1,12 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++ Copying and distribution of this file, with or without modification,
++ are permitted in any medium without royalty provided the copyright
++ notice and this notice are preserved. -->
++
++<!DOCTYPE target SYSTEM "gdb-target.dtd">
++<target>
++ <osabi>GNU/Linux</osabi>
++ <xi:include href="microblaze-core.xml"/>
++</target>
+diff --git a/gdb/gdbserver/Makefile.in b/gdb/gdbserver/Makefile.in
+index 45d95e6cab..7c8fa3c246 100644
+--- a/gdb/gdbserver/Makefile.in
++++ b/gdb/gdbserver/Makefile.in
+@@ -633,6 +633,8 @@ common/%.o: ../common/%.c
+
+ %-generated.c: ../regformats/rs6000/%.dat | $(regdat_sh)
+ $(ECHO_REGDAT) $(SHELL) $(regdat_sh) $< $@
++microblaze-linux.c : $(srcdir)/../regformats/reg-microblaze.dat $(regdat_sh)
++ $(ECHO_REGDAT) $(SHELL) $(regdat_sh) $(srcdir)/../regformats/reg-microblaze.dat microblaze-linux.c
+
+ #
+ # Dependency tracking.
+diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
+index c421790bd0..6ad0ac9fa6 100644
+--- a/gdb/gdbserver/configure.srv
++++ b/gdb/gdbserver/configure.srv
+@@ -210,8 +210,9 @@ case "${target}" in
+ srv_linux_usrregs=yes
+ srv_linux_thread_db=yes
+ ;;
+- microblaze*-*-linux*) srv_regobj=microblaze-linux.o
++ microblaze*-*-linux*) srv_regobj="microblaze-linux.o"
+ srv_tgtobj="$srv_linux_obj linux-microblaze-low.o "
++ srv_xmlfiles="microblaze-linux.xml"
+ srv_linux_regsets=yes
+ srv_linux_usrregs=yes
+ srv_linux_thread_db=yes
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index 011e513941..e3d2a7508d 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -41,7 +41,7 @@
+
+ #ifndef REGSET_H
+ #define REGSET_H 1
+-
++int MICROBLAZE_REGISTER_SIZE=4;
+ struct gdbarch;
+ struct regcache;
+
+@@ -115,7 +115,7 @@ microblaze_debug (const char *fmt, ...)
+ va_end (args);
+ }
+ }
+-
++#if 0
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ struct bp_target_info *bp_tgt)
+@@ -131,7 +131,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
+
+ /* Make sure we see the memory breakpoints. */
+- cleanup = make_show_memory_breakpoints_cleanup (1);
++ cleanup = make_scoped_restore_show_memory_breakpoints (1);
+ val = target_read_memory (addr, old_contents, bplen);
+
+ /* If our breakpoint is no longer at the address, this means that the
+@@ -146,6 +146,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ do_cleanups (cleanup);
+ return val;
+ }
++#endif
+
+ static void
+ microblaze_linux_sigtramp_cache (struct frame_info *next_frame,
+@@ -248,8 +249,8 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+
+ linux_init_abi (info, gdbarch);
+
+- set_gdbarch_memory_remove_breakpoint (gdbarch,
+- microblaze_linux_memory_remove_breakpoint);
++// set_gdbarch_memory_remove_breakpoint (gdbarch,
++// microblaze_linux_memory_remove_breakpoint);
+
+ /* Shared library handling. */
+ set_solib_svr4_fetch_link_map_offsets (gdbarch,
+@@ -261,10 +262,30 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+
+ /* BFD target for core files. */
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+- set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++ {
++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) {
++ set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblaze");
++ MICROBLAZE_REGISTER_SIZE=8;
++ }
++ else
++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++ }
+ else
+- set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++ {
++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) {
++ set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblazeel");
++ MICROBLAZE_REGISTER_SIZE=8;
++ }
++ else
++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++ }
+
++ switch (info.bfd_arch_info->mach)
++ {
++ case bfd_mach_microblaze64:
++ set_gdbarch_ptr_bit (gdbarch, 64);
++ break;
++ }
+
+ /* Shared library handling. */
+ set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
+@@ -278,6 +299,8 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+ void
+ _initialize_microblaze_linux_tdep (void)
+ {
+- gdbarch_register_osabi (bfd_arch_microblaze, 0, GDB_OSABI_LINUX,
++ gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze, GDB_OSABI_LINUX,
++ microblaze_linux_init_abi);
++ gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze64, GDB_OSABI_LINUX,
+ microblaze_linux_init_abi);
+ }
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0042-Correcting-the-register-names-from-slr-shr-to-rslr-r.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0042-Correcting-the-register-names-from-slr-shr-to-rslr-r.patch
new file mode 100644
index 0000000..ad8dcb5
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0042-Correcting-the-register-names-from-slr-shr-to-rslr-r.patch
@@ -0,0 +1,146 @@
+From c2a4667e87bd610a48a6690fcc9fdc6761398bcf Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Thu, 19 Dec 2019 12:22:04 +0530
+Subject: [PATCH 42/43] Correcting the register names from slr & shr to rslr &
+ rshr
+
+---
+ gdb/features/microblaze-core.xml | 4 ++--
+ gdb/features/microblaze-stack-protect.xml | 4 ++--
+ gdb/features/microblaze-with-stack-protect.c | 4 ++--
+ gdb/features/microblaze.c | 4 ++--
+ gdb/features/microblaze64-core.xml | 4 ++--
+ gdb/features/microblaze64-stack-protect.xml | 4 ++--
+ gdb/features/microblaze64-with-stack-protect.c | 4 ++--
+ gdb/features/microblaze64.c | 4 ++--
+ gdb/microblaze-tdep.c | 2 +-
+ 9 files changed, 17 insertions(+), 17 deletions(-)
+
+diff --git a/gdb/features/microblaze-core.xml b/gdb/features/microblaze-core.xml
+index 5bc3e49f84..6f73f4eb84 100644
+--- a/gdb/features/microblaze-core.xml
++++ b/gdb/features/microblaze-core.xml
+@@ -64,6 +64,6 @@
+ <reg name="rtlbsx" bitsize="32"/>
+ <reg name="rtlblo" bitsize="32"/>
+ <reg name="rtlbhi" bitsize="32"/>
+- <reg name="slr" bitsize="32"/>
+- <reg name="shr" bitsize="32"/>
++ <reg name="rslr" bitsize="32"/>
++ <reg name="rshr" bitsize="32"/>
+ </feature>
+diff --git a/gdb/features/microblaze-stack-protect.xml b/gdb/features/microblaze-stack-protect.xml
+index a7f27b903c..870c148bb0 100644
+--- a/gdb/features/microblaze-stack-protect.xml
++++ b/gdb/features/microblaze-stack-protect.xml
+@@ -7,6 +7,6 @@
+
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <feature name="org.gnu.gdb.microblaze.stack-protect">
+- <reg name="slr" bitsize="32"/>
+- <reg name="shr" bitsize="32"/>
++ <reg name="rslr" bitsize="32"/>
++ <reg name="rshr" bitsize="32"/>
+ </feature>
+diff --git a/gdb/features/microblaze-with-stack-protect.c b/gdb/features/microblaze-with-stack-protect.c
+index 609934e2b4..ab162fd258 100644
+--- a/gdb/features/microblaze-with-stack-protect.c
++++ b/gdb/features/microblaze-with-stack-protect.c
+@@ -72,8 +72,8 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.stack-protect");
+- tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int");
+- tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rslr", 57, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rshr", 58, 1, NULL, 32, "int");
+
+ tdesc_microblaze_with_stack_protect = result;
+ }
+diff --git a/gdb/features/microblaze.c b/gdb/features/microblaze.c
+index ceb98ca8b8..7919ac96e6 100644
+--- a/gdb/features/microblaze.c
++++ b/gdb/features/microblaze.c
+@@ -70,8 +70,8 @@ initialize_tdesc_microblaze (void)
+ tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+- tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
+- tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64");
+
+ tdesc_microblaze = result;
+ }
+diff --git a/gdb/features/microblaze64-core.xml b/gdb/features/microblaze64-core.xml
+index 96e99e2fb2..b9adadfade 100644
+--- a/gdb/features/microblaze64-core.xml
++++ b/gdb/features/microblaze64-core.xml
+@@ -64,6 +64,6 @@
+ <reg name="rtlbsx" bitsize="32"/>
+ <reg name="rtlblo" bitsize="32"/>
+ <reg name="rtlbhi" bitsize="32"/>
+- <reg name="slr" bitsize="64"/>
+- <reg name="shr" bitsize="64"/>
++ <reg name="rslr" bitsize="64"/>
++ <reg name="rshr" bitsize="64"/>
+ </feature>
+diff --git a/gdb/features/microblaze64-stack-protect.xml b/gdb/features/microblaze64-stack-protect.xml
+index 1bbf5fc3ce..9d7ea8b9fd 100644
+--- a/gdb/features/microblaze64-stack-protect.xml
++++ b/gdb/features/microblaze64-stack-protect.xml
+@@ -7,6 +7,6 @@
+
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <feature name="org.gnu.gdb.microblaze64.stack-protect">
+- <reg name="slr" bitsize="64"/>
+- <reg name="shr" bitsize="64"/>
++ <reg name="rslr" bitsize="64"/>
++ <reg name="rshr" bitsize="64"/>
+ </feature>
+diff --git a/gdb/features/microblaze64-with-stack-protect.c b/gdb/features/microblaze64-with-stack-protect.c
+index f448c9a749..249cb534da 100644
+--- a/gdb/features/microblaze64-with-stack-protect.c
++++ b/gdb/features/microblaze64-with-stack-protect.c
+@@ -72,8 +72,8 @@ initialize_tdesc_microblaze64_with_stack_protect (void)
+ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.stack-protect");
+- tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
+- tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64");
+
+ tdesc_microblaze64_with_stack_protect = result;
+ }
+diff --git a/gdb/features/microblaze64.c b/gdb/features/microblaze64.c
+index 1aa37c4512..5d3e2c8cd9 100644
+--- a/gdb/features/microblaze64.c
++++ b/gdb/features/microblaze64.c
+@@ -70,8 +70,8 @@ initialize_tdesc_microblaze64 (void)
+ tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+- tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
+- tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64");
+
+ tdesc_microblaze64 = result;
+ }
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 0605283c9e..7a0c2527f4 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -77,7 +77,7 @@ static const char *microblaze_register_names[] =
+ "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6",
+ "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11",
+ "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi",
+- "slr", "shr"
++ "rslr", "rshr"
+ };
+
+ #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names)
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0043-Removing-the-header-gdb_assert.h-from-MB-target-file.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0043-Removing-the-header-gdb_assert.h-from-MB-target-file.patch
new file mode 100644
index 0000000..930e161
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0043-Removing-the-header-gdb_assert.h-from-MB-target-file.patch
@@ -0,0 +1,24 @@
+From 9562530bc48c76d8f824b8f4901ad90dd2969086 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Fri, 17 Jan 2020 15:45:48 +0530
+Subject: [PATCH 43/43] Removing the header "gdb_assert.h" from MB target file
+
+---
+ gdb/microblaze-linux-tdep.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index e3d2a7508d..5ef937219c 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -37,7 +37,6 @@
+ #include "linux-tdep.h"
+ #include "glibc-tdep.h"
+
+-#include "gdb_assert.h"
+
+ #ifndef REGSET_H
+ #define REGSET_H 1
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0044-gdb-microblaze-linux-nat.c-Fix-target-compilation-of.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0044-gdb-microblaze-linux-nat.c-Fix-target-compilation-of.patch
new file mode 100644
index 0000000..29e198c
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0044-gdb-microblaze-linux-nat.c-Fix-target-compilation-of.patch
@@ -0,0 +1,364 @@
+From 4f0e06249d23629e1d56b296e7a040b6968484e9 Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@xilinx.com>
+Date: Mon, 20 Jan 2020 12:48:13 -0800
+Subject: [PATCH 44/45] gdb/microblaze-linux-nat.c: Fix target compilation of
+ gdb
+
+Add the nat to the configure file
+
+Remove gdb_assert.h and gdb_string.h.
+
+Adjust include for opcodes as well.
+
+Update to match latest style of components, similar to ppc-linux-nat.c
+
+Update:
+ get_regcache_arch(regcache) to regcache->arch()
+ regcache_raw_supply(regcache, ...) to regcache->raw_supply(...)
+ regcache_raw_collect(regcache, ...) to regcache->raw_collect(...)
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+---
+ gdb/configure.nat | 4 +
+ gdb/microblaze-linux-nat.c | 149 +++++++++++++------------------------
+ gdb/microblaze-tdep.c | 3 +-
+ 3 files changed, 57 insertions(+), 99 deletions(-)
+
+diff --git a/gdb/configure.nat b/gdb/configure.nat
+index 3118263ac6..b8dc7398a5 100644
+--- a/gdb/configure.nat
++++ b/gdb/configure.nat
+@@ -260,6 +260,10 @@ case ${gdb_host} in
+ # Host: Motorola m68k running GNU/Linux.
+ NATDEPFILES="${NATDEPFILES} m68k-linux-nat.o"
+ ;;
++ microblaze*)
++ # Host: Microblaze, running Linux
++ NATDEPFILES="${NATDEPFILES} microblaze-linux-nat.o"
++ ;;
+ mips)
+ # Host: Linux/MIPS
+ NATDEPFILES="${NATDEPFILES} linux-nat-trad.o \
+diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c
+index e9b8c9c522..e09a86bb3f 100644
+--- a/gdb/microblaze-linux-nat.c
++++ b/gdb/microblaze-linux-nat.c
+@@ -36,11 +36,9 @@
+ #include "dwarf2-frame.h"
+ #include "osabi.h"
+
+-#include "gdb_assert.h"
+-#include "gdb_string.h"
+ #include "target-descriptions.h"
+-#include "opcodes/microblaze-opcm.h"
+-#include "opcodes/microblaze-dis.h"
++#include "../opcodes/microblaze-opcm.h"
++#include "../opcodes/microblaze-dis.h"
+
+ #include "linux-nat.h"
+ #include "target-descriptions.h"
+@@ -61,34 +59,27 @@
+ /* Defines ps_err_e, struct ps_prochandle. */
+ #include "gdb_proc_service.h"
+
+-/* On GNU/Linux, threads are implemented as pseudo-processes, in which
+- case we may be tracing more than one process at a time. In that
+- case, inferior_ptid will contain the main process ID and the
+- individual thread (process) ID. get_thread_id () is used to get
+- the thread id if it's available, and the process id otherwise. */
+-
+-int
+-get_thread_id (ptid_t ptid)
+-{
+- int tid = TIDGET (ptid);
+- if (0 == tid)
+- tid = PIDGET (ptid);
+- return tid;
+-}
+-
+-#define GET_THREAD_ID(PTID) get_thread_id (PTID)
+-
+ /* Non-zero if our kernel may support the PTRACE_GETREGS and
+ PTRACE_SETREGS requests, for reading and writing the
+ general-purpose registers. Zero if we've tried one of
+ them and gotten an error. */
+ int have_ptrace_getsetregs = 1;
+
++struct microblaze_linux_nat_target final : public linux_nat_target
++{
++ /* Add our register access methods. */
++ void fetch_registers (struct regcache *, int) override;
++ void store_registers (struct regcache *, int) override;
++
++ const struct target_desc *read_description () override;
++};
++
++static microblaze_linux_nat_target the_microblaze_linux_nat_target;
++
+ static int
+ microblaze_register_u_addr (struct gdbarch *gdbarch, int regno)
+ {
+ int u_addr = -1;
+- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
+ interface, and not the wordsize of the program's ABI. */
+ int wordsize = sizeof (long);
+@@ -105,18 +96,16 @@ microblaze_register_u_addr (struct gdbarch *gdbarch, int regno)
+ static void
+ fetch_register (struct regcache *regcache, int tid, int regno)
+ {
+- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ struct gdbarch *gdbarch = regcache->arch();
+ /* This isn't really an address. But ptrace thinks of it as one. */
+ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
+ int bytes_transferred;
+- unsigned int offset; /* Offset of registers within the u area. */
+- char buf[MAX_REGISTER_SIZE];
++ char buf[sizeof(long)];
+
+ if (regaddr == -1)
+ {
+ memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */
+- regcache_raw_supply (regcache, regno, buf);
++ regcache->raw_supply (regno, buf);
+ return;
+ }
+
+@@ -149,14 +138,14 @@ fetch_register (struct regcache *regcache, int tid, int regno)
+ {
+ /* Little-endian values are always found at the left end of the
+ bytes transferred. */
+- regcache_raw_supply (regcache, regno, buf);
++ regcache->raw_supply (regno, buf);
+ }
+ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+ {
+ /* Big-endian values are found at the right end of the bytes
+ transferred. */
+ size_t padding = (bytes_transferred - register_size (gdbarch, regno));
+- regcache_raw_supply (regcache, regno, buf + padding);
++ regcache->raw_supply (regno, buf + padding);
+ }
+ else
+ internal_error (__FILE__, __LINE__,
+@@ -175,8 +164,6 @@ fetch_register (struct regcache *regcache, int tid, int regno)
+ static int
+ fetch_all_gp_regs (struct regcache *regcache, int tid)
+ {
+- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ gdb_gregset_t gregset;
+
+ if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
+@@ -204,8 +191,6 @@ fetch_all_gp_regs (struct regcache *regcache, int tid)
+ static void
+ fetch_gp_regs (struct regcache *regcache, int tid)
+ {
+- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ int i;
+
+ if (have_ptrace_getsetregs)
+@@ -219,17 +204,29 @@ fetch_gp_regs (struct regcache *regcache, int tid)
+ fetch_register (regcache, tid, i);
+ }
+
++/* Fetch registers from the child process. Fetch all registers if
++ regno == -1, otherwise fetch all general registers or all floating
++ point registers depending upon the value of regno. */
++void
++microblaze_linux_nat_target::fetch_registers (struct regcache *regcache, int regno)
++{
++ pid_t tid = get_ptrace_pid (regcache->ptid ());
++
++ if (regno == -1)
++ fetch_gp_regs (regcache, tid);
++ else
++ fetch_register (regcache, tid, regno);
++}
+
+ static void
+ store_register (const struct regcache *regcache, int tid, int regno)
+ {
+- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ struct gdbarch *gdbarch = regcache->arch();
+ /* This isn't really an address. But ptrace thinks of it as one. */
+ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
+ int i;
+ size_t bytes_to_transfer;
+- char buf[MAX_REGISTER_SIZE];
++ char buf[sizeof(long)];
+
+ if (regaddr == -1)
+ return;
+@@ -242,13 +239,13 @@ store_register (const struct regcache *regcache, int tid, int regno)
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
+ {
+ /* Little-endian values always sit at the left end of the buffer. */
+- regcache_raw_collect (regcache, regno, buf);
++ regcache->raw_collect (regno, buf);
+ }
+ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+ {
+ /* Big-endian values sit at the right end of the buffer. */
+ size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
+- regcache_raw_collect (regcache, regno, buf + padding);
++ regcache->raw_collect (regno, buf + padding);
+ }
+
+ for (i = 0; i < bytes_to_transfer; i += sizeof (long))
+@@ -281,8 +278,6 @@ store_register (const struct regcache *regcache, int tid, int regno)
+ static int
+ store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
+ {
+- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ gdb_gregset_t gregset;
+
+ if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
+@@ -319,8 +314,6 @@ store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
+ static void
+ store_gp_regs (const struct regcache *regcache, int tid, int regno)
+ {
+- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ int i;
+
+ if (have_ptrace_getsetregs)
+@@ -335,33 +328,10 @@ store_gp_regs (const struct regcache *regcache, int tid, int regno)
+ }
+
+
+-/* Fetch registers from the child process. Fetch all registers if
+- regno == -1, otherwise fetch all general registers or all floating
+- point registers depending upon the value of regno. */
+-
+-static void
+-microblaze_linux_fetch_inferior_registers (struct target_ops *ops,
+- struct regcache *regcache, int regno)
+-{
+- /* Get the thread id for the ptrace call. */
+- int tid = GET_THREAD_ID (inferior_ptid);
+-
+- if (regno == -1)
+- fetch_gp_regs (regcache, tid);
+- else
+- fetch_register (regcache, tid, regno);
+-}
+-
+-/* Store registers back into the inferior. Store all registers if
+- regno == -1, otherwise store all general registers or all floating
+- point registers depending upon the value of regno. */
+-
+-static void
+-microblaze_linux_store_inferior_registers (struct target_ops *ops,
+- struct regcache *regcache, int regno)
++void
++microblaze_linux_nat_target::store_registers (struct regcache *regcache, int regno)
+ {
+- /* Get the thread id for the ptrace call. */
+- int tid = GET_THREAD_ID (inferior_ptid);
++ pid_t tid = get_ptrace_pid (regcache->ptid ());
+
+ if (regno >= 0)
+ store_register (regcache, tid, regno);
+@@ -373,59 +343,44 @@ microblaze_linux_store_inferior_registers (struct target_ops *ops,
+ thread debugging. */
+
+ void
+-fill_gregset (const struct regcache *regcache,
+- gdb_gregset_t *gregsetp, int regno)
++supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
+ {
+- microblaze_collect_gregset (NULL, regcache, regno, gregsetp);
++ microblaze_supply_gregset (NULL, regcache, -1, gregsetp);
+ }
+
+ void
+-supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
++fill_gregset (const struct regcache *regcache,
++ gdb_gregset_t *gregsetp, int regno)
+ {
+- microblaze_supply_gregset (NULL, regcache, -1, gregsetp);
++ microblaze_collect_gregset (NULL, regcache, regno, gregsetp);
+ }
+
+ void
+-fill_fpregset (const struct regcache *regcache,
+- gdb_fpregset_t *fpregsetp, int regno)
++supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
+ {
+ /* FIXME. */
++ return;
+ }
+
+ void
+-supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
++fill_fpregset (const struct regcache *regcache,
++ gdb_fpregset_t *fpregsetp, int regno)
+ {
+ /* FIXME. */
++ return;
+ }
+
+-static const struct target_desc *
+-microblaze_linux_read_description (struct target_ops *ops)
++const struct target_desc *
++microblaze_linux_nat_target::read_description ()
+ {
+- CORE_ADDR microblaze_hwcap = 0;
+-
+- if (target_auxv_search (ops, AT_HWCAP, µblaze_hwcap) != 1)
+- return NULL;
+-
+ return NULL;
+ }
+
+-
+-void _initialize_microblaze_linux_nat (void);
+-
+ void
+ _initialize_microblaze_linux_nat (void)
+ {
+- struct target_ops *t;
+-
+- /* Fill in the generic GNU/Linux methods. */
+- t = linux_target ();
+-
+- /* Add our register access methods. */
+- t->to_fetch_registers = microblaze_linux_fetch_inferior_registers;
+- t->to_store_registers = microblaze_linux_store_inferior_registers;
+-
+- t->to_read_description = microblaze_linux_read_description;
++ linux_target = &the_microblaze_linux_nat_target;
+
+ /* Register the target. */
+- linux_nat_add_target (t);
++ add_inf_child_target (linux_target);
+ }
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 7a0c2527f4..23deb24d26 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -657,7 +657,7 @@ static std::vector<CORE_ADDR>
+ microblaze_software_single_step (struct regcache *regcache)
+ {
+ // struct gdbarch *arch = get_frame_arch(frame);
+- struct gdbarch *arch = get_regcache_arch (regcache);
++ struct gdbarch *arch = regcache->arch();
+ struct address_space *aspace = get_regcache_aspace (regcache);
+ // struct address_space *aspace = get_frame_address_space (frame);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
+@@ -876,7 +876,6 @@ microblaze_regset_from_core_section (struct gdbarch *gdbarch,
+ static void
+ make_regs (struct gdbarch *arch)
+ {
+- struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
+ int mach = gdbarch_bfd_arch_info (arch)->mach;
+
+ if (mach == bfd_mach_microblaze64)
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0045-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0045-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch
new file mode 100644
index 0000000..118c562
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0045-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch
@@ -0,0 +1,86 @@
+From d64ce07a2b9206ce1e53d8958b28de02cc7cca2b Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Wed, 22 Jan 2020 16:31:12 +0530
+Subject: [PATCH 45/45] Fixed bug in generation of IMML instruction for the new
+ MB-64 instructions with single register.
+
+---
+ gas/config/tc-microblaze.c | 50 +++++++++++++++++++++++++++++++++++---
+ 1 file changed, 47 insertions(+), 3 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 95a1e69729..dc79328df6 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -1642,12 +1642,56 @@ md_assemble (char * str)
+ exp.X_add_symbol,
+ exp.X_add_number,
+ (char *) opc);
+- immedl = 0L;
++ immed = 0L;
+ }
+ else
+ {
+ output = frag_more (isize);
+ immed = exp.X_add_number;
++ temp = ((long long)immed) & 0xFFFFFFFFFFFF8000;
++ if (temp != 0 && temp != 0xFFFFFFFFFFFF8000 && temp != 0x8000)
++ {
++ /* Needs an immediate inst. */
++ if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887)
++ {
++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ if (opcode1 == NULL)
++ {
++ as_bad (_("unknown opcode \"%s\""), "imml");
++ return;
++ }
++ inst1 = opcode1->bit_sequence;
++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++ output[0] = INST_BYTE0 (inst1);
++ output[1] = INST_BYTE1 (inst1);
++ output[2] = INST_BYTE2 (inst1);
++ output[3] = INST_BYTE3 (inst1);
++ output = frag_more (isize);
++ }
++ else {
++ opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++ if (opcode1 == NULL || opcode2 == NULL)
++ {
++ as_bad (_("unknown opcode \"%s\""), "imml");
++ return;
++ }
++ inst1 = opcode2->bit_sequence;
++ inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
++ output[0] = INST_BYTE0 (inst1);
++ output[1] = INST_BYTE1 (inst1);
++ output[2] = INST_BYTE2 (inst1);
++ output[3] = INST_BYTE3 (inst1);
++ output = frag_more (isize);
++ inst1 = opcode1->bit_sequence;
++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++ output[0] = INST_BYTE0 (inst1);
++ output[1] = INST_BYTE1 (inst1);
++ output[2] = INST_BYTE2 (inst1);
++ output[3] = INST_BYTE3 (inst1);
++ output = frag_more (isize);
++ }
++ }
+ }
+ inst |= (reg1 << RD_LOW) & RD_MASK;
+ inst |= (immed << IMM_LOW) & IMM16_MASK;
+@@ -2141,8 +2185,8 @@ md_assemble (char * str)
+ streq (name, "breaid") ||
+ streq (name, "brai") || streq (name, "braid")))
+ {
+- temp = immed & 0xFFFFFFFFFFFF8000;
+- if (temp != 0)
++ temp = ((long long)immed) & 0xFFFFFFFFFFFF8000;
++ if (temp != 0 && temp != 0xFFFFFFFFFFFF8000 && temp != 0x8000)
+ {
+ /* Needs an immediate inst. */
+ if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887)
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0046-Patch-MicroBlaze-m64-This-patch-will-remove-imml-0-a.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0046-Patch-MicroBlaze-m64-This-patch-will-remove-imml-0-a.patch
new file mode 100644
index 0000000..7677ab3
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils/0046-Patch-MicroBlaze-m64-This-patch-will-remove-imml-0-a.patch
@@ -0,0 +1,38 @@
+From 9c8f4f1c11d324f0788da3a077b06c6bc9e6f2b8 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 16 Apr 2020 18:08:58 +0530
+Subject: [PATCH] [Patch,MicroBlaze m64] : This patch will remove imml 0 and
+ imml -1 instructions when the offset is less than 16 bit for Type A branch EA
+ instructions.
+
+---
+ gas/config/tc-microblaze.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 088eae73a9..12fd145a03 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -2150,9 +2150,7 @@ md_assemble (char * str)
+ if (exp.X_op != O_constant)
+ {
+ char *opc;
+- if (microblaze_arch_size == 64 && (streq (name, "breai") ||
+- streq (name, "breaid") ||
+- streq (name, "brai") || streq (name, "braid")))
++ if (microblaze_arch_size == 64 && (streq (name, "brai") || streq (name, "braid")))
+ opc = str_microblaze_64;
+ else
+ opc = NULL;
+@@ -2920,7 +2918,7 @@ md_apply_fix (fixS * fixP,
+ case BFD_RELOC_MICROBLAZE_64:
+ case BFD_RELOC_MICROBLAZE_64_PCREL:
+ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64
+- || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
++ || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL || (fixP->fx_r_type == BFD_RELOC_64_PCREL && microblaze_arch_size == 64))
+ {
+ /* Generate the imm instruction. */
+ if (((long long)val) > (long long)-549755813888 && ((long long)val) < (long long)549755813887)
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils_%.bbappend
new file mode 100644
index 0000000..e439cae
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils_%.bbappend
@@ -0,0 +1,4 @@
+MICROBLAZEPATCHES = ""
+MICROBLAZEPATCHES_microblaze = "binutils-microblaze.inc"
+
+require ${MICROBLAZEPATCHES}