From 7fb6d720a285b6135a9247b2adde833ea90e2549 Mon Sep 17 00:00:00 2001
From: Usama Arif <usama.arif@arm.com>
Date: Mon, 27 Sep 2021 19:58:56 +0100
Subject: [PATCH] plat-totalcompute: add support for higher DRAM

The new 6GB DRAM bank starts at 0x8080000000.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

Upstream-Status: Backport [https://github.com/OP-TEE/optee_os/commit/6d8430f943e091282849b188fbc0847c159e5de4]
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
---
 core/arch/arm/plat-totalcompute/conf.mk           | 2 ++
 core/arch/arm/plat-totalcompute/main.c            | 1 +
 core/arch/arm/plat-totalcompute/platform_config.h | 3 +++
 3 files changed, 6 insertions(+)

diff --git a/core/arch/arm/plat-totalcompute/conf.mk b/core/arch/arm/plat-totalcompute/conf.mk
index 558b7889..e894b1e1 100644
--- a/core/arch/arm/plat-totalcompute/conf.mk
+++ b/core/arch/arm/plat-totalcompute/conf.mk
@@ -24,6 +24,8 @@ platform-cflags-debug-info = -gdwarf-2
 platform-aflags-debug-info = -gdwarf-2
 endif
 
+$(call force,CFG_CORE_ARM64_PA_BITS,40)
+
 ifneq (,$(filter ${PLATFORM_FLAVOR},tc0 tc1))
 CFG_TEE_CORE_NB_CORE = 8
 
diff --git a/core/arch/arm/plat-totalcompute/main.c b/core/arch/arm/plat-totalcompute/main.c
index 42acf8dd..eab237bf 100644
--- a/core/arch/arm/plat-totalcompute/main.c
+++ b/core/arch/arm/plat-totalcompute/main.c
@@ -27,6 +27,7 @@ register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
 #endif
 
 register_ddr(DRAM0_BASE, DRAM0_SIZE);
+register_ddr(DRAM1_BASE, DRAM1_SIZE);
 
 #ifndef CFG_CORE_SEL2_SPMC
 void main_init_gic(void)
diff --git a/core/arch/arm/plat-totalcompute/platform_config.h b/core/arch/arm/plat-totalcompute/platform_config.h
index 4255abca..b474a899 100644
--- a/core/arch/arm/plat-totalcompute/platform_config.h
+++ b/core/arch/arm/plat-totalcompute/platform_config.h
@@ -26,6 +26,9 @@
 #define DRAM0_BASE		0x80000000
 #define DRAM0_SIZE		0x7d000000
 
+#define DRAM1_BASE		0x8080000000ULL
+#define DRAM1_SIZE		0x180000000ULL
+
 #define TZCDRAM_BASE		0xff000000
 #define TZCDRAM_SIZE		0x01000000
 
-- 
2.30.2