tree bb3a167681f1489bf8a0d1e42f796277bd3612a3
parent 8fc2a182e149dd8906f973853fb83e18c84c26ee
author Benjamin Fair <benjaminfair@google.com> 1608598302 -0800
committer Andrew Geissler <geissonator@yahoo.com> 1609432853 -0600

meta-nuvoton: npcm7xx-bootblock: upgrade to 10.10.16

Changelog from 10.10.09:
 * MC: Enhanced training optimization.
 * SPI0 frequency is now only limited to be up to 50MHz (remove 40MHz
lower limit). This check is only performed if PLLs are changes (RUN_BMC
or new header frequency values).
 * Fix an issue in INTCR3 settings (FIU_FIX field).
 * MC: in enhanced training: change the sweep range accrording to the
location of the step. (run time optimization)

(From meta-nuvoton rev: e7db9495062eab77a319e6eb322cdfe0f68719d8)

Change-Id: I65a512a0110b183c5d9307aea1380cc914236d7d
Signed-off-by: Benjamin Fair <benjaminfair@google.com>
Signed-off-by: Andrew Geissler <geissonator@yahoo.com>