reset meta-xilinx subtree on master HEAD(874b9cee5e)
Change-Id: Ic0716e95ff53e7d63c54dc5fce6ee42fc99ed424
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb-cross-canadian_%.bbappend b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb-cross-canadian_%.bbappend
new file mode 100644
index 0000000..ceb7b02
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb-cross-canadian_%.bbappend
@@ -0,0 +1,4 @@
+MICROBLAZEPATCHES = ""
+MICROBLAZEPATCHES_microblaze = "gdb-microblaze.inc"
+
+require ${MICROBLAZEPATCHES}
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb-cross_%.bbappend b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb-cross_%.bbappend
new file mode 100644
index 0000000..ceb7b02
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb-cross_%.bbappend
@@ -0,0 +1,4 @@
+MICROBLAZEPATCHES = ""
+MICROBLAZEPATCHES_microblaze = "gdb-microblaze.inc"
+
+require ${MICROBLAZEPATCHES}
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc
new file mode 100644
index 0000000..906ef4d
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc
@@ -0,0 +1,39 @@
+# MicroBlaze does not support LTTng UST
+LTTNGUST_microblaze = ""
+
+# Add MicroBlaze patches
+FILESEXTRAPATHS_append := ":${THISDIR}/gdb"
+
+SRC_URI_append_microblaze = " \
+ file://0001-sim-Allow-microblaze-architecture.patch \
+ file://0002-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch \
+ file://0004-Disable-the-warning-message-for-eh_frame_hdr.patch \
+ file://0005-Fix-relaxation-of-assembler-resolved-references.patch \
+ file://0006-microblaze-Fixup-debug_loc-sections-after-linker-rel.patch \
+ file://0007-upstream-change-to-garbage-collection-sweep-causes-m.patch \
+ file://0008-Fix-bug-in-TLSTPREL-Relocation.patch \
+ file://0009-Added-Address-extension-instructions.patch \
+ file://0010-Add-new-bit-field-instructions.patch \
+ file://0011-fixing-the-imm-bug.patch \
+ file://0015-intial-commit-of-MB-64-bit.patch \
+ file://0016-MB-X-initial-commit.patch \
+ file://0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch \
+ file://0018-Added-relocations-for-MB-X.patch \
+ file://0019-Update-MB-x.patch \
+ file://0020-Various-fixes.patch \
+ file://0021-Adding-new-relocation-to-support-64bit-rodata.patch \
+ file://0022-fixing-the-.bss-relocation-issue.patch \
+ file://0023-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch \
+ file://0025-Patch-Microblaze-Binutils-security-check-is-causing-.patch \
+ file://0026-fixing-the-long-long-long-mingw-toolchain-issue.patch \
+ file://0027-Added-support-to-new-arithmetic-single-register-inst.patch \
+ file://0028-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch \
+ file://0033-Fix-various-compile-warnings.patch \
+ file://0034-Add-initial-port-of-linux-gdbserver.patch \
+ file://0035-Initial-port-of-core-reading-support.patch \
+ file://0036-Fix-debug-message-when-register-is-unavailable.patch \
+ file://0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch \
+ file://0038-Initial-support-for-native-gdb.patch \
+ file://0039-Fixing-the-issues-related-to-GDB-7.12.patch \
+ file://0040-Patch-microblaze-Adding-64-bit-MB-support.patch \
+ "
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0001-sim-Allow-microblaze-architecture.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0001-sim-Allow-microblaze-architecture.patch
new file mode 100644
index 0000000..6f05472
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0001-sim-Allow-microblaze-architecture.patch
@@ -0,0 +1,40 @@
+From d23be47051b4410e2e74c6db6bf9a1a9f7195f6d Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@kernel.crashing.org>
+Date: Thu, 6 Aug 2020 15:37:52 -0500
+Subject: [PATCH 01/40] sim: Allow microblaze* architecture
+
+Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
+---
+ sim/configure | 2 +-
+ sim/configure.tgt | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/sim/configure b/sim/configure
+index 72f95cd5c7a..9e28cc78687 100755
+--- a/sim/configure
++++ b/sim/configure
+@@ -3795,7 +3795,7 @@ subdirs="$subdirs aarch64"
+
+
+ ;;
+- microblaze-*-*)
++ microblaze*-*-*)
+
+ sim_arch=microblaze
+ subdirs="$subdirs microblaze"
+diff --git a/sim/configure.tgt b/sim/configure.tgt
+index 8a8e03d96f4..f6743fe8d41 100644
+--- a/sim/configure.tgt
++++ b/sim/configure.tgt
+@@ -59,7 +59,7 @@ case "${target}" in
+ mcore-*-*)
+ SIM_ARCH(mcore)
+ ;;
+- microblaze-*-*)
++ microblaze*-*-*)
+ SIM_ARCH(microblaze)
+ ;;
+ mips*-*-*)
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0002-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0002-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
new file mode 100644
index 0000000..6967a3d
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0002-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
@@ -0,0 +1,65 @@
+From d7a3a238edac153f391a65ae45215a117d25bc48 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Wed, 8 May 2013 11:03:36 +1000
+Subject: [PATCH 02/40] Add wdc.ext.clear and wdc.ext.flush insns
+
+Added two new instructions, wdc.ext.clear and wdc.ext.flush,
+to enable MicroBlaze to flush an external cache, which is
+used with the new coherency support for multiprocessing.
+
+Signed-off-by:nagaraju <nmekala@xilix.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ opcodes/microblaze-opc.h | 5 ++++-
+ opcodes/microblaze-opcm.h | 4 ++--
+ 2 files changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 62ee3c9a4d1..865151f95b0 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -91,6 +91,7 @@
+ #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
+ #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
+ #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
++#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
+
+ /* New Mask for msrset, msrclr insns. */
+@@ -101,7 +102,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+
+-#define MAX_OPCODES 289
++#define MAX_OPCODES 291
+
+ struct op_code_struct
+ {
+@@ -174,7 +175,9 @@ struct op_code_struct
+ {"wic", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
+ {"wdc", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
+ {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
++ {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
+ {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
++ {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
+ {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
+ {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
+ {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 5a2d3b0c8bb..42f3dd3be53 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -33,8 +33,8 @@ enum microblaze_instr
+ /* 'or/and/xor' are C++ keywords. */
+ microblaze_or, microblaze_and, microblaze_xor,
+ andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+- wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
+- brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
++ wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
++ brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+ bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+ imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+ brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0004-Disable-the-warning-message-for-eh_frame_hdr.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0004-Disable-the-warning-message-for-eh_frame_hdr.patch
new file mode 100644
index 0000000..78e1026
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0004-Disable-the-warning-message-for-eh_frame_hdr.patch
@@ -0,0 +1,31 @@
+From 2e87167d8c5d40d8dfbd8d879d78ab0bd6f3bdfd Mon Sep 17 00:00:00 2001
+From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
+Date: Fri, 22 Jun 2012 01:20:20 +0200
+Subject: [PATCH 04/40] Disable the warning message for eh_frame_hdr
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+---
+ bfd/elf-eh-frame.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c
+index b622ffcee2a..26b180f1490 100644
+--- a/bfd/elf-eh-frame.c
++++ b/bfd/elf-eh-frame.c
+@@ -1044,10 +1044,13 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info,
+ goto success;
+
+ free_no_table:
++/* FIXME: Remove the microblaze specifics when relaxing gets fixed. */
++if (bfd_get_arch(abfd) != bfd_arch_microblaze) {
+ _bfd_error_handler
+ /* xgettext:c-format */
+ (_("error in %pB(%pA); no .eh_frame_hdr table will be created"),
+ abfd, sec);
++}
+ hdr_info->u.dwarf.table = FALSE;
+ if (sec_info)
+ free (sec_info);
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0005-Fix-relaxation-of-assembler-resolved-references.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0005-Fix-relaxation-of-assembler-resolved-references.patch
new file mode 100644
index 0000000..d851c58
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0005-Fix-relaxation-of-assembler-resolved-references.patch
@@ -0,0 +1,64 @@
+From 210bb23010e2c3e65f5f54c220d27da0590bab06 Mon Sep 17 00:00:00 2001
+From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
+Date: Tue, 14 Feb 2012 01:00:22 +0100
+Subject: [PATCH 05/40] Fix relaxation of assembler resolved references
+
+---
+ bfd/elf32-microblaze.c | 41 ++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 42 insertions(+)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index c187d83ee04..dfd82438e35 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -1973,6 +1973,47 @@ microblaze_elf_relax_section (bfd *abfd,
+ irelscanend = irelocs + o->reloc_count;
+ for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+ {
++ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
++ {
++ unsigned int val;
++
++ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
++
++ /* This was a PC-relative instruction that was completely resolved. */
++ if (ocontents == NULL)
++ {
++ if (elf_section_data (o)->this_hdr.contents != NULL)
++ ocontents = elf_section_data (o)->this_hdr.contents;
++ else
++ {
++ /* We always cache the section contents.
++ Perhaps, if info->keep_memory is FALSE, we
++ should free them, if we are permitted to. */
++
++ if (o->rawsize == 0)
++ o->rawsize = o->size;
++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++ if (ocontents == NULL)
++ goto error_return;
++ if (!bfd_get_section_contents (abfd, o, ocontents,
++ (file_ptr) 0,
++ o->rawsize))
++ goto error_return;
++ elf_section_data (o)->this_hdr.contents = ocontents;
++ }
++ }
++ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++ if (val != irelscan->r_addend) {
++ fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
++ }
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend
++ + isym->st_value, 0, sec);
++ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
++ irelscan->r_addend);
++ }
++ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
++ fprintf(stderr, "Unhandled NONE 64\n");
++ }
+ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+ {
+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0006-microblaze-Fixup-debug_loc-sections-after-linker-rel.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0006-microblaze-Fixup-debug_loc-sections-after-linker-rel.patch
new file mode 100644
index 0000000..eea2905
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0006-microblaze-Fixup-debug_loc-sections-after-linker-rel.patch
@@ -0,0 +1,184 @@
+From d2aee40b9753b783853bf38d36d9b6e50d16cc20 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Mon, 6 Feb 2017 15:53:08 +0530
+Subject: [PATCH 06/40] microblaze: Fixup debug_loc sections after linker
+ relaxation
+
+Adds a new reloctype R_MICROBLAZE_32_NONE, used for passing
+reloc info from the assembler to the linker when the linker
+manages to fully resolve a local symbol reference.
+
+This is a workaround for design flaws in the assembler to
+linker interface with regards to linker relaxation.
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com>
+---
+ bfd/bfd-in2.h | 5 +++++
+ bfd/elf32-microblaze.c | 39 +++++++++++++++++++++++++++++++-------
+ bfd/libbfd.h | 1 +
+ bfd/reloc.c | 6 ++++++
+ include/elf/microblaze.h | 1 +
+ 7 files changed, 52 insertions(+), 7 deletions(-)
+
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 6f3e41da376..52c81b10b6d 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -5363,6 +5363,11 @@ value relative to the read-write small data area anchor */
+ expressions of the form "Symbol Op Symbol" */
+ BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
+
++/* This is a 32 bit reloc that stores the 32 bit pc relative
++value in two words (with an imm instruction). No relocation is
++done here - only used for relaxing */
++ BFD_RELOC_MICROBLAZE_32_NONE,
++
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction). No relocation is
+ done here - only used for relaxing */
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index dfd82438e35..cbba704e691 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -176,6 +176,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+ 0x0000ffff, /* Dest Mask. */
+ FALSE), /* PC relative offset? */
+
++ HOWTO (R_MICROBLAZE_32_NONE, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 32, /* Bitsize. */
++ TRUE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_bitfield, /* Complain on overflow. */
++ NULL, /* Special Function. */
++ "R_MICROBLAZE_32_NONE",/* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
+ /* This reloc does nothing. Used for relaxation. */
+ HOWTO (R_MICROBLAZE_64_NONE, /* Type. */
+ 0, /* Rightshift. */
+@@ -562,6 +576,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+ case BFD_RELOC_NONE:
+ microblaze_reloc = R_MICROBLAZE_NONE;
+ break;
++ case BFD_RELOC_MICROBLAZE_32_NONE:
++ microblaze_reloc = R_MICROBLAZE_32_NONE;
++ break;
+ case BFD_RELOC_MICROBLAZE_64_NONE:
+ microblaze_reloc = R_MICROBLAZE_64_NONE;
+ break;
+@@ -1918,14 +1935,22 @@ microblaze_elf_relax_section (bfd *abfd,
+ }
+ break;
+ case R_MICROBLAZE_NONE:
++ case R_MICROBLAZE_32_NONE:
+ {
+ /* This was a PC-relative instruction that was
+ completely resolved. */
+ int sfix, efix;
++ unsigned int val;
+ bfd_vma target_address;
+ target_address = irel->r_addend + irel->r_offset;
+ sfix = calc_fixup (irel->r_offset, 0, sec);
+ efix = calc_fixup (target_address, 0, sec);
++
++ /* Validate the in-band val. */
++ val = bfd_get_32 (abfd, contents + irel->r_offset);
++ if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++ }
+ irel->r_addend -= (efix - sfix);
+ /* Should use HOWTO. */
+ microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
+@@ -1973,12 +1998,16 @@ microblaze_elf_relax_section (bfd *abfd,
+ irelscanend = irelocs + o->reloc_count;
+ for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+ {
+- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
++ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
+ {
+ unsigned int val;
+
+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+
++ /* hax: We only do the following fixup for debug location lists. */
++ if (strcmp(".debug_loc", o->name))
++ continue;
++
+ /* This was a PC-relative instruction that was completely resolved. */
+ if (ocontents == NULL)
+ {
+@@ -2006,14 +2035,10 @@ microblaze_elf_relax_section (bfd *abfd,
+ if (val != irelscan->r_addend) {
+ fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
+ }
+- irelscan->r_addend -= calc_fixup (irelscan->r_addend
+- + isym->st_value, 0, sec);
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
+ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
+ irelscan->r_addend);
+ }
+- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
+- fprintf(stderr, "Unhandled NONE 64\n");
+- }
+ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+ {
+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+@@ -2073,7 +2098,7 @@ microblaze_elf_relax_section (bfd *abfd,
+ elf_section_data (o)->this_hdr.contents = ocontents;
+ }
+ }
+- irelscan->r_addend -= calc_fixup (irel->r_addend
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend
+ + isym->st_value,
+ 0,
+ sec);
+diff --git a/bfd/libbfd.h b/bfd/libbfd.h
+index 44cefbd66d4..a01891f3423 100644
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -2903,6 +2903,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+ "BFD_RELOC_MICROBLAZE_32_ROSDA",
+ "BFD_RELOC_MICROBLAZE_32_RWSDA",
+ "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
++ "BFD_RELOC_MICROBLAZE_32_NONE",
+ "BFD_RELOC_MICROBLAZE_64_NONE",
+ "BFD_RELOC_MICROBLAZE_64_GOTPC",
+ "BFD_RELOC_MICROBLAZE_64_GOT",
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index b00b79f3190..78f13180c71 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6806,6 +6806,12 @@ ENUM
+ ENUMDOC
+ This is a 32 bit reloc for the microblaze to handle
+ expressions of the form "Symbol Op Symbol"
++ENUM
++ BFD_RELOC_MICROBLAZE_32_NONE
++ENUMDOC
++ This is a 32 bit reloc that stores the 32 bit pc relative
++ value in two words (with an imm instruction). No relocation is
++ done here - only used for relaxing
+ ENUM
+ BFD_RELOC_MICROBLAZE_64_NONE
+ ENUMDOC
+diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
+index 830b5ad4461..0dba2c0f44f 100644
+--- a/include/elf/microblaze.h
++++ b/include/elf/microblaze.h
+@@ -61,6 +61,7 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
+ RELOC_NUMBER (R_MICROBLAZE_TEXTPCREL_64, 30) /* PC-relative TEXT offset. */
+ RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31) /* TEXT Entry offset 64-bit. */
+ RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit. */
++ RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33)
+ END_RELOC_NUMBERS (R_MICROBLAZE_max)
+
+ /* Global base address names. */
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0007-upstream-change-to-garbage-collection-sweep-causes-m.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0007-upstream-change-to-garbage-collection-sweep-causes-m.patch
new file mode 100644
index 0000000..09a17ed
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0007-upstream-change-to-garbage-collection-sweep-causes-m.patch
@@ -0,0 +1,39 @@
+From df187bca3d19a3e5c36182929e7e14bc6a49aad5 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Wed, 27 Feb 2013 13:56:11 +1000
+Subject: [PATCH 07/40] upstream change to garbage collection sweep causes mb
+ regression
+
+Upstream change for PR13177 now clears the def_regular during gc_sweep of a
+section. (All other archs in binutils/bfd/elf32-*.c received an update
+to a warning about unresolvable relocations - this warning is not present
+in binutils/bfd/elf32-microblaze.c, but this warning check would not
+prevent the error being seen)
+
+The visible issue with this change is when running a c++ application
+in Petalinux which links libstdc++.so for exception handling it segfaults
+on execution.
+
+This does not occur if static linking libstdc++.a, so its during the
+relocations for a shared lib with garbage collection this occurs
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ bfd/elflink.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/bfd/elflink.c b/bfd/elflink.c
+index 7078a2fb6f4..7926fdf63be 100644
+--- a/bfd/elflink.c
++++ b/bfd/elflink.c
+@@ -6274,7 +6274,6 @@ elf_gc_sweep_symbol (struct elf_link_hash_entry *h, void *data)
+
+ inf = (struct elf_gc_sweep_symbol_info *) data;
+ (*inf->hide_symbol) (inf->info, h, TRUE);
+- h->def_regular = 0;
+ h->ref_regular = 0;
+ h->ref_regular_nonweak = 0;
+ }
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0008-Fix-bug-in-TLSTPREL-Relocation.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0008-Fix-bug-in-TLSTPREL-Relocation.patch
new file mode 100644
index 0000000..c37a5ae
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0008-Fix-bug-in-TLSTPREL-Relocation.patch
@@ -0,0 +1,33 @@
+From 0f1d7bd04916af6172780335dc6abc11d45564f2 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Mon, 15 Jun 2015 16:50:30 +0530
+Subject: [PATCH 08/40] Fix bug in TLSTPREL Relocation
+
+Fixed the problem related to the fixup/relocations TLSTPREL.
+When the fixup is applied the addend is not added at the correct offset
+of the instruction. The offset is hard coded considering its big endian
+and it fails for Little endian. This patch allows support for both
+big & little-endian compilers
+---
+ bfd/elf32-microblaze.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index cbba704e691..cc4c0568c68 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -1451,9 +1451,9 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ relocation += addend;
+ relocation -= dtprel_base(info);
+ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
+- contents + offset + 2);
++ contents + offset + endian);
+ bfd_put_16 (input_bfd, relocation & 0xffff,
+- contents + offset + 2 + INST_WORD_SIZE);
++ contents + offset + endian + INST_WORD_SIZE);
+ break;
+ case (int) R_MICROBLAZE_TEXTREL_64:
+ case (int) R_MICROBLAZE_TEXTREL_32_LO:
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0009-Added-Address-extension-instructions.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0009-Added-Address-extension-instructions.patch
new file mode 100644
index 0000000..c9903a4
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0009-Added-Address-extension-instructions.patch
@@ -0,0 +1,124 @@
+From c0bb923f0978d5767048274cd778c8cbcef184ec Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Mon, 18 Jan 2016 12:28:21 +0530
+Subject: [PATCH 09/40] Added Address extension instructions
+
+This patch adds the support of new instructions which are required
+for supporting Address extension feature.
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+
+ChangeLog:
+ 2016-01-18 Nagaraju Mekala <nmekala@xilix.com>
+
+ *microblaze-opc.h (op_code_struct): Update
+ Added new instructions
+ Set MAX_OPCODES to matching value
+ *microblaze-opcm.h (microblaze_instr): Update
+ Added new instructions
+---
+ opcodes/microblaze-opc.h | 19 +++++++++++++++----
+ opcodes/microblaze-opcm.h | 12 ++++++------
+ 2 files changed, 21 insertions(+), 10 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 865151f95b0..d9a84e575e8 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -102,7 +102,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+
+-#define MAX_OPCODES 291
++#define MAX_OPCODES 299
+
+ struct op_code_struct
+ {
+@@ -178,8 +178,11 @@ struct op_code_struct
+ {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
+ {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
+ {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
++ {"wdc.clear.ea", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E6, OPCODE_MASK_H34B, wdcclearea, special_inst },
+ {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
++ {"mtse", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9500C000, OPCODE_MASK_H13S, mtse,special_inst },
+ {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
++ {"mfse", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94088000, OPCODE_MASK_H23S, mfse, special_inst },
+ {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
+ {"brd", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
+ {"brld", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
+@@ -229,18 +232,24 @@ struct op_code_struct
+ {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
+ {"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
+ {"lbur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst },
++ {"lbuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000080, OPCODE_MASK_H4, lbuea, memory_load_inst },
+ {"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
+ {"lhur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst },
++ {"lhuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000080, OPCODE_MASK_H4, lhuea, memory_load_inst },
+ {"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
+ {"lwr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst },
+ {"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
++ {"lwea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000080, OPCODE_MASK_H4, lwea, memory_load_inst },
+ {"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
+ {"sbr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst },
++ {"sbea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000080, OPCODE_MASK_H4, sbea, memory_store_inst },
+ {"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
+ {"shr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst },
++ {"shea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000080, OPCODE_MASK_H4, shea, memory_store_inst },
+ {"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
+ {"swr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst },
+ {"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
++ {"swea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000080, OPCODE_MASK_H4, swea, memory_store_inst },
+ {"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
+ {"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
+ {"lwi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
+@@ -258,10 +267,10 @@ struct op_code_struct
+ {"smi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst },
+ {"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst },
+ {"msrclr",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94110000, OPCODE_MASK_H23N, msrclr, special_inst },
+- {"fadd", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000000, OPCODE_MASK_H4, fadd, arithmetic_inst },
++ {"fadd", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000000, OPCODE_MASK_H4, mbi_fadd, arithmetic_inst },
+ {"frsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000080, OPCODE_MASK_H4, frsub, arithmetic_inst },
+- {"fmul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000100, OPCODE_MASK_H4, fmul, arithmetic_inst },
+- {"fdiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000180, OPCODE_MASK_H4, fdiv, arithmetic_inst },
++ {"fmul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000100, OPCODE_MASK_H4, mbi_fmul, arithmetic_inst },
++ {"fdiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000180, OPCODE_MASK_H4, mbi_fdiv, arithmetic_inst },
+ {"fcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000210, OPCODE_MASK_H4, fcmp_lt, arithmetic_inst },
+ {"fcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000220, OPCODE_MASK_H4, fcmp_eq, arithmetic_inst },
+ {"fcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000230, OPCODE_MASK_H4, fcmp_le, arithmetic_inst },
+@@ -405,6 +414,8 @@ struct op_code_struct
+ {"clz", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34, clz, special_inst },
+ {"mbar", INST_TYPE_IMM5, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN, mbar, special_inst },
+ {"sleep", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 16. */
++ {"hibernate", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB9020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 8. */
++ {"suspend", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 24. */
+ {"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst },
+ {"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst },
+ {"", 0, 0, 0, 0, 0, 0, 0, 0},
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 42f3dd3be53..8be6e97a1d5 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -33,14 +33,14 @@ enum microblaze_instr
+ /* 'or/and/xor' are C++ keywords. */
+ microblaze_or, microblaze_and, microblaze_xor,
+ andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+- wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
+- brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+- bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
++ wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, wdcclearea, mts, mtse,
++ mfs, mfse, mbar, br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd,
++ bne, bned, blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+ imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+ brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+- bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
+- shr, sw, swr, swx, lbui, lhui, lwi,
+- sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
++ bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
++ sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi,
++ sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
+ fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
+ fint, fsqrt,
+ tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0010-Add-new-bit-field-instructions.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0010-Add-new-bit-field-instructions.patch
new file mode 100644
index 0000000..f94410d
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0010-Add-new-bit-field-instructions.patch
@@ -0,0 +1,140 @@
+From 32058fa03c18d710b3029108e967be687d00516c Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Mon, 18 Jul 2016 12:24:28 +0530
+Subject: [PATCH 10/40] Add new bit-field instructions
+
+This patches adds new bsefi and bsifi instructions.
+BSEFI- The instruction shall extract a bit field from a
+register and place it right-adjusted in the destination register.
+The other bits in the destination register shall be set to zero
+BSIFI- The instruction shall insert a right-adjusted bit field
+from a register at another position in the destination register.
+The rest of the bits in the destination register shall be unchanged
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+---
+ opcodes/microblaze-dis.c | 17 +++++++++
+ opcodes/microblaze-opc.h | 12 ++++++-
+ opcodes/microblaze-opcm.h | 6 +++-
+ 4 files changed, 103 insertions(+), 3 deletions(-)
+
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index 2b3aa8e0786..356f1da22ed 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -90,6 +90,18 @@ get_field_imm5_mbar (struct string_buf *buf, long instr)
+ return p;
+ }
+
++static char *
++get_field_imm5width (struct string_buf *buf, long instr)
++{
++ char *p = strbuf (buf);
++
++ if (instr & 0x00004000)
++ sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
++ else
++ sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
++ return p;
++}
++
+ static char *
+ get_field_rfsl (struct string_buf *buf, long instr)
+ {
+@@ -426,6 +438,11 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+ case INST_TYPE_NONE:
+ break;
+ /* For tuqula instruction */
++ /* For bit field insns. */
++ case INST_TYPE_RD_R1_IMM5_IMM5:
++ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst), get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst));
++ break;
++ /* For tuqula instruction */
+ case INST_TYPE_RD:
+ print_func (stream, "\t%s", get_field_rd (&buf, inst));
+ break;
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index d9a84e575e8..d3b234e1fcd 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -59,6 +59,9 @@
+ /* For mbar. */
+ #define INST_TYPE_IMM5 20
+
++/* For bsefi and bsifi */
++#define INST_TYPE_RD_R1_IMM5_IMM5 21
++
+ #define INST_TYPE_NONE 25
+
+
+@@ -89,7 +92,9 @@
+ #define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */
+ #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */
+ #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
++#define OPCODE_MASK_H3B 0xFC00C600 /* High 6 bits and bits 16, 17, 21, 22. */
+ #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
++#define OPCODE_MASK_H32B 0xFC00C000 /* High 6 bits and bit 16, 17. */
+ #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
+ #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
+@@ -102,7 +107,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+
+-#define MAX_OPCODES 299
++#define MAX_OPCODES 301
+
+ struct op_code_struct
+ {
+@@ -159,6 +164,8 @@ struct op_code_struct
+ {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
+ {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
+ {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
++ {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
++ {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
+ {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
+ {"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
+ {"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
+@@ -438,5 +445,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM5 ((int) 0x00000000)
+ #define MAX_IMM5 ((int) 0x0000001f)
+
++#define MIN_IMM_WIDTH ((int) 0x00000001)
++#define MAX_IMM_WIDTH ((int) 0x00000020)
++
+ #endif /* MICROBLAZE_OPC */
+
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 8be6e97a1d5..c3b2b8f0f6e 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -29,7 +29,7 @@ enum microblaze_instr
+ addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
+ mulh, mulhu, mulhsu,swapb,swaph,
+ idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
+- ncget, ncput, muli, bslli, bsrai, bsrli, mului,
++ ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului,
+ /* 'or/and/xor' are C++ keywords. */
+ microblaze_or, microblaze_and, microblaze_xor,
+ andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+@@ -129,6 +129,7 @@ enum microblaze_instr_type
+ #define RB_LOW 11 /* Low bit for RB. */
+ #define IMM_LOW 0 /* Low bit for immediate. */
+ #define IMM_MBAR 21 /* low bit for mbar instruction. */
++#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */
+
+ #define RD_MASK 0x03E00000
+ #define RA_MASK 0x001F0000
+@@ -141,6 +142,9 @@ enum microblaze_instr_type
+ /* Imm mask for mbar. */
+ #define IMM5_MBAR_MASK 0x03E00000
+
++/* Imm mask for extract/insert width. */
++#define IMM5_WIDTH_MASK 0x000007C0
++
+ /* FSL imm mask for get, put instructions. */
+ #define RFSL_MASK 0x000000F
+
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0011-fixing-the-imm-bug.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0011-fixing-the-imm-bug.patch
new file mode 100644
index 0000000..3f3c814
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0011-fixing-the-imm-bug.patch
@@ -0,0 +1,27 @@
+From 121b64d9dafd3119925a7e95a09fa9f388e53922 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Mon, 10 Jul 2017 16:07:28 +0530
+Subject: [PATCH 11/40] fixing the imm bug.
+
+with relax option imm -1 is also getting removed this is corrected now.
+---
+ bfd/elf32-microblaze.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index cc4c0568c68..cb7271f5017 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -1869,8 +1869,7 @@ microblaze_elf_relax_section (bfd *abfd,
+ else
+ symval += irel->r_addend;
+
+- if ((symval & 0xffff8000) == 0
+- || (symval & 0xffff8000) == 0xffff8000)
++ if ((symval & 0xffff8000) == 0)
+ {
+ /* We can delete this instruction. */
+ sec->relax[sec->relax_count].addr = irel->r_offset;
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0015-intial-commit-of-MB-64-bit.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0015-intial-commit-of-MB-64-bit.patch
new file mode 100644
index 0000000..bda74ad
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0015-intial-commit-of-MB-64-bit.patch
@@ -0,0 +1,4189 @@
+From 48e5b2505d97ca936e9946c3945c72bdcfc1743e Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Sun, 30 Sep 2018 16:28:28 +0530
+Subject: [PATCH 15/40] intial commit of MB 64-bit
+
+---
+ bfd/Makefile.am | 2 +
+ bfd/Makefile.in | 3 +
+ bfd/config.bfd | 4 +
+ bfd/configure | 2 +
+ bfd/configure.ac | 2 +
+ bfd/cpu-microblaze.c | 55 +-
+ bfd/doc/Makefile.in | 1 +
+ bfd/elf64-microblaze.c | 3560 ++++++++++++++++++++++++++++
+ bfd/targets.c | 6 +
+ include/elf/common.h | 1 +
+ ld/Makefile.am | 4 +
+ ld/Makefile.in | 7 +
+ ld/configure.tgt | 3 +
+ ld/emulparams/elf64microblaze.sh | 23 +
+ ld/emulparams/elf64microblazeel.sh | 23 +
+ opcodes/microblaze-dis.c | 43 +-
+ opcodes/microblaze-opc.h | 162 +-
+ opcodes/microblaze-opcm.h | 20 +-
+ 20 files changed, 4156 insertions(+), 43 deletions(-)
+ create mode 100644 bfd/elf64-microblaze.c
+ create mode 100644 ld/emulparams/elf64microblaze.sh
+ create mode 100644 ld/emulparams/elf64microblazeel.sh
+
+diff --git a/bfd/Makefile.am b/bfd/Makefile.am
+index e5bd28f03f5..35ecb83a1a1 100644
+--- a/bfd/Makefile.am
++++ b/bfd/Makefile.am
+@@ -558,6 +558,7 @@ BFD64_BACKENDS = \
+ elf64-ia64.lo \
+ elf64-ia64-vms.lo \
+ elfxx-ia64.lo \
++ elf64-microblaze.lo \
+ elfn32-mips.lo \
+ elf64-mips.lo \
+ elfxx-mips.lo \
+@@ -597,6 +598,7 @@ BFD64_BACKENDS_CFILES = \
+ elf64-gen.c \
+ elf64-hppa.c \
+ elf64-ia64-vms.c \
++ elf64-microblaze.c \
+ elf64-mips.c \
+ elf64-mmix.c \
+ elf64-nfp.c \
+diff --git a/bfd/Makefile.in b/bfd/Makefile.in
+index 15334f10c55..89a2470ec8f 100644
+--- a/bfd/Makefile.in
++++ b/bfd/Makefile.in
+@@ -984,6 +984,7 @@ BFD64_BACKENDS = \
+ elf64-ia64.lo \
+ elf64-ia64-vms.lo \
+ elfxx-ia64.lo \
++ elf64-microblaze.lo \
+ elfn32-mips.lo \
+ elf64-mips.lo \
+ elfxx-mips.lo \
+@@ -1023,6 +1024,7 @@ BFD64_BACKENDS_CFILES = \
+ elf64-gen.c \
+ elf64-hppa.c \
+ elf64-ia64-vms.c \
++ elf64-microblaze.c \
+ elf64-mips.c \
+ elf64-mmix.c \
+ elf64-nfp.c \
+@@ -1504,6 +1506,7 @@ distclean-compile:
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-hppa.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ia64-vms.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ia64.Plo@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-microblaze.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-mips.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-mmix.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-nfp.Plo@am__quote@
+diff --git a/bfd/config.bfd b/bfd/config.bfd
+index 0a96927e0ed..1fcae568c36 100644
+--- a/bfd/config.bfd
++++ b/bfd/config.bfd
+@@ -842,11 +842,15 @@ case "${targ}" in
+ microblazeel*-*)
+ targ_defvec=microblaze_elf32_le_vec
+ targ_selvecs=microblaze_elf32_vec
++ targ64_selvecs=microblaze_elf64_vec
++ targ64_selvecs=microblaze_elf64_le_vec
+ ;;
+
+ microblaze*-*)
+ targ_defvec=microblaze_elf32_vec
+ targ_selvecs=microblaze_elf32_le_vec
++ targ64_selvecs=microblaze_elf64_vec
++ targ64_selvecs=microblaze_elf64_le_vec
+ ;;
+
+ #ifdef BFD64
+diff --git a/bfd/configure b/bfd/configure
+index abd7b2a83e5..731c059eba0 100755
+--- a/bfd/configure
++++ b/bfd/configure
+@@ -14804,6 +14804,8 @@ do
+ metag_elf32_vec) tb="$tb elf32-metag.lo elf32.lo $elf" ;;
+ microblaze_elf32_vec) tb="$tb elf32-microblaze.lo elf32.lo $elf" ;;
+ microblaze_elf32_le_vec) tb="$tb elf32-microblaze.lo elf32.lo $elf" ;;
++ microblaze_elf64_vec) tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
++ microblaze_elf64_le_vec) tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
+ mips_ecoff_be_vec) tb="$tb coff-mips.lo ecoff.lo $ecoff" ;;
+ mips_ecoff_le_vec) tb="$tb coff-mips.lo ecoff.lo $ecoff" ;;
+ mips_ecoff_bele_vec) tb="$tb coff-mips.lo ecoff.lo $ecoff" ;;
+diff --git a/bfd/configure.ac b/bfd/configure.ac
+index 7eee83ae4d4..b87f6183b98 100644
+--- a/bfd/configure.ac
++++ b/bfd/configure.ac
+@@ -540,6 +540,8 @@ do
+ metag_elf32_vec) tb="$tb elf32-metag.lo elf32.lo $elf" ;;
+ microblaze_elf32_vec) tb="$tb elf32-microblaze.lo elf32.lo $elf" ;;
+ microblaze_elf32_le_vec) tb="$tb elf32-microblaze.lo elf32.lo $elf" ;;
++ microblaze_elf64_vec) tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
++ microblaze_elf64_le_vec) tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
+ mips_ecoff_be_vec) tb="$tb coff-mips.lo ecoff.lo $ecoff" ;;
+ mips_ecoff_le_vec) tb="$tb coff-mips.lo ecoff.lo $ecoff" ;;
+ mips_ecoff_bele_vec) tb="$tb coff-mips.lo ecoff.lo $ecoff" ;;
+diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c
+index 4e05d73f01b..4b48b310c6a 100644
+--- a/bfd/cpu-microblaze.c
++++ b/bfd/cpu-microblaze.c
+@@ -23,7 +23,25 @@
+ #include "bfd.h"
+ #include "libbfd.h"
+
+-const bfd_arch_info_type bfd_microblaze_arch =
++const bfd_arch_info_type bfd_microblaze_arch[] =
++{
++#if BFD_DEFAULT_TARGET_SIZE == 64
++{
++ 64, /* 32 bits in a word. */
++ 64, /* 32 bits in an address. */
++ 8, /* 8 bits in a byte. */
++ bfd_arch_microblaze, /* Architecture. */
++ 0, /* Machine number - 0 for now. */
++ "microblaze", /* Architecture name. */
++ "MicroBlaze", /* Printable name. */
++ 3, /* Section align power. */
++ FALSE, /* Is this the default architecture ? */
++ bfd_default_compatible, /* Architecture comparison function. */
++ bfd_default_scan, /* String to architecture conversion. */
++ bfd_arch_default_fill, /* Default fill. */
++ &bfd_microblaze_arch[1], /* Next in list. */
++ 0 /* Maximum offset of a reloc from the start of an insn. */
++},
+ {
+ 32, /* Bits in a word. */
+ 32, /* Bits in an address. */
+@@ -39,4 +57,39 @@ const bfd_arch_info_type bfd_microblaze_arch =
+ bfd_arch_default_fill, /* Default fill. */
+ NULL, /* Next in list. */
+ 0 /* Maximum offset of a reloc from the start of an insn. */
++}
++#else
++{
++ 32, /* 32 bits in a word. */
++ 32, /* 32 bits in an address. */
++ 8, /* 8 bits in a byte. */
++ bfd_arch_microblaze, /* Architecture. */
++ 0, /* Machine number - 0 for now. */
++ "microblaze", /* Architecture name. */
++ "MicroBlaze", /* Printable name. */
++ 3, /* Section align power. */
++ TRUE, /* Is this the default architecture ? */
++ bfd_default_compatible, /* Architecture comparison function. */
++ bfd_default_scan, /* String to architecture conversion. */
++ bfd_arch_default_fill, /* Default fill. */
++ &bfd_microblaze_arch[1], /* Next in list. */
++ 0 /* Maximum offset of a reloc from the start of an insn. */
++},
++{
++ 64, /* 32 bits in a word. */
++ 64, /* 32 bits in an address. */
++ 8, /* 8 bits in a byte. */
++ bfd_arch_microblaze, /* Architecture. */
++ 0, /* Machine number - 0 for now. */
++ "microblaze", /* Architecture name. */
++ "MicroBlaze", /* Printable name. */
++ 3, /* Section align power. */
++ FALSE, /* Is this the default architecture ? */
++ bfd_default_compatible, /* Architecture comparison function. */
++ bfd_default_scan, /* String to architecture conversion. */
++ bfd_arch_default_fill, /* Default fill. */
++ NULL, /* Next in list. */
++ 0 /* Maximum offset of a reloc from the start of an insn. */
++}
++#endif
+ };
+diff --git a/bfd/doc/Makefile.in b/bfd/doc/Makefile.in
+index 0115dfc406c..d75411d2af7 100644
+--- a/bfd/doc/Makefile.in
++++ b/bfd/doc/Makefile.in
+@@ -375,6 +375,7 @@ pdfdir = @pdfdir@
+ prefix = @prefix@
+ program_transform_name = @program_transform_name@
+ psdir = @psdir@
++runstatedir = @runstatedir@
+ sbindir = @sbindir@
+ sharedstatedir = @sharedstatedir@
+ srcdir = @srcdir@
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+new file mode 100644
+index 00000000000..fa4b95e47e0
+--- /dev/null
++++ b/bfd/elf64-microblaze.c
+@@ -0,0 +1,3560 @@
++/* Xilinx MicroBlaze-specific support for 32-bit ELF
++
++ Copyright (C) 2009-2016 Free Software Foundation, Inc.
++
++ This file is part of BFD, the Binary File Descriptor library.
++
++ This program is free software; you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 3 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the
++ Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
++ Boston, MA 02110-1301, USA. */
++
++
++int dbg1 = 0;
++
++#include "sysdep.h"
++#include "bfd.h"
++#include "bfdlink.h"
++#include "libbfd.h"
++#include "elf-bfd.h"
++#include "elf/microblaze.h"
++#include <assert.h>
++
++#define USE_RELA /* Only USE_REL is actually significant, but this is
++ here are a reminder... */
++#define INST_WORD_SIZE 4
++
++static int ro_small_data_pointer = 0;
++static int rw_small_data_pointer = 0;
++
++static reloc_howto_type * microblaze_elf_howto_table [(int) R_MICROBLAZE_max];
++
++static reloc_howto_type microblaze_elf_howto_raw[] =
++{
++ /* This reloc does nothing. */
++ HOWTO (R_MICROBLAZE_NONE, /* Type. */
++ 0, /* Rightshift. */
++ 3, /* Size (0 = byte, 1 = short, 2 = long). */
++ 0, /* Bitsize. */
++ FALSE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_dont, /* Complain on overflow. */
++ NULL, /* Special Function. */
++ "R_MICROBLAZE_NONE", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
++ /* A standard 32 bit relocation. */
++ HOWTO (R_MICROBLAZE_32, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 32, /* Bitsize. */
++ FALSE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_bitfield, /* Complain on overflow. */
++ bfd_elf_generic_reloc,/* Special Function. */
++ "R_MICROBLAZE_32", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0xffffffff, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
++ /* A standard PCREL 32 bit relocation. */
++ HOWTO (R_MICROBLAZE_32_PCREL,/* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 32, /* Bitsize. */
++ TRUE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_bitfield, /* Complain on overflow. */
++ bfd_elf_generic_reloc,/* Special Function. */
++ "R_MICROBLAZE_32_PCREL", /* Name. */
++ TRUE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0xffffffff, /* Dest Mask. */
++ TRUE), /* PC relative offset? */
++
++ /* A 64 bit PCREL relocation. Table-entry not really used. */
++ HOWTO (R_MICROBLAZE_64_PCREL,/* Type. */
++ 0, /* Rightshift. */
++ 4, /* Size (0 = byte, 1 = short, 2 = long). */
++ 64, /* Bitsize. */
++ TRUE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_dont, /* Complain on overflow. */
++ bfd_elf_generic_reloc,/* Special Function. */
++ "R_MICROBLAZE_64_PCREL", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0x0000ffff, /* Dest Mask. */
++ TRUE), /* PC relative offset? */
++
++ /* The low half of a PCREL 32 bit relocation. */
++ HOWTO (R_MICROBLAZE_32_PCREL_LO, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 16, /* Bitsize. */
++ TRUE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_signed, /* Complain on overflow. */
++ bfd_elf_generic_reloc, /* Special Function. */
++ "R_MICROBLAZE_32_PCREL_LO", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0x0000ffff, /* Dest Mask. */
++ TRUE), /* PC relative offset? */
++
++ /* A 64 bit relocation. Table entry not really used. */
++ HOWTO (R_MICROBLAZE_64, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 16, /* Bitsize. */
++ FALSE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_dont, /* Complain on overflow. */
++ bfd_elf_generic_reloc,/* Special Function. */
++ "R_MICROBLAZE_64", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0x0000ffff, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
++ /* The low half of a 32 bit relocation. */
++ HOWTO (R_MICROBLAZE_32_LO, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 16, /* Bitsize. */
++ FALSE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_signed, /* Complain on overflow. */
++ bfd_elf_generic_reloc,/* Special Function. */
++ "R_MICROBLAZE_32_LO", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0x0000ffff, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
++ /* Read-only small data section relocation. */
++ HOWTO (R_MICROBLAZE_SRO32, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 16, /* Bitsize. */
++ FALSE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_bitfield, /* Complain on overflow. */
++ bfd_elf_generic_reloc,/* Special Function. */
++ "R_MICROBLAZE_SRO32", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0x0000ffff, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
++ /* Read-write small data area relocation. */
++ HOWTO (R_MICROBLAZE_SRW32, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 16, /* Bitsize. */
++ FALSE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_bitfield, /* Complain on overflow. */
++ bfd_elf_generic_reloc,/* Special Function. */
++ "R_MICROBLAZE_SRW32", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0x0000ffff, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
++ HOWTO (R_MICROBLAZE_32_NONE, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 32, /* Bitsize. */
++ TRUE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_bitfield, /* Complain on overflow. */
++ NULL, /* Special Function. */
++ "R_MICROBLAZE_32_NONE",/* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
++ /* This reloc does nothing. Used for relaxation. */
++ HOWTO (R_MICROBLAZE_64_NONE, /* Type. */
++ 0, /* Rightshift. */
++ 3, /* Size (0 = byte, 1 = short, 2 = long). */
++ 0, /* Bitsize. */
++ TRUE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_dont, /* Complain on overflow. */
++ NULL, /* Special Function. */
++ "R_MICROBLAZE_64_NONE",/* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
++ /* Symbol Op Symbol relocation. */
++ HOWTO (R_MICROBLAZE_32_SYM_OP_SYM, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 32, /* Bitsize. */
++ FALSE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_bitfield, /* Complain on overflow. */
++ bfd_elf_generic_reloc,/* Special Function. */
++ "R_MICROBLAZE_32_SYM_OP_SYM", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0xffffffff, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
++ /* GNU extension to record C++ vtable hierarchy. */
++ HOWTO (R_MICROBLAZE_GNU_VTINHERIT, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 0, /* Bitsize. */
++ FALSE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_dont,/* Complain on overflow. */
++ NULL, /* Special Function. */
++ "R_MICROBLAZE_GNU_VTINHERIT", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
++ /* GNU extension to record C++ vtable member usage. */
++ HOWTO (R_MICROBLAZE_GNU_VTENTRY, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 0, /* Bitsize. */
++ FALSE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_dont,/* Complain on overflow. */
++ _bfd_elf_rel_vtable_reloc_fn, /* Special Function. */
++ "R_MICROBLAZE_GNU_VTENTRY", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
++ /* A 64 bit GOTPC relocation. Table-entry not really used. */
++ HOWTO (R_MICROBLAZE_GOTPC_64, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 16, /* Bitsize. */
++ TRUE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_dont, /* Complain on overflow. */
++ bfd_elf_generic_reloc, /* Special Function. */
++ "R_MICROBLAZE_GOTPC_64", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0x0000ffff, /* Dest Mask. */
++ TRUE), /* PC relative offset? */
++
++ /* A 64 bit GOT relocation. Table-entry not really used. */
++ HOWTO (R_MICROBLAZE_GOT_64, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 16, /* Bitsize. */
++ FALSE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_dont, /* Complain on overflow. */
++ bfd_elf_generic_reloc,/* Special Function. */
++ "R_MICROBLAZE_GOT_64",/* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0x0000ffff, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
++ /* A 64 bit PLT relocation. Table-entry not really used. */
++ HOWTO (R_MICROBLAZE_PLT_64, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 16, /* Bitsize. */
++ TRUE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_dont, /* Complain on overflow. */
++ bfd_elf_generic_reloc,/* Special Function. */
++ "R_MICROBLAZE_PLT_64",/* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0x0000ffff, /* Dest Mask. */
++ TRUE), /* PC relative offset? */
++
++ /* Table-entry not really used. */
++ HOWTO (R_MICROBLAZE_REL, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 16, /* Bitsize. */
++ TRUE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_dont, /* Complain on overflow. */
++ bfd_elf_generic_reloc,/* Special Function. */
++ "R_MICROBLAZE_REL", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0x0000ffff, /* Dest Mask. */
++ TRUE), /* PC relative offset? */
++
++ /* Table-entry not really used. */
++ HOWTO (R_MICROBLAZE_JUMP_SLOT,/* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 16, /* Bitsize. */
++ TRUE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_dont, /* Complain on overflow. */
++ bfd_elf_generic_reloc,/* Special Function. */
++ "R_MICROBLAZE_JUMP_SLOT", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0x0000ffff, /* Dest Mask. */
++ TRUE), /* PC relative offset? */
++
++ /* Table-entry not really used. */
++ HOWTO (R_MICROBLAZE_GLOB_DAT,/* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 16, /* Bitsize. */
++ TRUE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_dont, /* Complain on overflow. */
++ bfd_elf_generic_reloc,/* Special Function. */
++ "R_MICROBLAZE_GLOB_DAT", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0x0000ffff, /* Dest Mask. */
++ TRUE), /* PC relative offset? */
++
++ /* A 64 bit GOT relative relocation. Table-entry not really used. */
++ HOWTO (R_MICROBLAZE_GOTOFF_64, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 16, /* Bitsize. */
++ FALSE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_dont, /* Complain on overflow. */
++ bfd_elf_generic_reloc,/* Special Function. */
++ "R_MICROBLAZE_GOTOFF_64", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0x0000ffff, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
++ /* A 32 bit GOT relative relocation. Table-entry not really used. */
++ HOWTO (R_MICROBLAZE_GOTOFF_32, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 16, /* Bitsize. */
++ FALSE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_dont, /* Complain on overflow. */
++ bfd_elf_generic_reloc, /* Special Function. */
++ "R_MICROBLAZE_GOTOFF_32", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0x0000ffff, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
++ /* COPY relocation. Table-entry not really used. */
++ HOWTO (R_MICROBLAZE_COPY, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 16, /* Bitsize. */
++ FALSE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_dont, /* Complain on overflow. */
++ bfd_elf_generic_reloc,/* Special Function. */
++ "R_MICROBLAZE_COPY", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0x0000ffff, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
++ /* Marker relocs for TLS. */
++ HOWTO (R_MICROBLAZE_TLS,
++ 0, /* rightshift */
++ 2, /* size (0 = byte, 1 = short, 2 = long) */
++ 32, /* bitsize */
++ FALSE, /* pc_relative */
++ 0, /* bitpos */
++ complain_overflow_dont, /* complain_on_overflow */
++ bfd_elf_generic_reloc, /* special_function */
++ "R_MICROBLAZE_TLS", /* name */
++ FALSE, /* partial_inplace */
++ 0, /* src_mask */
++ 0x0000ffff, /* dst_mask */
++ FALSE), /* pcrel_offset */
++
++ HOWTO (R_MICROBLAZE_TLSGD,
++ 0, /* rightshift */
++ 2, /* size (0 = byte, 1 = short, 2 = long) */
++ 32, /* bitsize */
++ FALSE, /* pc_relative */
++ 0, /* bitpos */
++ complain_overflow_dont, /* complain_on_overflow */
++ bfd_elf_generic_reloc, /* special_function */
++ "R_MICROBLAZE_TLSGD", /* name */
++ FALSE, /* partial_inplace */
++ 0, /* src_mask */
++ 0x0000ffff, /* dst_mask */
++ FALSE), /* pcrel_offset */
++
++ HOWTO (R_MICROBLAZE_TLSLD,
++ 0, /* rightshift */
++ 2, /* size (0 = byte, 1 = short, 2 = long) */
++ 32, /* bitsize */
++ FALSE, /* pc_relative */
++ 0, /* bitpos */
++ complain_overflow_dont, /* complain_on_overflow */
++ bfd_elf_generic_reloc, /* special_function */
++ "R_MICROBLAZE_TLSLD", /* name */
++ FALSE, /* partial_inplace */
++ 0, /* src_mask */
++ 0x0000ffff, /* dst_mask */
++ FALSE), /* pcrel_offset */
++
++ /* Computes the load module index of the load module that contains the
++ definition of its TLS sym. */
++ HOWTO (R_MICROBLAZE_TLSDTPMOD32,
++ 0, /* rightshift */
++ 2, /* size (0 = byte, 1 = short, 2 = long) */
++ 32, /* bitsize */
++ FALSE, /* pc_relative */
++ 0, /* bitpos */
++ complain_overflow_dont, /* complain_on_overflow */
++ bfd_elf_generic_reloc, /* special_function */
++ "R_MICROBLAZE_TLSDTPMOD32", /* name */
++ FALSE, /* partial_inplace */
++ 0, /* src_mask */
++ 0x0000ffff, /* dst_mask */
++ FALSE), /* pcrel_offset */
++
++ /* Computes a dtv-relative displacement, the difference between the value
++ of sym+add and the base address of the thread-local storage block that
++ contains the definition of sym, minus 0x8000. Used for initializing GOT */
++ HOWTO (R_MICROBLAZE_TLSDTPREL32,
++ 0, /* rightshift */
++ 2, /* size (0 = byte, 1 = short, 2 = long) */
++ 32, /* bitsize */
++ FALSE, /* pc_relative */
++ 0, /* bitpos */
++ complain_overflow_dont, /* complain_on_overflow */
++ bfd_elf_generic_reloc, /* special_function */
++ "R_MICROBLAZE_TLSDTPREL32", /* name */
++ FALSE, /* partial_inplace */
++ 0, /* src_mask */
++ 0x0000ffff, /* dst_mask */
++ FALSE), /* pcrel_offset */
++
++ /* Computes a dtv-relative displacement, the difference between the value
++ of sym+add and the base address of the thread-local storage block that
++ contains the definition of sym, minus 0x8000. */
++ HOWTO (R_MICROBLAZE_TLSDTPREL64,
++ 0, /* rightshift */
++ 2, /* size (0 = byte, 1 = short, 2 = long) */
++ 32, /* bitsize */
++ FALSE, /* pc_relative */
++ 0, /* bitpos */
++ complain_overflow_dont, /* complain_on_overflow */
++ bfd_elf_generic_reloc, /* special_function */
++ "R_MICROBLAZE_TLSDTPREL64", /* name */
++ FALSE, /* partial_inplace */
++ 0, /* src_mask */
++ 0x0000ffff, /* dst_mask */
++ FALSE), /* pcrel_offset */
++
++ /* Computes a tp-relative displacement, the difference between the value of
++ sym+add and the value of the thread pointer (r13). */
++ HOWTO (R_MICROBLAZE_TLSGOTTPREL32,
++ 0, /* rightshift */
++ 2, /* size (0 = byte, 1 = short, 2 = long) */
++ 32, /* bitsize */
++ FALSE, /* pc_relative */
++ 0, /* bitpos */
++ complain_overflow_dont, /* complain_on_overflow */
++ bfd_elf_generic_reloc, /* special_function */
++ "R_MICROBLAZE_TLSGOTTPREL32", /* name */
++ FALSE, /* partial_inplace */
++ 0, /* src_mask */
++ 0x0000ffff, /* dst_mask */
++ FALSE), /* pcrel_offset */
++
++ /* Computes a tp-relative displacement, the difference between the value of
++ sym+add and the value of the thread pointer (r13). */
++ HOWTO (R_MICROBLAZE_TLSTPREL32,
++ 0, /* rightshift */
++ 2, /* size (0 = byte, 1 = short, 2 = long) */
++ 32, /* bitsize */
++ FALSE, /* pc_relative */
++ 0, /* bitpos */
++ complain_overflow_dont, /* complain_on_overflow */
++ bfd_elf_generic_reloc, /* special_function */
++ "R_MICROBLAZE_TLSTPREL32", /* name */
++ FALSE, /* partial_inplace */
++ 0, /* src_mask */
++ 0x0000ffff, /* dst_mask */
++ FALSE), /* pcrel_offset */
++
++};
++
++#ifndef NUM_ELEM
++#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
++#endif
++
++/* Initialize the microblaze_elf_howto_table, so that linear accesses can be done. */
++
++static void
++microblaze_elf_howto_init (void)
++{
++ unsigned int i;
++
++ for (i = NUM_ELEM (microblaze_elf_howto_raw); i--;)
++ {
++ unsigned int type;
++
++ type = microblaze_elf_howto_raw[i].type;
++
++ BFD_ASSERT (type < NUM_ELEM (microblaze_elf_howto_table));
++
++ microblaze_elf_howto_table [type] = & microblaze_elf_howto_raw [i];
++ }
++}
++
++static reloc_howto_type *
++microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
++ bfd_reloc_code_real_type code)
++{
++ enum elf_microblaze_reloc_type microblaze_reloc = R_MICROBLAZE_NONE;
++
++ switch (code)
++ {
++ case BFD_RELOC_NONE:
++ microblaze_reloc = R_MICROBLAZE_NONE;
++ break;
++ case BFD_RELOC_MICROBLAZE_32_NONE:
++ microblaze_reloc = R_MICROBLAZE_32_NONE;
++ break;
++ case BFD_RELOC_MICROBLAZE_64_NONE:
++ microblaze_reloc = R_MICROBLAZE_64_NONE;
++ break;
++ case BFD_RELOC_32:
++ microblaze_reloc = R_MICROBLAZE_32;
++ break;
++ /* RVA is treated the same as 32 */
++ case BFD_RELOC_RVA:
++ microblaze_reloc = R_MICROBLAZE_32;
++ break;
++ case BFD_RELOC_32_PCREL:
++ microblaze_reloc = R_MICROBLAZE_32_PCREL;
++ break;
++ case BFD_RELOC_64_PCREL:
++ microblaze_reloc = R_MICROBLAZE_64_PCREL;
++ break;
++ case BFD_RELOC_MICROBLAZE_32_LO_PCREL:
++ microblaze_reloc = R_MICROBLAZE_32_PCREL_LO;
++ break;
++ case BFD_RELOC_64:
++ microblaze_reloc = R_MICROBLAZE_64;
++ break;
++ case BFD_RELOC_MICROBLAZE_32_LO:
++ microblaze_reloc = R_MICROBLAZE_32_LO;
++ break;
++ case BFD_RELOC_MICROBLAZE_32_ROSDA:
++ microblaze_reloc = R_MICROBLAZE_SRO32;
++ break;
++ case BFD_RELOC_MICROBLAZE_32_RWSDA:
++ microblaze_reloc = R_MICROBLAZE_SRW32;
++ break;
++ case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM:
++ microblaze_reloc = R_MICROBLAZE_32_SYM_OP_SYM;
++ break;
++ case BFD_RELOC_VTABLE_INHERIT:
++ microblaze_reloc = R_MICROBLAZE_GNU_VTINHERIT;
++ break;
++ case BFD_RELOC_VTABLE_ENTRY:
++ microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
++ break;
++ case BFD_RELOC_MICROBLAZE_64_GOTPC:
++ microblaze_reloc = R_MICROBLAZE_GOTPC_64;
++ break;
++ case BFD_RELOC_MICROBLAZE_64_GOT:
++ microblaze_reloc = R_MICROBLAZE_GOT_64;
++ break;
++ case BFD_RELOC_MICROBLAZE_64_PLT:
++ microblaze_reloc = R_MICROBLAZE_PLT_64;
++ break;
++ case BFD_RELOC_MICROBLAZE_64_GOTOFF:
++ microblaze_reloc = R_MICROBLAZE_GOTOFF_64;
++ break;
++ case BFD_RELOC_MICROBLAZE_32_GOTOFF:
++ microblaze_reloc = R_MICROBLAZE_GOTOFF_32;
++ break;
++ case BFD_RELOC_MICROBLAZE_64_TLSGD:
++ microblaze_reloc = R_MICROBLAZE_TLSGD;
++ break;
++ case BFD_RELOC_MICROBLAZE_64_TLSLD:
++ microblaze_reloc = R_MICROBLAZE_TLSLD;
++ break;
++ case BFD_RELOC_MICROBLAZE_32_TLSDTPREL:
++ microblaze_reloc = R_MICROBLAZE_TLSDTPREL32;
++ break;
++ case BFD_RELOC_MICROBLAZE_64_TLSDTPREL:
++ microblaze_reloc = R_MICROBLAZE_TLSDTPREL64;
++ break;
++ case BFD_RELOC_MICROBLAZE_32_TLSDTPMOD:
++ microblaze_reloc = R_MICROBLAZE_TLSDTPMOD32;
++ break;
++ case BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL:
++ microblaze_reloc = R_MICROBLAZE_TLSGOTTPREL32;
++ break;
++ case BFD_RELOC_MICROBLAZE_64_TLSTPREL:
++ microblaze_reloc = R_MICROBLAZE_TLSTPREL32;
++ break;
++ case BFD_RELOC_MICROBLAZE_COPY:
++ microblaze_reloc = R_MICROBLAZE_COPY;
++ break;
++ default:
++ return (reloc_howto_type *) NULL;
++ }
++
++ if (!microblaze_elf_howto_table [R_MICROBLAZE_32])
++ /* Initialize howto table if needed. */
++ microblaze_elf_howto_init ();
++
++ return microblaze_elf_howto_table [(int) microblaze_reloc];
++};
++
++static reloc_howto_type *
++microblaze_elf_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
++ const char *r_name)
++{
++ unsigned int i;
++
++ for (i = 0; i < NUM_ELEM (microblaze_elf_howto_raw); i++)
++ if (microblaze_elf_howto_raw[i].name != NULL
++ && strcasecmp (microblaze_elf_howto_raw[i].name, r_name) == 0)
++ return µblaze_elf_howto_raw[i];
++
++ return NULL;
++}
++
++/* Set the howto pointer for a RCE ELF reloc. */
++
++static bfd_boolean
++microblaze_elf_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED,
++ arelent * cache_ptr,
++ Elf_Internal_Rela * dst)
++{
++ unsigned int r_type;
++
++ if (!microblaze_elf_howto_table [R_MICROBLAZE_32])
++ /* Initialize howto table if needed. */
++ microblaze_elf_howto_init ();
++
++ r_type = ELF64_R_TYPE (dst->r_info);
++ if (r_type >= R_MICROBLAZE_max)
++ {
++ (*_bfd_error_handler) (_("%pB: unrecognised MicroBlaze reloc number: %d"),
++ abfd, r_type);
++ bfd_set_error (bfd_error_bad_value);
++ return FALSE;
++ }
++
++ cache_ptr->howto = microblaze_elf_howto_table [r_type];
++ return TRUE;
++}
++
++/* Microblaze ELF local labels start with 'L.' or '$L', not '.L'. */
++
++static bfd_boolean
++microblaze_elf_is_local_label_name (bfd *abfd, const char *name)
++{
++ if (name[0] == 'L' && name[1] == '.')
++ return TRUE;
++
++ if (name[0] == '$' && name[1] == 'L')
++ return TRUE;
++
++ /* With gcc, the labels go back to starting with '.', so we accept
++ the generic ELF local label syntax as well. */
++ return _bfd_elf_is_local_label_name (abfd, name);
++}
++
++/* The microblaze linker (like many others) needs to keep track of
++ the number of relocs that it decides to copy as dynamic relocs in
++ check_relocs for each symbol. This is so that it can later discard
++ them if they are found to be unnecessary. We store the information
++ in a field extending the regular ELF linker hash table. */
++
++struct elf64_mb_dyn_relocs
++{
++ struct elf64_mb_dyn_relocs *next;
++
++ /* The input section of the reloc. */
++ asection *sec;
++
++ /* Total number of relocs copied for the input section. */
++ bfd_size_type count;
++
++ /* Number of pc-relative relocs copied for the input section. */
++ bfd_size_type pc_count;
++};
++
++/* ELF linker hash entry. */
++
++struct elf64_mb_link_hash_entry
++{
++ struct elf_link_hash_entry elf;
++
++ /* Track dynamic relocs copied for this symbol. */
++ struct elf64_mb_dyn_relocs *dyn_relocs;
++
++ /* TLS Reference Types for the symbol; Updated by check_relocs */
++#define TLS_GD 1 /* GD reloc. */
++#define TLS_LD 2 /* LD reloc. */
++#define TLS_TPREL 4 /* TPREL reloc, => IE. */
++#define TLS_DTPREL 8 /* DTPREL reloc, => LD. */
++#define TLS_TLS 16 /* Any TLS reloc. */
++ unsigned char tls_mask;
++
++};
++
++#define IS_TLS_GD(x) (x == (TLS_TLS | TLS_GD))
++#define IS_TLS_LD(x) (x == (TLS_TLS | TLS_LD))
++#define IS_TLS_DTPREL(x) (x == (TLS_TLS | TLS_DTPREL))
++#define IS_TLS_NONE(x) (x == 0)
++
++#define elf64_mb_hash_entry(ent) ((struct elf64_mb_link_hash_entry *)(ent))
++
++/* ELF linker hash table. */
++
++struct elf64_mb_link_hash_table
++{
++ struct elf_link_hash_table elf;
++
++ /* Short-cuts to get to dynamic linker sections. */
++ asection *sgot;
++ asection *sgotplt;
++ asection *srelgot;
++ asection *splt;
++ asection *srelplt;
++ asection *sdynbss;
++ asection *srelbss;
++
++ /* Small local sym to section mapping cache. */
++ struct sym_cache sym_sec;
++
++ /* TLS Local Dynamic GOT Entry */
++ union {
++ bfd_signed_vma refcount;
++ bfd_vma offset;
++ } tlsld_got;
++};
++
++/* Nonzero if this section has TLS related relocations. */
++#define has_tls_reloc sec_flg0
++
++/* Get the ELF linker hash table from a link_info structure. */
++
++#define elf64_mb_hash_table(p) \
++ (elf_hash_table_id ((struct elf_link_hash_table *) ((p)->hash)) \
++ == MICROBLAZE_ELF_DATA ? ((struct elf64_mb_link_hash_table *) ((p)->hash)) : NULL)
++
++/* Create an entry in a microblaze ELF linker hash table. */
++
++static struct bfd_hash_entry *
++link_hash_newfunc (struct bfd_hash_entry *entry,
++ struct bfd_hash_table *table,
++ const char *string)
++{
++ /* Allocate the structure if it has not already been allocated by a
++ subclass. */
++ if (entry == NULL)
++ {
++ entry = bfd_hash_allocate (table,
++ sizeof (struct elf64_mb_link_hash_entry));
++ if (entry == NULL)
++ return entry;
++ }
++
++ /* Call the allocation method of the superclass. */
++ entry = _bfd_elf_link_hash_newfunc (entry, table, string);
++ if (entry != NULL)
++ {
++ struct elf64_mb_link_hash_entry *eh;
++
++ eh = (struct elf64_mb_link_hash_entry *) entry;
++ eh->dyn_relocs = NULL;
++ eh->tls_mask = 0;
++ }
++
++ return entry;
++}
++
++/* Create a mb ELF linker hash table. */
++
++static struct bfd_link_hash_table *
++microblaze_elf_link_hash_table_create (bfd *abfd)
++{
++ struct elf64_mb_link_hash_table *ret;
++ bfd_size_type amt = sizeof (struct elf64_mb_link_hash_table);
++
++ ret = (struct elf64_mb_link_hash_table *) bfd_zmalloc (amt);
++ if (ret == NULL)
++ return NULL;
++
++ if (!_bfd_elf_link_hash_table_init (&ret->elf, abfd, link_hash_newfunc,
++ sizeof (struct elf64_mb_link_hash_entry),
++ MICROBLAZE_ELF_DATA))
++ {
++ free (ret);
++ return NULL;
++ }
++
++ return &ret->elf.root;
++}
++
++/* Set the values of the small data pointers. */
++
++static void
++microblaze_elf_final_sdp (struct bfd_link_info *info)
++{
++ struct bfd_link_hash_entry *h;
++
++ h = bfd_link_hash_lookup (info->hash, RO_SDA_ANCHOR_NAME, FALSE, FALSE, TRUE);
++ if (h != (struct bfd_link_hash_entry *) NULL
++ && h->type == bfd_link_hash_defined)
++ ro_small_data_pointer = (h->u.def.value
++ + h->u.def.section->output_section->vma
++ + h->u.def.section->output_offset);
++
++ h = bfd_link_hash_lookup (info->hash, RW_SDA_ANCHOR_NAME, FALSE, FALSE, TRUE);
++ if (h != (struct bfd_link_hash_entry *) NULL
++ && h->type == bfd_link_hash_defined)
++ rw_small_data_pointer = (h->u.def.value
++ + h->u.def.section->output_section->vma
++ + h->u.def.section->output_offset);
++}
++
++static bfd_vma
++dtprel_base (struct bfd_link_info *info)
++{
++ /* If tls_sec is NULL, we should have signalled an error already. */
++ if (elf_hash_table (info)->tls_sec == NULL)
++ return 0;
++ return elf_hash_table (info)->tls_sec->vma;
++}
++
++/* The size of the thread control block. */
++#define TCB_SIZE 8
++
++/* Output a simple dynamic relocation into SRELOC. */
++
++static void
++microblaze_elf_output_dynamic_relocation (bfd *output_bfd,
++ asection *sreloc,
++ unsigned long reloc_index,
++ unsigned long indx,
++ int r_type,
++ bfd_vma offset,
++ bfd_vma addend)
++{
++
++ Elf_Internal_Rela rel;
++
++ rel.r_info = ELF64_R_INFO (indx, r_type);
++ rel.r_offset = offset;
++ rel.r_addend = addend;
++
++ bfd_elf64_swap_reloca_out (output_bfd, &rel,
++ (sreloc->contents + reloc_index * sizeof (Elf64_External_Rela)));
++}
++
++/* This code is taken from elf64-m32r.c
++ There is some attempt to make this function usable for many architectures,
++ both USE_REL and USE_RELA ['twould be nice if such a critter existed],
++ if only to serve as a learning tool.
++
++ The RELOCATE_SECTION function is called by the new ELF backend linker
++ to handle the relocations for a section.
++
++ The relocs are always passed as Rela structures; if the section
++ actually uses Rel structures, the r_addend field will always be
++ zero.
++
++ This function is responsible for adjust the section contents as
++ necessary, and (if using Rela relocs and generating a
++ relocatable output file) adjusting the reloc addend as
++ necessary.
++
++ This function does not have to worry about setting the reloc
++ address or the reloc symbol index.
++
++ LOCAL_SYMS is a pointer to the swapped in local symbols.
++
++ LOCAL_SECTIONS is an array giving the section in the input file
++ corresponding to the st_shndx field of each local symbol.
++
++ The global hash table entry for the global symbols can be found
++ via elf_sym_hashes (input_bfd).
++
++ When generating relocatable output, this function must handle
++ STB_LOCAL/STT_SECTION symbols specially. The output symbol is
++ going to be the section symbol corresponding to the output
++ section, which means that the addend must be adjusted
++ accordingly. */
++
++static bfd_boolean
++microblaze_elf_relocate_section (bfd *output_bfd,
++ struct bfd_link_info *info,
++ bfd *input_bfd,
++ asection *input_section,
++ bfd_byte *contents,
++ Elf_Internal_Rela *relocs,
++ Elf_Internal_Sym *local_syms,
++ asection **local_sections)
++{
++ struct elf64_mb_link_hash_table *htab;
++ Elf_Internal_Shdr *symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
++ struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd);
++ Elf_Internal_Rela *rel, *relend;
++ int endian = (bfd_little_endian (output_bfd)) ? 0 : 2;
++ /* Assume success. */
++ bfd_boolean ret = TRUE;
++ asection *sreloc;
++ bfd_vma *local_got_offsets;
++ unsigned int tls_type;
++
++ if (!microblaze_elf_howto_table[R_MICROBLAZE_max-1])
++ microblaze_elf_howto_init ();
++
++ htab = elf64_mb_hash_table (info);
++ if (htab == NULL)
++ return FALSE;
++
++ local_got_offsets = elf_local_got_offsets (input_bfd);
++
++ sreloc = elf_section_data (input_section)->sreloc;
++
++ rel = relocs;
++ relend = relocs + input_section->reloc_count;
++ for (; rel < relend; rel++)
++ {
++ int r_type;
++ reloc_howto_type *howto;
++ unsigned long r_symndx;
++ bfd_vma addend = rel->r_addend;
++ bfd_vma offset = rel->r_offset;
++ struct elf_link_hash_entry *h;
++ Elf_Internal_Sym *sym;
++ asection *sec;
++ const char *sym_name;
++ bfd_reloc_status_type r = bfd_reloc_ok;
++ const char *errmsg = NULL;
++ bfd_boolean unresolved_reloc = FALSE;
++
++ h = NULL;
++ r_type = ELF64_R_TYPE (rel->r_info);
++ tls_type = 0;
++
++ if (r_type < 0 || r_type >= (int) R_MICROBLAZE_max)
++ {
++ (*_bfd_error_handler) (_("%s: unknown relocation type %d"),
++ bfd_get_filename (input_bfd), (int) r_type);
++ bfd_set_error (bfd_error_bad_value);
++ ret = FALSE;
++ continue;
++ }
++
++ howto = microblaze_elf_howto_table[r_type];
++ r_symndx = ELF64_R_SYM (rel->r_info);
++
++ if (bfd_link_relocatable (info))
++ {
++ /* This is a relocatable link. We don't have to change
++ anything, unless the reloc is against a section symbol,
++ in which case we have to adjust according to where the
++ section symbol winds up in the output section. */
++ sec = NULL;
++ if (r_symndx >= symtab_hdr->sh_info)
++ /* External symbol. */
++ continue;
++
++ /* Local symbol. */
++ sym = local_syms + r_symndx;
++ sym_name = "<local symbol>";
++ /* STT_SECTION: symbol is associated with a section. */
++ if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
++ /* Symbol isn't associated with a section. Nothing to do. */
++ continue;
++
++ sec = local_sections[r_symndx];
++ addend += sec->output_offset + sym->st_value;
++#ifndef USE_REL
++ /* This can't be done for USE_REL because it doesn't mean anything
++ and elf_link_input_bfd asserts this stays zero. */
++ /* rel->r_addend = addend; */
++#endif
++
++#ifndef USE_REL
++ /* Addends are stored with relocs. We're done. */
++ continue;
++#else /* USE_REL */
++ /* If partial_inplace, we need to store any additional addend
++ back in the section. */
++ if (!howto->partial_inplace)
++ continue;
++ /* ??? Here is a nice place to call a special_function like handler. */
++ r = _bfd_relocate_contents (howto, input_bfd, addend,
++ contents + offset);
++#endif /* USE_REL */
++ }
++ else
++ {
++ bfd_vma relocation;
++
++ /* This is a final link. */
++ sym = NULL;
++ sec = NULL;
++ unresolved_reloc = FALSE;
++
++ if (r_symndx < symtab_hdr->sh_info)
++ {
++ /* Local symbol. */
++ sym = local_syms + r_symndx;
++ sec = local_sections[r_symndx];
++ if (sec == 0)
++ continue;
++ sym_name = "<local symbol>";
++ relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
++ /* r_addend may have changed if the reference section was
++ a merge section. */
++ addend = rel->r_addend;
++ }
++ else
++ {
++ /* External symbol. */
++ bfd_boolean warned ATTRIBUTE_UNUSED;
++ bfd_boolean ignored ATTRIBUTE_UNUSED;
++
++ RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
++ r_symndx, symtab_hdr, sym_hashes,
++ h, sec, relocation,
++ unresolved_reloc, warned, ignored);
++ sym_name = h->root.root.string;
++ }
++
++ /* Sanity check the address. */
++ if (offset > bfd_get_section_limit (input_bfd, input_section))
++ {
++ r = bfd_reloc_outofrange;
++ goto check_reloc;
++ }
++
++ switch ((int) r_type)
++ {
++ case (int) R_MICROBLAZE_SRO32 :
++ {
++ const char *name;
++
++ /* Only relocate if the symbol is defined. */
++ if (sec)
++ {
++ name = bfd_section_name (sec);
++
++ if (strcmp (name, ".sdata2") == 0
++ || strcmp (name, ".sbss2") == 0)
++ {
++ if (ro_small_data_pointer == 0)
++ microblaze_elf_final_sdp (info);
++ if (ro_small_data_pointer == 0)
++ {
++ ret = FALSE;
++ r = bfd_reloc_undefined;
++ goto check_reloc;
++ }
++
++ /* At this point `relocation' contains the object's
++ address. */
++ relocation -= ro_small_data_pointer;
++ /* Now it contains the offset from _SDA2_BASE_. */
++ r = _bfd_final_link_relocate (howto, input_bfd,
++ input_section,
++ contents, offset,
++ relocation, addend);
++ }
++ else
++ {
++ (*_bfd_error_handler) (_("%s: The target (%s) of an %s relocation is in the wrong section (%s)"),
++ bfd_get_filename (input_bfd),
++ sym_name,
++ microblaze_elf_howto_table[(int) r_type]->name,
++ bfd_section_name (sec));
++ /*bfd_set_error (bfd_error_bad_value); ??? why? */
++ ret = FALSE;
++ continue;
++ }
++ }
++ }
++ break;
++
++ case (int) R_MICROBLAZE_SRW32 :
++ {
++ const char *name;
++
++ /* Only relocate if the symbol is defined. */
++ if (sec)
++ {
++ name = bfd_section_name (sec);
++
++ if (strcmp (name, ".sdata") == 0
++ || strcmp (name, ".sbss") == 0)
++ {
++ if (rw_small_data_pointer == 0)
++ microblaze_elf_final_sdp (info);
++ if (rw_small_data_pointer == 0)
++ {
++ ret = FALSE;
++ r = bfd_reloc_undefined;
++ goto check_reloc;
++ }
++
++ /* At this point `relocation' contains the object's
++ address. */
++ relocation -= rw_small_data_pointer;
++ /* Now it contains the offset from _SDA_BASE_. */
++ r = _bfd_final_link_relocate (howto, input_bfd,
++ input_section,
++ contents, offset,
++ relocation, addend);
++ }
++ else
++ {
++ (*_bfd_error_handler) (_("%s: The target (%s) of an %s relocation is in the wrong section (%s)"),
++ bfd_get_filename (input_bfd),
++ sym_name,
++ microblaze_elf_howto_table[(int) r_type]->name,
++ bfd_section_name (sec));
++ /*bfd_set_error (bfd_error_bad_value); ??? why? */
++ ret = FALSE;
++ continue;
++ }
++ }
++ }
++ break;
++
++ case (int) R_MICROBLAZE_32_SYM_OP_SYM:
++ break; /* Do nothing. */
++
++ case (int) R_MICROBLAZE_GOTPC_64:
++ relocation = htab->sgotplt->output_section->vma
++ + htab->sgotplt->output_offset;
++ relocation -= (input_section->output_section->vma
++ + input_section->output_offset
++ + offset + INST_WORD_SIZE);
++ relocation += addend;
++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++ contents + offset + endian);
++ bfd_put_16 (input_bfd, relocation & 0xffff,
++ contents + offset + endian + INST_WORD_SIZE);
++ break;
++
++ case (int) R_MICROBLAZE_PLT_64:
++ {
++ bfd_vma immediate;
++ if (htab->splt != NULL && h != NULL
++ && h->plt.offset != (bfd_vma) -1)
++ {
++ relocation = (htab->splt->output_section->vma
++ + htab->splt->output_offset
++ + h->plt.offset);
++ unresolved_reloc = FALSE;
++ immediate = relocation - (input_section->output_section->vma
++ + input_section->output_offset
++ + offset + INST_WORD_SIZE);
++ bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff,
++ contents + offset + endian);
++ bfd_put_16 (input_bfd, immediate & 0xffff,
++ contents + offset + endian + INST_WORD_SIZE);
++ }
++ else
++ {
++ relocation -= (input_section->output_section->vma
++ + input_section->output_offset
++ + offset + INST_WORD_SIZE);
++ immediate = relocation;
++ bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff,
++ contents + offset + endian);
++ bfd_put_16 (input_bfd, immediate & 0xffff,
++ contents + offset + endian + INST_WORD_SIZE);
++ }
++ break;
++ }
++
++ case (int) R_MICROBLAZE_TLSGD:
++ tls_type = (TLS_TLS | TLS_GD);
++ goto dogot;
++ case (int) R_MICROBLAZE_TLSLD:
++ tls_type = (TLS_TLS | TLS_LD);
++ /* Fall through. */
++ dogot:
++ case (int) R_MICROBLAZE_GOT_64:
++ {
++ bfd_vma *offp;
++ bfd_vma off, off2;
++ unsigned long indx;
++ bfd_vma static_value;
++
++ bfd_boolean need_relocs = FALSE;
++ if (htab->sgot == NULL)
++ abort ();
++
++ indx = 0;
++ offp = NULL;
++
++ /* 1. Identify GOT Offset;
++ 2. Compute Static Values
++ 3. Process Module Id, Process Offset
++ 4. Fixup Relocation with GOT offset value. */
++
++ /* 1. Determine GOT Offset to use : TLS_LD, global, local */
++ if (IS_TLS_LD (tls_type))
++ offp = &htab->tlsld_got.offset;
++ else if (h != NULL)
++ {
++ if (htab->sgotplt != NULL && h->got.offset != (bfd_vma) -1)
++ offp = &h->got.offset;
++ else
++ abort ();
++ }
++ else
++ {
++ if (local_got_offsets == NULL)
++ abort ();
++ offp = &local_got_offsets[r_symndx];
++ }
++
++ if (!offp)
++ abort ();
++
++ off = (*offp) & ~1;
++ off2 = off;
++
++ if (IS_TLS_LD(tls_type) || IS_TLS_GD(tls_type))
++ off2 = off + 4;
++
++ /* Symbol index to use for relocs */
++ if (h != NULL)
++ {
++ bfd_boolean dyn =
++ elf_hash_table (info)->dynamic_sections_created;
++
++ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
++ bfd_link_pic (info),
++ h)
++ && (!bfd_link_pic (info)
++ || !SYMBOL_REFERENCES_LOCAL (info, h)))
++ indx = h->dynindx;
++ }
++
++ /* Need to generate relocs ? */
++ if ((bfd_link_pic (info) || indx != 0)
++ && (h == NULL
++ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
++ || h->root.type != bfd_link_hash_undefweak))
++ need_relocs = TRUE;
++
++ /* 2. Compute/Emit Static value of r-expression */
++ static_value = relocation + addend;
++
++ /* 3. Process module-id and offset */
++ if (! ((*offp) & 1) )
++ {
++ bfd_vma got_offset;
++
++ got_offset = (htab->sgot->output_section->vma
++ + htab->sgot->output_offset
++ + off);
++
++ /* Process module-id */
++ if (IS_TLS_LD(tls_type))
++ {
++ if (! bfd_link_pic (info))
++ {
++ bfd_put_32 (output_bfd, 1, htab->sgot->contents + off);
++ }
++ else
++ {
++ microblaze_elf_output_dynamic_relocation (output_bfd,
++ htab->srelgot, htab->srelgot->reloc_count++,
++ /* symindex= */ 0, R_MICROBLAZE_TLSDTPMOD32,
++ got_offset, 0);
++ }
++ }
++ else if (IS_TLS_GD(tls_type))
++ {
++ if (! need_relocs)
++ {
++ bfd_put_32 (output_bfd, 1, htab->sgot->contents + off);
++ }
++ else
++ {
++ microblaze_elf_output_dynamic_relocation (output_bfd,
++ htab->srelgot,
++ htab->srelgot->reloc_count++,
++ /* symindex= */ indx, R_MICROBLAZE_TLSDTPMOD32,
++ got_offset, indx ? 0 : static_value);
++ }
++ }
++
++ /* Process Offset */
++ if (htab->srelgot == NULL)
++ abort ();
++
++ got_offset = (htab->sgot->output_section->vma
++ + htab->sgot->output_offset
++ + off2);
++ if (IS_TLS_LD(tls_type))
++ {
++ /* For LD, offset should be 0 */
++ *offp |= 1;
++ bfd_put_32 (output_bfd, 0, htab->sgot->contents + off2);
++ }
++ else if (IS_TLS_GD(tls_type))
++ {
++ *offp |= 1;
++ static_value -= dtprel_base(info);
++ if (need_relocs)
++ {
++ microblaze_elf_output_dynamic_relocation (output_bfd,
++ htab->srelgot, htab->srelgot->reloc_count++,
++ /* symindex= */ indx, R_MICROBLAZE_TLSDTPREL32,
++ got_offset, indx ? 0 : static_value);
++ }
++ else
++ {
++ bfd_put_32 (output_bfd, static_value,
++ htab->sgot->contents + off2);
++ }
++ }
++ else
++ {
++ bfd_put_32 (output_bfd, static_value,
++ htab->sgot->contents + off2);
++
++ /* Relocs for dyn symbols generated by
++ finish_dynamic_symbols */
++ if (bfd_link_pic (info) && h == NULL)
++ {
++ *offp |= 1;
++ microblaze_elf_output_dynamic_relocation (output_bfd,
++ htab->srelgot, htab->srelgot->reloc_count++,
++ /* symindex= */ indx, R_MICROBLAZE_REL,
++ got_offset, static_value);
++ }
++ }
++ }
++
++ /* 4. Fixup Relocation with GOT offset value
++ Compute relative address of GOT entry for applying
++ the current relocation */
++ relocation = htab->sgot->output_section->vma
++ + htab->sgot->output_offset
++ + off
++ - htab->sgotplt->output_section->vma
++ - htab->sgotplt->output_offset;
++
++ /* Apply Current Relocation */
++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++ contents + offset + endian);
++ bfd_put_16 (input_bfd, relocation & 0xffff,
++ contents + offset + endian + INST_WORD_SIZE);
++
++ unresolved_reloc = FALSE;
++ break;
++ }
++
++ case (int) R_MICROBLAZE_GOTOFF_64:
++ {
++ bfd_vma immediate;
++ unsigned short lo, high;
++ relocation += addend;
++ relocation -= htab->sgotplt->output_section->vma
++ + htab->sgotplt->output_offset;
++ /* Write this value into correct location. */
++ immediate = relocation;
++ lo = immediate & 0x0000ffff;
++ high = (immediate >> 16) & 0x0000ffff;
++ bfd_put_16 (input_bfd, high, contents + offset + endian);
++ bfd_put_16 (input_bfd, lo, contents + offset + INST_WORD_SIZE + endian);
++ break;
++ }
++
++ case (int) R_MICROBLAZE_GOTOFF_32:
++ {
++ relocation += addend;
++ relocation -= htab->sgotplt->output_section->vma
++ + htab->sgotplt->output_offset;
++ /* Write this value into correct location. */
++ bfd_put_32 (input_bfd, relocation, contents + offset);
++ break;
++ }
++
++ case (int) R_MICROBLAZE_TLSDTPREL64:
++ relocation += addend;
++ relocation -= dtprel_base(info);
++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++ contents + offset + endian);
++ bfd_put_16 (input_bfd, relocation & 0xffff,
++ contents + offset + endian + INST_WORD_SIZE);
++ break;
++ case (int) R_MICROBLAZE_64_PCREL :
++ case (int) R_MICROBLAZE_64:
++ case (int) R_MICROBLAZE_32:
++ {
++ /* r_symndx will be STN_UNDEF (zero) only for relocs against symbols
++ from removed linkonce sections, or sections discarded by
++ a linker script. */
++ if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0)
++ {
++ relocation += addend;
++ if (r_type == R_MICROBLAZE_32)
++ bfd_put_32 (input_bfd, relocation, contents + offset);
++ else
++ {
++ if (r_type == R_MICROBLAZE_64_PCREL)
++ relocation -= (input_section->output_section->vma
++ + input_section->output_offset
++ + offset + INST_WORD_SIZE);
++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++ contents + offset + endian);
++ bfd_put_16 (input_bfd, relocation & 0xffff,
++ contents + offset + endian + INST_WORD_SIZE);
++ }
++ break;
++ }
++
++ if ((bfd_link_pic (info)
++ && (h == NULL
++ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
++ || h->root.type != bfd_link_hash_undefweak)
++ && (!howto->pc_relative
++ || (h != NULL
++ && h->dynindx != -1
++ && (!info->symbolic
++ || !h->def_regular))))
++ || (!bfd_link_pic (info)
++ && h != NULL
++ && h->dynindx != -1
++ && !h->non_got_ref
++ && ((h->def_dynamic
++ && !h->def_regular)
++ || h->root.type == bfd_link_hash_undefweak
++ || h->root.type == bfd_link_hash_undefined)))
++ {
++ Elf_Internal_Rela outrel;
++ bfd_byte *loc;
++ bfd_boolean skip;
++
++ /* When generating a shared object, these relocations
++ are copied into the output file to be resolved at run
++ time. */
++
++ BFD_ASSERT (sreloc != NULL);
++
++ skip = FALSE;
++
++ outrel.r_offset =
++ _bfd_elf_section_offset (output_bfd, info, input_section,
++ rel->r_offset);
++ if (outrel.r_offset == (bfd_vma) -1)
++ skip = TRUE;
++ else if (outrel.r_offset == (bfd_vma) -2)
++ skip = TRUE;
++ outrel.r_offset += (input_section->output_section->vma
++ + input_section->output_offset);
++
++ if (skip)
++ memset (&outrel, 0, sizeof outrel);
++ /* h->dynindx may be -1 if the symbol was marked to
++ become local. */
++ else if (h != NULL
++ && ((! info->symbolic && h->dynindx != -1)
++ || !h->def_regular))
++ {
++ BFD_ASSERT (h->dynindx != -1);
++ outrel.r_info = ELF64_R_INFO (h->dynindx, r_type);
++ outrel.r_addend = addend;
++ }
++ else
++ {
++ if (r_type == R_MICROBLAZE_32)
++ {
++ outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL);
++ outrel.r_addend = relocation + addend;
++ }
++ else
++ {
++ BFD_FAIL ();
++ (*_bfd_error_handler)
++ (_("%pB: probably compiled without -fPIC?"),
++ input_bfd);
++ bfd_set_error (bfd_error_bad_value);
++ return FALSE;
++ }
++ }
++
++ loc = sreloc->contents;
++ loc += sreloc->reloc_count++ * sizeof (Elf64_External_Rela);
++ bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
++ break;
++ }
++ else
++ {
++ relocation += addend;
++ if (r_type == R_MICROBLAZE_32)
++ bfd_put_32 (input_bfd, relocation, contents + offset);
++ else
++ {
++ if (r_type == R_MICROBLAZE_64_PCREL)
++ relocation -= (input_section->output_section->vma
++ + input_section->output_offset
++ + offset + INST_WORD_SIZE);
++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++ contents + offset + endian);
++ bfd_put_16 (input_bfd, relocation & 0xffff,
++ contents + offset + endian + INST_WORD_SIZE);
++ }
++ break;
++ }
++ }
++
++ default :
++ r = _bfd_final_link_relocate (howto, input_bfd, input_section,
++ contents, offset,
++ relocation, addend);
++ break;
++ }
++ }
++
++ check_reloc:
++
++ if (r != bfd_reloc_ok)
++ {
++ /* FIXME: This should be generic enough to go in a utility. */
++ const char *name;
++
++ if (h != NULL)
++ name = h->root.root.string;
++ else
++ {
++ name = (bfd_elf_string_from_elf_section
++ (input_bfd, symtab_hdr->sh_link, sym->st_name));
++ if (name == NULL || *name == '\0')
++ name = bfd_section_name (sec);
++ }
++
++ if (errmsg != NULL)
++ goto common_error;
++
++ switch (r)
++ {
++ case bfd_reloc_overflow:
++ (*info->callbacks->reloc_overflow)
++ (info, (h ? &h->root : NULL), name, howto->name,
++ (bfd_vma) 0, input_bfd, input_section, offset);
++ break;
++
++ case bfd_reloc_undefined:
++ (*info->callbacks->undefined_symbol)
++ (info, name, input_bfd, input_section, offset, TRUE);
++ break;
++
++ case bfd_reloc_outofrange:
++ errmsg = _("internal error: out of range error");
++ goto common_error;
++
++ case bfd_reloc_notsupported:
++ errmsg = _("internal error: unsupported relocation error");
++ goto common_error;
++
++ case bfd_reloc_dangerous:
++ errmsg = _("internal error: dangerous error");
++ goto common_error;
++
++ default:
++ errmsg = _("internal error: unknown error");
++ /* Fall through. */
++ common_error:
++ (*info->callbacks->warning) (info, errmsg, name, input_bfd,
++ input_section, offset);
++ break;
++ }
++ }
++ }
++
++ return ret;
++}
++
++/* Calculate fixup value for reference. */
++
++static int
++calc_fixup (bfd_vma start, bfd_vma size, asection *sec)
++{
++ bfd_vma end = start + size;
++ int i, fixup = 0;
++
++ if (sec == NULL || sec->relax == NULL)
++ return 0;
++
++ /* Look for addr in relax table, total fixup value. */
++ for (i = 0; i < sec->relax_count; i++)
++ {
++ if (end <= sec->relax[i].addr)
++ break;
++ if ((end != start) && (start > sec->relax[i].addr))
++ continue;
++ fixup += sec->relax[i].size;
++ }
++ return fixup;
++}
++
++/* Read-modify-write into the bfd, an immediate value into appropriate fields of
++ a 32-bit instruction. */
++static void
++microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
++{
++ unsigned long instr = bfd_get_32 (abfd, bfd_addr);
++ instr &= ~0x0000ffff;
++ instr |= (val & 0x0000ffff);
++ bfd_put_32 (abfd, instr, bfd_addr);
++}
++
++/* Read-modify-write into the bfd, an immediate value into appropriate fields of
++ two consecutive 32-bit instructions. */
++static void
++microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
++{
++ unsigned long instr_hi;
++ unsigned long instr_lo;
++
++ instr_hi = bfd_get_32 (abfd, bfd_addr);
++ instr_hi &= ~0x0000ffff;
++ instr_hi |= ((val >> 16) & 0x0000ffff);
++ bfd_put_32 (abfd, instr_hi, bfd_addr);
++
++ instr_lo = bfd_get_32 (abfd, bfd_addr + INST_WORD_SIZE);
++ instr_lo &= ~0x0000ffff;
++ instr_lo |= (val & 0x0000ffff);
++ bfd_put_32 (abfd, instr_lo, bfd_addr + INST_WORD_SIZE);
++}
++
++static bfd_boolean
++microblaze_elf_relax_section (bfd *abfd,
++ asection *sec,
++ struct bfd_link_info *link_info,
++ bfd_boolean *again)
++{
++ Elf_Internal_Shdr *symtab_hdr;
++ Elf_Internal_Rela *internal_relocs;
++ Elf_Internal_Rela *free_relocs = NULL;
++ Elf_Internal_Rela *irel, *irelend;
++ bfd_byte *contents = NULL;
++ bfd_byte *free_contents = NULL;
++ int rel_count;
++ unsigned int shndx;
++ int i, sym_index;
++ asection *o;
++ struct elf_link_hash_entry *sym_hash;
++ Elf_Internal_Sym *isymbuf, *isymend;
++ Elf_Internal_Sym *isym;
++ int symcount;
++ int offset;
++ bfd_vma src, dest;
++
++ /* We only do this once per section. We may be able to delete some code
++ by running multiple passes, but it is not worth it. */
++ *again = FALSE;
++
++ /* Only do this for a text section. */
++ if (bfd_link_relocatable (link_info)
++ || (sec->flags & SEC_RELOC) == 0
++ || (sec->reloc_count == 0)
++ || (sec->flags & SEC_CODE) == 0)
++ return TRUE;
++
++ BFD_ASSERT ((sec->size > 0) || (sec->rawsize > 0));
++
++ /* If this is the first time we have been called for this section,
++ initialize the cooked size. */
++ if (sec->size == 0)
++ sec->size = sec->rawsize;
++
++ /* Get symbols for this section. */
++ symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
++ isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
++ symcount = symtab_hdr->sh_size / sizeof (Elf64_External_Sym);
++ if (isymbuf == NULL)
++ isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, symcount,
++ 0, NULL, NULL, NULL);
++ BFD_ASSERT (isymbuf != NULL);
++
++ internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory);
++ if (internal_relocs == NULL)
++ goto error_return;
++ if (! link_info->keep_memory)
++ free_relocs = internal_relocs;
++
++ sec->relax = (struct relax_table *) bfd_malloc ((sec->reloc_count + 1)
++ * sizeof (struct relax_table));
++ if (sec->relax == NULL)
++ goto error_return;
++ sec->relax_count = 0;
++
++ irelend = internal_relocs + sec->reloc_count;
++ rel_count = 0;
++ for (irel = internal_relocs; irel < irelend; irel++, rel_count++)
++ {
++ bfd_vma symval;
++ if ((ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64_PCREL)
++ && (ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64 ))
++ continue; /* Can't delete this reloc. */
++
++ /* Get the section contents. */
++ if (contents == NULL)
++ {
++ if (elf_section_data (sec)->this_hdr.contents != NULL)
++ contents = elf_section_data (sec)->this_hdr.contents;
++ else
++ {
++ contents = (bfd_byte *) bfd_malloc (sec->size);
++ if (contents == NULL)
++ goto error_return;
++ free_contents = contents;
++
++ if (!bfd_get_section_contents (abfd, sec, contents,
++ (file_ptr) 0, sec->size))
++ goto error_return;
++ elf_section_data (sec)->this_hdr.contents = contents;
++ }
++ }
++
++ /* Get the value of the symbol referred to by the reloc. */
++ if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info)
++ {
++ /* A local symbol. */
++ asection *sym_sec;
++
++ isym = isymbuf + ELF64_R_SYM (irel->r_info);
++ if (isym->st_shndx == SHN_UNDEF)
++ sym_sec = bfd_und_section_ptr;
++ else if (isym->st_shndx == SHN_ABS)
++ sym_sec = bfd_abs_section_ptr;
++ else if (isym->st_shndx == SHN_COMMON)
++ sym_sec = bfd_com_section_ptr;
++ else
++ sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
++
++ symval = _bfd_elf_rela_local_sym (abfd, isym, &sym_sec, irel);
++ }
++ else
++ {
++ unsigned long indx;
++ struct elf_link_hash_entry *h;
++
++ indx = ELF64_R_SYM (irel->r_info) - symtab_hdr->sh_info;
++ h = elf_sym_hashes (abfd)[indx];
++ BFD_ASSERT (h != NULL);
++
++ if (h->root.type != bfd_link_hash_defined
++ && h->root.type != bfd_link_hash_defweak)
++ /* This appears to be a reference to an undefined
++ symbol. Just ignore it--it will be caught by the
++ regular reloc processing. */
++ continue;
++
++ symval = (h->root.u.def.value
++ + h->root.u.def.section->output_section->vma
++ + h->root.u.def.section->output_offset);
++ }
++
++ /* If this is a PC-relative reloc, subtract the instr offset from
++ the symbol value. */
++ if (ELF64_R_TYPE (irel->r_info) == (int) R_MICROBLAZE_64_PCREL)
++ {
++ symval = symval + irel->r_addend
++ - (irel->r_offset
++ + sec->output_section->vma
++ + sec->output_offset);
++ }
++ else
++ symval += irel->r_addend;
++
++ if ((symval & 0xffff8000) == 0)
++ {
++ /* We can delete this instruction. */
++ sec->relax[sec->relax_count].addr = irel->r_offset;
++ sec->relax[sec->relax_count].size = INST_WORD_SIZE;
++ sec->relax_count++;
++
++ /* Rewrite relocation type. */
++ switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info))
++ {
++ case R_MICROBLAZE_64_PCREL:
++ irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info),
++ (int) R_MICROBLAZE_32_PCREL_LO);
++ break;
++ case R_MICROBLAZE_64:
++ irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info),
++ (int) R_MICROBLAZE_32_LO);
++ break;
++ default:
++ /* Cannot happen. */
++ BFD_ASSERT (FALSE);
++ }
++ }
++ } /* Loop through all relocations. */
++
++ /* Loop through the relocs again, and see if anything needs to change. */
++ if (sec->relax_count > 0)
++ {
++ shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
++ rel_count = 0;
++ sec->relax[sec->relax_count].addr = sec->size;
++
++ for (irel = internal_relocs; irel < irelend; irel++, rel_count++)
++ {
++ bfd_vma nraddr;
++
++ /* Get the new reloc address. */
++ nraddr = irel->r_offset - calc_fixup (irel->r_offset, 0, sec);
++ switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info))
++ {
++ default:
++ break;
++ case R_MICROBLAZE_64_PCREL:
++ break;
++ case R_MICROBLAZE_64:
++ case R_MICROBLAZE_32_LO:
++ /* If this reloc is against a symbol defined in this
++ section, we must check the addend to see it will put the value in
++ range to be adjusted, and hence must be changed. */
++ if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info)
++ {
++ isym = isymbuf + ELF64_R_SYM (irel->r_info);
++ /* Only handle relocs against .text. */
++ if (isym->st_shndx == shndx
++ && ELF64_ST_TYPE (isym->st_info) == STT_SECTION)
++ irel->r_addend -= calc_fixup (irel->r_addend, 0, sec);
++ }
++ break;
++ case R_MICROBLAZE_NONE:
++ case R_MICROBLAZE_32_NONE:
++ {
++ /* This was a PC-relative instruction that was
++ completely resolved. */
++ int sfix, efix;
++ unsigned int val;
++ bfd_vma target_address;
++ target_address = irel->r_addend + irel->r_offset;
++ sfix = calc_fixup (irel->r_offset, 0, sec);
++ efix = calc_fixup (target_address, 0, sec);
++
++ /* Validate the in-band val. */
++ val = bfd_get_32 (abfd, contents + irel->r_offset);
++ if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++ }
++ irel->r_addend -= (efix - sfix);
++ /* Should use HOWTO. */
++ microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
++ irel->r_addend);
++ }
++ break;
++ case R_MICROBLAZE_64_NONE:
++ {
++ /* This was a PC-relative 64-bit instruction that was
++ completely resolved. */
++ int sfix, efix;
++ bfd_vma target_address;
++ target_address = irel->r_addend + irel->r_offset + INST_WORD_SIZE;
++ sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec);
++ efix = calc_fixup (target_address, 0, sec);
++ irel->r_addend -= (efix - sfix);
++ microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset
++ + INST_WORD_SIZE, irel->r_addend);
++ }
++ break;
++ }
++ irel->r_offset = nraddr;
++ } /* Change all relocs in this section. */
++
++ /* Look through all other sections. */
++ for (o = abfd->sections; o != NULL; o = o->next)
++ {
++ Elf_Internal_Rela *irelocs;
++ Elf_Internal_Rela *irelscan, *irelscanend;
++ bfd_byte *ocontents;
++
++ if (o == sec
++ || (o->flags & SEC_RELOC) == 0
++ || o->reloc_count == 0)
++ continue;
++
++ /* We always cache the relocs. Perhaps, if info->keep_memory is
++ FALSE, we should free them, if we are permitted to. */
++
++ irelocs = _bfd_elf_link_read_relocs (abfd, o, NULL, NULL, TRUE);
++ if (irelocs == NULL)
++ goto error_return;
++
++ ocontents = NULL;
++ irelscanend = irelocs + o->reloc_count;
++ for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
++ {
++ if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
++ {
++ unsigned int val;
++
++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++ /* hax: We only do the following fixup for debug location lists. */
++ if (strcmp(".debug_loc", o->name))
++ continue;
++
++ /* This was a PC-relative instruction that was completely resolved. */
++ if (ocontents == NULL)
++ {
++ if (elf_section_data (o)->this_hdr.contents != NULL)
++ ocontents = elf_section_data (o)->this_hdr.contents;
++ else
++ {
++ /* We always cache the section contents.
++ Perhaps, if info->keep_memory is FALSE, we
++ should free them, if we are permitted to. */
++
++ if (o->rawsize == 0)
++ o->rawsize = o->size;
++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++ if (ocontents == NULL)
++ goto error_return;
++ if (!bfd_get_section_contents (abfd, o, ocontents,
++ (file_ptr) 0,
++ o->rawsize))
++ goto error_return;
++ elf_section_data (o)->this_hdr.contents = ocontents;
++ }
++ }
++
++ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++ if (val != irelscan->r_addend) {
++ fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
++ }
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
++ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
++ irelscan->r_addend);
++ }
++ if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
++ {
++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++ /* Look at the reloc only if the value has been resolved. */
++ if (isym->st_shndx == shndx
++ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
++ {
++ if (ocontents == NULL)
++ {
++ if (elf_section_data (o)->this_hdr.contents != NULL)
++ ocontents = elf_section_data (o)->this_hdr.contents;
++ else
++ {
++ /* We always cache the section contents.
++ Perhaps, if info->keep_memory is FALSE, we
++ should free them, if we are permitted to. */
++ if (o->rawsize == 0)
++ o->rawsize = o->size;
++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++ if (ocontents == NULL)
++ goto error_return;
++ if (!bfd_get_section_contents (abfd, o, ocontents,
++ (file_ptr) 0,
++ o->rawsize))
++ goto error_return;
++ elf_section_data (o)->this_hdr.contents = ocontents;
++ }
++
++ }
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
++ }
++ else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_SYM_OP_SYM)
++ {
++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++ /* Look at the reloc only if the value has been resolved. */
++ if (ocontents == NULL)
++ {
++ if (elf_section_data (o)->this_hdr.contents != NULL)
++ ocontents = elf_section_data (o)->this_hdr.contents;
++ else
++ {
++ /* We always cache the section contents.
++ Perhaps, if info->keep_memory is FALSE, we
++ should free them, if we are permitted to. */
++
++ if (o->rawsize == 0)
++ o->rawsize = o->size;
++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++ if (ocontents == NULL)
++ goto error_return;
++ if (!bfd_get_section_contents (abfd, o, ocontents,
++ (file_ptr) 0,
++ o->rawsize))
++ goto error_return;
++ elf_section_data (o)->this_hdr.contents = ocontents;
++ }
++ }
++ irelscan->r_addend -= calc_fixup (irelscan->r_addend
++ + isym->st_value,
++ 0,
++ sec);
++ }
++ }
++ else if ((ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_PCREL_LO)
++ || (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_LO))
++ {
++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++ /* Look at the reloc only if the value has been resolved. */
++ if (isym->st_shndx == shndx
++ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
++ {
++ bfd_vma immediate;
++ bfd_vma target_address;
++
++ if (ocontents == NULL)
++ {
++ if (elf_section_data (o)->this_hdr.contents != NULL)
++ ocontents = elf_section_data (o)->this_hdr.contents;
++ else
++ {
++ /* We always cache the section contents.
++ Perhaps, if info->keep_memory is FALSE, we
++ should free them, if we are permitted to. */
++ if (o->rawsize == 0)
++ o->rawsize = o->size;
++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++ if (ocontents == NULL)
++ goto error_return;
++ if (!bfd_get_section_contents (abfd, o, ocontents,
++ (file_ptr) 0,
++ o->rawsize))
++ goto error_return;
++ elf_section_data (o)->this_hdr.contents = ocontents;
++ }
++ }
++
++ unsigned long instr = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++ immediate = instr & 0x0000ffff;
++ target_address = immediate;
++ offset = calc_fixup (target_address, 0, sec);
++ immediate -= offset;
++ irelscan->r_addend -= offset;
++ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
++ irelscan->r_addend);
++ }
++ }
++
++ if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64)
++ {
++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++ /* Look at the reloc only if the value has been resolved. */
++ if (isym->st_shndx == shndx
++ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
++ {
++ bfd_vma immediate;
++
++ if (ocontents == NULL)
++ {
++ if (elf_section_data (o)->this_hdr.contents != NULL)
++ ocontents = elf_section_data (o)->this_hdr.contents;
++ else
++ {
++ /* We always cache the section contents.
++ Perhaps, if info->keep_memory is FALSE, we
++ should free them, if we are permitted to. */
++
++ if (o->rawsize == 0)
++ o->rawsize = o->size;
++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++ if (ocontents == NULL)
++ goto error_return;
++ if (!bfd_get_section_contents (abfd, o, ocontents,
++ (file_ptr) 0,
++ o->rawsize))
++ goto error_return;
++ elf_section_data (o)->this_hdr.contents = ocontents;
++ }
++ }
++ unsigned long instr_hi = bfd_get_32 (abfd, ocontents
++ + irelscan->r_offset);
++ unsigned long instr_lo = bfd_get_32 (abfd, ocontents
++ + irelscan->r_offset
++ + INST_WORD_SIZE);
++ immediate = (instr_hi & 0x0000ffff) << 16;
++ immediate |= (instr_lo & 0x0000ffff);
++ offset = calc_fixup (irelscan->r_addend, 0, sec);
++ immediate -= offset;
++ irelscan->r_addend -= offset;
++ }
++ }
++ else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_PCREL)
++ {
++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++ /* Look at the reloc only if the value has been resolved. */
++ if (isym->st_shndx == shndx
++ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
++ {
++ bfd_vma immediate;
++ bfd_vma target_address;
++
++ if (ocontents == NULL)
++ {
++ if (elf_section_data (o)->this_hdr.contents != NULL)
++ ocontents = elf_section_data (o)->this_hdr.contents;
++ else
++ {
++ /* We always cache the section contents.
++ Perhaps, if info->keep_memory is FALSE, we
++ should free them, if we are permitted to. */
++ if (o->rawsize == 0)
++ o->rawsize = o->size;
++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++ if (ocontents == NULL)
++ goto error_return;
++ if (!bfd_get_section_contents (abfd, o, ocontents,
++ (file_ptr) 0,
++ o->rawsize))
++ goto error_return;
++ elf_section_data (o)->this_hdr.contents = ocontents;
++ }
++ }
++ unsigned long instr_hi = bfd_get_32 (abfd, ocontents
++ + irelscan->r_offset);
++ unsigned long instr_lo = bfd_get_32 (abfd, ocontents
++ + irelscan->r_offset
++ + INST_WORD_SIZE);
++ immediate = (instr_hi & 0x0000ffff) << 16;
++ immediate |= (instr_lo & 0x0000ffff);
++ target_address = immediate;
++ offset = calc_fixup (target_address, 0, sec);
++ immediate -= offset;
++ irelscan->r_addend -= offset;
++ microblaze_bfd_write_imm_value_64 (abfd, ocontents
++ + irelscan->r_offset, immediate);
++ }
++ }
++ }
++ }
++
++ /* Adjust the local symbols defined in this section. */
++ isymend = isymbuf + symtab_hdr->sh_info;
++ for (isym = isymbuf; isym < isymend; isym++)
++ {
++ if (isym->st_shndx == shndx)
++ {
++ isym->st_value -= calc_fixup (isym->st_value, 0, sec);
++ if (isym->st_size)
++ isym->st_size -= calc_fixup (isym->st_value, isym->st_size, sec);
++ }
++ }
++
++ /* Now adjust the global symbols defined in this section. */
++ isym = isymbuf + symtab_hdr->sh_info;
++ symcount = (symtab_hdr->sh_size / sizeof (Elf64_External_Sym)) - symtab_hdr->sh_info;
++ for (sym_index = 0; sym_index < symcount; sym_index++)
++ {
++ sym_hash = elf_sym_hashes (abfd)[sym_index];
++ if ((sym_hash->root.type == bfd_link_hash_defined
++ || sym_hash->root.type == bfd_link_hash_defweak)
++ && sym_hash->root.u.def.section == sec)
++ {
++ sym_hash->root.u.def.value -= calc_fixup (sym_hash->root.u.def.value,
++ 0, sec);
++ if (sym_hash->size)
++ sym_hash->size -= calc_fixup (sym_hash->root.u.def.value,
++ sym_hash->size, sec);
++ }
++ }
++
++ /* Physically move the code and change the cooked size. */
++ dest = sec->relax[0].addr;
++ for (i = 0; i < sec->relax_count; i++)
++ {
++ int len;
++ src = sec->relax[i].addr + sec->relax[i].size;
++ len = sec->relax[i+1].addr - sec->relax[i].addr - sec->relax[i].size;
++
++ memmove (contents + dest, contents + src, len);
++ sec->size -= sec->relax[i].size;
++ dest += len;
++ }
++
++ elf_section_data (sec)->relocs = internal_relocs;
++ free_relocs = NULL;
++
++ elf_section_data (sec)->this_hdr.contents = contents;
++ free_contents = NULL;
++
++ symtab_hdr->contents = (bfd_byte *) isymbuf;
++ }
++
++ if (free_relocs != NULL)
++ {
++ free (free_relocs);
++ free_relocs = NULL;
++ }
++
++ if (free_contents != NULL)
++ {
++ if (!link_info->keep_memory)
++ free (free_contents);
++ else
++ /* Cache the section contents for elf_link_input_bfd. */
++ elf_section_data (sec)->this_hdr.contents = contents;
++ free_contents = NULL;
++ }
++
++ if (sec->relax_count == 0)
++ {
++ *again = FALSE;
++ free (sec->relax);
++ sec->relax = NULL;
++ }
++ else
++ *again = TRUE;
++ return TRUE;
++
++ error_return:
++ if (free_relocs != NULL)
++ free (free_relocs);
++ if (free_contents != NULL)
++ free (free_contents);
++ if (sec->relax != NULL)
++ {
++ free (sec->relax);
++ sec->relax = NULL;
++ sec->relax_count = 0;
++ }
++ return FALSE;
++}
++
++/* Return the section that should be marked against GC for a given
++ relocation. */
++
++static asection *
++microblaze_elf_gc_mark_hook (asection *sec,
++ struct bfd_link_info * info,
++ Elf_Internal_Rela * rel,
++ struct elf_link_hash_entry * h,
++ Elf_Internal_Sym * sym)
++{
++ if (h != NULL)
++ switch (ELF64_R_TYPE (rel->r_info))
++ {
++ case R_MICROBLAZE_GNU_VTINHERIT:
++ case R_MICROBLAZE_GNU_VTENTRY:
++ return NULL;
++ }
++
++ return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
++}
++
++/* PIC support. */
++
++#define PLT_ENTRY_SIZE 16
++
++#define PLT_ENTRY_WORD_0 0xb0000000 /* "imm 0". */
++#define PLT_ENTRY_WORD_1 0xe9940000 /* "lwi r12,r20,0" - relocated to lwi r12,r20,func@GOT. */
++#define PLT_ENTRY_WORD_1_NOPIC 0xe9800000 /* "lwi r12,r0,0" - non-PIC object. */
++#define PLT_ENTRY_WORD_2 0x98186000 /* "brad r12". */
++#define PLT_ENTRY_WORD_3 0x80000000 /* "nop". */
++
++/* Create .got, .gotplt, and .rela.got sections in DYNOBJ, and set up
++ shortcuts to them in our hash table. */
++
++static bfd_boolean
++create_got_section (bfd *dynobj, struct bfd_link_info *info)
++{
++ struct elf64_mb_link_hash_table *htab;
++
++ if (! _bfd_elf_create_got_section (dynobj, info))
++ return FALSE;
++ htab = elf64_mb_hash_table (info);
++ if (htab == NULL)
++ return FALSE;
++
++ htab->sgot = bfd_get_linker_section (dynobj, ".got");
++ htab->sgotplt = bfd_get_linker_section (dynobj, ".got.plt");
++ if (!htab->sgot || !htab->sgotplt)
++ return FALSE;
++
++ if ((htab->srelgot = bfd_get_linker_section (dynobj, ".rela.got")) == NULL)
++ htab->srelgot = bfd_make_section_anyway (dynobj, ".rela.got");
++ if (htab->srelgot == NULL
++ || ! bfd_set_section_flags (htab->srelgot, SEC_ALLOC
++ | SEC_LOAD
++ | SEC_HAS_CONTENTS
++ | SEC_IN_MEMORY
++ | SEC_LINKER_CREATED
++ | SEC_READONLY)
++ || ! bfd_set_section_alignment (htab->srelgot, 2))
++ return FALSE;
++ return TRUE;
++}
++
++static bfd_boolean
++update_local_sym_info (bfd *abfd,
++ Elf_Internal_Shdr *symtab_hdr,
++ unsigned long r_symndx,
++ unsigned int tls_type)
++{
++ bfd_signed_vma *local_got_refcounts = elf_local_got_refcounts (abfd);
++ unsigned char *local_got_tls_masks;
++
++ if (local_got_refcounts == NULL)
++ {
++ bfd_size_type size = symtab_hdr->sh_info;
++
++ size *= (sizeof (*local_got_refcounts) + sizeof (*local_got_tls_masks));
++ local_got_refcounts = bfd_zalloc (abfd, size);
++ if (local_got_refcounts == NULL)
++ return FALSE;
++ elf_local_got_refcounts (abfd) = local_got_refcounts;
++ }
++
++ local_got_tls_masks =
++ (unsigned char *) (local_got_refcounts + symtab_hdr->sh_info);
++ local_got_tls_masks[r_symndx] |= tls_type;
++ local_got_refcounts[r_symndx] += 1;
++
++ return TRUE;
++}
++/* Look through the relocs for a section during the first phase. */
++
++static bfd_boolean
++microblaze_elf_check_relocs (bfd * abfd,
++ struct bfd_link_info * info,
++ asection * sec,
++ const Elf_Internal_Rela * relocs)
++{
++ Elf_Internal_Shdr * symtab_hdr;
++ struct elf_link_hash_entry ** sym_hashes;
++ struct elf_link_hash_entry ** sym_hashes_end;
++ const Elf_Internal_Rela * rel;
++ const Elf_Internal_Rela * rel_end;
++ struct elf64_mb_link_hash_table *htab;
++ asection *sreloc = NULL;
++
++ if (bfd_link_relocatable (info))
++ return TRUE;
++
++ htab = elf64_mb_hash_table (info);
++ if (htab == NULL)
++ return FALSE;
++
++ symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
++ sym_hashes = elf_sym_hashes (abfd);
++ sym_hashes_end = sym_hashes + symtab_hdr->sh_size / sizeof (Elf64_External_Sym);
++ if (!elf_bad_symtab (abfd))
++ sym_hashes_end -= symtab_hdr->sh_info;
++
++ rel_end = relocs + sec->reloc_count;
++
++ for (rel = relocs; rel < rel_end; rel++)
++ {
++ unsigned int r_type;
++ struct elf_link_hash_entry * h;
++ unsigned long r_symndx;
++ unsigned char tls_type = 0;
++
++ r_symndx = ELF64_R_SYM (rel->r_info);
++ r_type = ELF64_R_TYPE (rel->r_info);
++
++ if (r_symndx < symtab_hdr->sh_info)
++ h = NULL;
++ else
++ {
++ h = sym_hashes [r_symndx - symtab_hdr->sh_info];
++
++ /* PR15323, ref flags aren't set for references in the same
++ object. */
++ h->root.non_ir_ref_regular = 1;
++ }
++
++ switch (r_type)
++ {
++ /* This relocation describes the C++ object vtable hierarchy.
++ Reconstruct it for later use during GC. */
++ case R_MICROBLAZE_GNU_VTINHERIT:
++ if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
++ return FALSE;
++ break;
++
++ /* This relocation describes which C++ vtable entries are actually
++ used. Record for later use during GC. */
++ case R_MICROBLAZE_GNU_VTENTRY:
++ if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend))
++ return FALSE;
++ break;
++
++ /* This relocation requires .plt entry. */
++ case R_MICROBLAZE_PLT_64:
++ if (h != NULL)
++ {
++ h->needs_plt = 1;
++ h->plt.refcount += 1;
++ }
++ break;
++
++ /* This relocation requires .got entry. */
++ case R_MICROBLAZE_TLSGD:
++ tls_type |= (TLS_TLS | TLS_GD);
++ goto dogottls;
++ case R_MICROBLAZE_TLSLD:
++ tls_type |= (TLS_TLS | TLS_LD);
++ dogottls:
++ sec->has_tls_reloc = 1;
++ /* Fall through. */
++ case R_MICROBLAZE_GOT_64:
++ if (htab->sgot == NULL)
++ {
++ if (htab->elf.dynobj == NULL)
++ htab->elf.dynobj = abfd;
++ if (!create_got_section (htab->elf.dynobj, info))
++ return FALSE;
++ }
++ if (h != NULL)
++ {
++ h->got.refcount += 1;
++ elf64_mb_hash_entry (h)->tls_mask |= tls_type;
++ }
++ else
++ {
++ if (! update_local_sym_info(abfd, symtab_hdr, r_symndx, tls_type) )
++ return FALSE;
++ }
++ break;
++
++ case R_MICROBLAZE_64:
++ case R_MICROBLAZE_64_PCREL:
++ case R_MICROBLAZE_32:
++ {
++ if (h != NULL && !bfd_link_pic (info))
++ {
++ /* we may need a copy reloc. */
++ h->non_got_ref = 1;
++
++ /* we may also need a .plt entry. */
++ h->plt.refcount += 1;
++ if (ELF64_R_TYPE (rel->r_info) != R_MICROBLAZE_64_PCREL)
++ h->pointer_equality_needed = 1;
++ }
++
++
++ /* If we are creating a shared library, and this is a reloc
++ against a global symbol, or a non PC relative reloc
++ against a local symbol, then we need to copy the reloc
++ into the shared library. However, if we are linking with
++ -Bsymbolic, we do not need to copy a reloc against a
++ global symbol which is defined in an object we are
++ including in the link (i.e., DEF_REGULAR is set). At
++ this point we have not seen all the input files, so it is
++ possible that DEF_REGULAR is not set now but will be set
++ later (it is never cleared). In case of a weak definition,
++ DEF_REGULAR may be cleared later by a strong definition in
++ a shared library. We account for that possibility below by
++ storing information in the relocs_copied field of the hash
++ table entry. A similar situation occurs when creating
++ shared libraries and symbol visibility changes render the
++ symbol local.
++
++ If on the other hand, we are creating an executable, we
++ may need to keep relocations for symbols satisfied by a
++ dynamic library if we manage to avoid copy relocs for the
++ symbol. */
++
++ if ((bfd_link_pic (info)
++ && (sec->flags & SEC_ALLOC) != 0
++ && (r_type != R_MICROBLAZE_64_PCREL
++ || (h != NULL
++ && (! info->symbolic
++ || h->root.type == bfd_link_hash_defweak
++ || !h->def_regular))))
++ || (!bfd_link_pic (info)
++ && (sec->flags & SEC_ALLOC) != 0
++ && h != NULL
++ && (h->root.type == bfd_link_hash_defweak
++ || !h->def_regular)))
++ {
++ struct elf64_mb_dyn_relocs *p;
++ struct elf64_mb_dyn_relocs **head;
++
++ /* When creating a shared object, we must copy these
++ relocs into the output file. We create a reloc
++ section in dynobj and make room for the reloc. */
++
++ if (sreloc == NULL)
++ {
++ bfd *dynobj;
++
++ if (htab->elf.dynobj == NULL)
++ htab->elf.dynobj = abfd;
++ dynobj = htab->elf.dynobj;
++
++ sreloc = _bfd_elf_make_dynamic_reloc_section (sec, dynobj,
++ 2, abfd, 1);
++ if (sreloc == NULL)
++ return FALSE;
++ }
++
++ /* If this is a global symbol, we count the number of
++ relocations we need for this symbol. */
++ if (h != NULL)
++ head = &((struct elf64_mb_link_hash_entry *) h)->dyn_relocs;
++ else
++ {
++ /* Track dynamic relocs needed for local syms too.
++ We really need local syms available to do this
++ easily. Oh well. */
++
++ asection *s;
++ Elf_Internal_Sym *isym;
++ void *vpp;
++
++ isym = bfd_sym_from_r_symndx (&htab->sym_sec,
++ abfd, r_symndx);
++ if (isym == NULL)
++ return FALSE;
++
++ s = bfd_section_from_elf_index (abfd, isym->st_shndx);
++ if (s == NULL)
++ return FALSE;
++
++ vpp = &elf_section_data (s)->local_dynrel;
++ head = (struct elf64_mb_dyn_relocs **) vpp;
++ }
++
++ p = *head;
++ if (p == NULL || p->sec != sec)
++ {
++ bfd_size_type amt = sizeof *p;
++ p = ((struct elf64_mb_dyn_relocs *)
++ bfd_alloc (htab->elf.dynobj, amt));
++ if (p == NULL)
++ return FALSE;
++ p->next = *head;
++ *head = p;
++ p->sec = sec;
++ p->count = 0;
++ p->pc_count = 0;
++ }
++
++ p->count += 1;
++ if (r_type == R_MICROBLAZE_64_PCREL)
++ p->pc_count += 1;
++ }
++ }
++ break;
++ }
++ }
++
++ return TRUE;
++}
++
++static bfd_boolean
++microblaze_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
++{
++ struct elf64_mb_link_hash_table *htab;
++
++ htab = elf64_mb_hash_table (info);
++ if (htab == NULL)
++ return FALSE;
++
++ if (!htab->sgot && !create_got_section (dynobj, info))
++ return FALSE;
++
++ if (!_bfd_elf_create_dynamic_sections (dynobj, info))
++ return FALSE;
++
++ htab->splt = bfd_get_linker_section (dynobj, ".plt");
++ htab->srelplt = bfd_get_linker_section (dynobj, ".rela.plt");
++ htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
++ if (!bfd_link_pic (info))
++ htab->srelbss = bfd_get_linker_section (dynobj, ".rela.bss");
++
++ if (!htab->splt || !htab->srelplt || !htab->sdynbss
++ || (!bfd_link_pic (info) && !htab->srelbss))
++ abort ();
++
++ return TRUE;
++}
++
++/* Copy the extra info we tack onto an elf_link_hash_entry. */
++
++static void
++microblaze_elf_copy_indirect_symbol (struct bfd_link_info *info,
++ struct elf_link_hash_entry *dir,
++ struct elf_link_hash_entry *ind)
++{
++ struct elf64_mb_link_hash_entry *edir, *eind;
++
++ edir = (struct elf64_mb_link_hash_entry *) dir;
++ eind = (struct elf64_mb_link_hash_entry *) ind;
++
++ if (eind->dyn_relocs != NULL)
++ {
++ if (edir->dyn_relocs != NULL)
++ {
++ struct elf64_mb_dyn_relocs **pp;
++ struct elf64_mb_dyn_relocs *p;
++
++ if (ind->root.type == bfd_link_hash_indirect)
++ abort ();
++
++ /* Add reloc counts against the weak sym to the strong sym
++ list. Merge any entries against the same section. */
++ for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
++ {
++ struct elf64_mb_dyn_relocs *q;
++
++ for (q = edir->dyn_relocs; q != NULL; q = q->next)
++ if (q->sec == p->sec)
++ {
++ q->pc_count += p->pc_count;
++ q->count += p->count;
++ *pp = p->next;
++ break;
++ }
++ if (q == NULL)
++ pp = &p->next;
++ }
++ *pp = edir->dyn_relocs;
++ }
++
++ edir->dyn_relocs = eind->dyn_relocs;
++ eind->dyn_relocs = NULL;
++ }
++
++ edir->tls_mask |= eind->tls_mask;
++
++ _bfd_elf_link_hash_copy_indirect (info, dir, ind);
++}
++
++static bfd_boolean
++microblaze_elf_adjust_dynamic_symbol (struct bfd_link_info *info,
++ struct elf_link_hash_entry *h)
++{
++ struct elf64_mb_link_hash_table *htab;
++ struct elf64_mb_link_hash_entry * eh;
++ struct elf64_mb_dyn_relocs *p;
++ asection *sdynbss, *s;
++ unsigned int power_of_two;
++ bfd *dynobj;
++
++ htab = elf64_mb_hash_table (info);
++ if (htab == NULL)
++ return FALSE;
++
++ /* If this is a function, put it in the procedure linkage table. We
++ will fill in the contents of the procedure linkage table later,
++ when we know the address of the .got section. */
++ if (h->type == STT_FUNC
++ || h->needs_plt)
++ {
++ if (h->plt.refcount <= 0
++ || SYMBOL_CALLS_LOCAL (info, h)
++ || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
++ && h->root.type == bfd_link_hash_undefweak))
++ {
++ /* This case can occur if we saw a PLT reloc in an input
++ file, but the symbol was never referred to by a dynamic
++ object, or if all references were garbage collected. In
++ such a case, we don't actually need to build a procedure
++ linkage table, and we can just do a PC32 reloc instead. */
++ h->plt.offset = (bfd_vma) -1;
++ h->needs_plt = 0;
++ }
++
++ return TRUE;
++ }
++ else
++ /* It's possible that we incorrectly decided a .plt reloc was
++ needed for an R_MICROBLAZE_64_PCREL reloc to a non-function sym in
++ check_relocs. We can't decide accurately between function and
++ non-function syms in check-relocs; Objects loaded later in
++ the link may change h->type. So fix it now. */
++ h->plt.offset = (bfd_vma) -1;
++
++ /* If this is a weak symbol, and there is a real definition, the
++ processor independent code will have arranged for us to see the
++ real definition first, and we can just use the same value. */
++ if (h->is_weakalias)
++ {
++ struct elf_link_hash_entry *def = weakdef (h);
++ BFD_ASSERT (def->root.type == bfd_link_hash_defined);
++ h->root.u.def.section = def->root.u.def.section;
++ h->root.u.def.value = def->root.u.def.value;
++ return TRUE;
++ }
++
++ /* This is a reference to a symbol defined by a dynamic object which
++ is not a function. */
++
++ /* If we are creating a shared library, we must presume that the
++ only references to the symbol are via the global offset table.
++ For such cases we need not do anything here; the relocations will
++ be handled correctly by relocate_section. */
++ if (bfd_link_pic (info))
++ return TRUE;
++
++ /* If there are no references to this symbol that do not use the
++ GOT, we don't need to generate a copy reloc. */
++ if (!h->non_got_ref)
++ return TRUE;
++
++ /* If -z nocopyreloc was given, we won't generate them either. */
++ if (info->nocopyreloc)
++ {
++ h->non_got_ref = 0;
++ return TRUE;
++ }
++
++ eh = (struct elf64_mb_link_hash_entry *) h;
++ for (p = eh->dyn_relocs; p != NULL; p = p->next)
++ {
++ s = p->sec->output_section;
++ if (s != NULL && (s->flags & SEC_READONLY) != 0)
++ break;
++ }
++
++ /* If we didn't find any dynamic relocs in read-only sections, then
++ we'll be keeping the dynamic relocs and avoiding the copy reloc. */
++ if (p == NULL)
++ {
++ h->non_got_ref = 0;
++ return TRUE;
++ }
++
++ /* We must allocate the symbol in our .dynbss section, which will
++ become part of the .bss section of the executable. There will be
++ an entry for this symbol in the .dynsym section. The dynamic
++ object will contain position independent code, so all references
++ from the dynamic object to this symbol will go through the global
++ offset table. The dynamic linker will use the .dynsym entry to
++ determine the address it must put in the global offset table, so
++ both the dynamic object and the regular object will refer to the
++ same memory location for the variable. */
++
++ /* We must generate a R_MICROBLAZE_COPY reloc to tell the dynamic linker
++ to copy the initial value out of the dynamic object and into the
++ runtime process image. */
++ dynobj = elf_hash_table (info)->dynobj;
++ BFD_ASSERT (dynobj != NULL);
++ if ((h->root.u.def.section->flags & SEC_ALLOC) != 0)
++ {
++ htab->srelbss->size += sizeof (Elf64_External_Rela);
++ h->needs_copy = 1;
++ }
++
++ /* We need to figure out the alignment required for this symbol. I
++ have no idea how ELF linkers handle this. */
++ power_of_two = bfd_log2 (h->size);
++ if (power_of_two > 3)
++ power_of_two = 3;
++
++ sdynbss = htab->sdynbss;
++ /* Apply the required alignment. */
++ sdynbss->size = BFD_ALIGN (sdynbss->size, (bfd_size_type) (1 << power_of_two));
++ if (power_of_two > bfd_section_alignment (sdynbss))
++ {
++ if (! bfd_set_section_alignment (sdynbss, power_of_two))
++ return FALSE;
++ }
++
++ /* Define the symbol as being at this point in the section. */
++ h->root.u.def.section = sdynbss;
++ h->root.u.def.value = sdynbss->size;
++
++ /* Increment the section size to make room for the symbol. */
++ sdynbss->size += h->size;
++ return TRUE;
++}
++
++/* Allocate space in .plt, .got and associated reloc sections for
++ dynamic relocs. */
++
++static bfd_boolean
++allocate_dynrelocs (struct elf_link_hash_entry *h, void * dat)
++{
++ struct bfd_link_info *info;
++ struct elf64_mb_link_hash_table *htab;
++ struct elf64_mb_link_hash_entry *eh;
++ struct elf64_mb_dyn_relocs *p;
++
++ if (h->root.type == bfd_link_hash_indirect)
++ return TRUE;
++
++ info = (struct bfd_link_info *) dat;
++ htab = elf64_mb_hash_table (info);
++ if (htab == NULL)
++ return FALSE;
++
++ if (htab->elf.dynamic_sections_created
++ && h->plt.refcount > 0)
++ {
++ /* Make sure this symbol is output as a dynamic symbol.
++ Undefined weak syms won't yet be marked as dynamic. */
++ if (h->dynindx == -1
++ && !h->forced_local)
++ {
++ if (! bfd_elf_link_record_dynamic_symbol (info, h))
++ return FALSE;
++ }
++
++ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, bfd_link_pic (info), h))
++ {
++ asection *s = htab->splt;
++
++ /* The first entry in .plt is reserved. */
++ if (s->size == 0)
++ s->size = PLT_ENTRY_SIZE;
++
++ h->plt.offset = s->size;
++
++ /* If this symbol is not defined in a regular file, and we are
++ not generating a shared library, then set the symbol to this
++ location in the .plt. This is required to make function
++ pointers compare as equal between the normal executable and
++ the shared library. */
++ if (! bfd_link_pic (info)
++ && !h->def_regular)
++ {
++ h->root.u.def.section = s;
++ h->root.u.def.value = h->plt.offset;
++ }
++
++ /* Make room for this entry. */
++ s->size += PLT_ENTRY_SIZE;
++
++ /* We also need to make an entry in the .got.plt section, which
++ will be placed in the .got section by the linker script. */
++ htab->sgotplt->size += 4;
++
++ /* We also need to make an entry in the .rel.plt section. */
++ htab->srelplt->size += sizeof (Elf64_External_Rela);
++ }
++ else
++ {
++ h->plt.offset = (bfd_vma) -1;
++ h->needs_plt = 0;
++ }
++ }
++ else
++ {
++ h->plt.offset = (bfd_vma) -1;
++ h->needs_plt = 0;
++ }
++
++ eh = (struct elf64_mb_link_hash_entry *) h;
++ if (h->got.refcount > 0)
++ {
++ unsigned int need;
++ asection *s;
++
++ /* Make sure this symbol is output as a dynamic symbol.
++ Undefined weak syms won't yet be marked as dynamic. */
++ if (h->dynindx == -1
++ && !h->forced_local)
++ {
++ if (! bfd_elf_link_record_dynamic_symbol (info, h))
++ return FALSE;
++ }
++
++ need = 0;
++ if ((eh->tls_mask & TLS_TLS) != 0)
++ {
++ /* Handle TLS Symbol */
++ if ((eh->tls_mask & TLS_LD) != 0)
++ {
++ if (!eh->elf.def_dynamic)
++ /* We'll just use htab->tlsld_got.offset. This should
++ always be the case. It's a little odd if we have
++ a local dynamic reloc against a non-local symbol. */
++ htab->tlsld_got.refcount += 1;
++ else
++ need += 8;
++ }
++ if ((eh->tls_mask & TLS_GD) != 0)
++ need += 8;
++ }
++ else
++ {
++ /* Regular (non-TLS) symbol */
++ need += 4;
++ }
++ if (need == 0)
++ {
++ h->got.offset = (bfd_vma) -1;
++ }
++ else
++ {
++ s = htab->sgot;
++ h->got.offset = s->size;
++ s->size += need;
++ htab->srelgot->size += need * (sizeof (Elf64_External_Rela) / 4);
++ }
++ }
++ else
++ h->got.offset = (bfd_vma) -1;
++
++ if (eh->dyn_relocs == NULL)
++ return TRUE;
++
++ /* In the shared -Bsymbolic case, discard space allocated for
++ dynamic pc-relative relocs against symbols which turn out to be
++ defined in regular objects. For the normal shared case, discard
++ space for pc-relative relocs that have become local due to symbol
++ visibility changes. */
++
++ if (bfd_link_pic (info))
++ {
++ if (h->def_regular
++ && (h->forced_local
++ || info->symbolic))
++ {
++ struct elf64_mb_dyn_relocs **pp;
++
++ for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
++ {
++ p->count -= p->pc_count;
++ p->pc_count = 0;
++ if (p->count == 0)
++ *pp = p->next;
++ else
++ pp = &p->next;
++ }
++ }
++ }
++ else
++ {
++ /* For the non-shared case, discard space for relocs against
++ symbols which turn out to need copy relocs or are not
++ dynamic. */
++
++ if (!h->non_got_ref
++ && ((h->def_dynamic
++ && !h->def_regular)
++ || (htab->elf.dynamic_sections_created
++ && (h->root.type == bfd_link_hash_undefweak
++ || h->root.type == bfd_link_hash_undefined))))
++ {
++ /* Make sure this symbol is output as a dynamic symbol.
++ Undefined weak syms won't yet be marked as dynamic. */
++ if (h->dynindx == -1
++ && !h->forced_local)
++ {
++ if (! bfd_elf_link_record_dynamic_symbol (info, h))
++ return FALSE;
++ }
++
++ /* If that succeeded, we know we'll be keeping all the
++ relocs. */
++ if (h->dynindx != -1)
++ goto keep;
++ }
++
++ eh->dyn_relocs = NULL;
++
++ keep: ;
++ }
++
++ /* Finally, allocate space. */
++ for (p = eh->dyn_relocs; p != NULL; p = p->next)
++ {
++ asection *sreloc = elf_section_data (p->sec)->sreloc;
++ sreloc->size += p->count * sizeof (Elf64_External_Rela);
++ }
++
++ return TRUE;
++}
++
++/* Set the sizes of the dynamic sections. */
++
++static bfd_boolean
++microblaze_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
++ struct bfd_link_info *info)
++{
++ struct elf64_mb_link_hash_table *htab;
++ bfd *dynobj;
++ asection *s;
++ bfd *ibfd;
++
++ htab = elf64_mb_hash_table (info);
++ if (htab == NULL)
++ return FALSE;
++
++ dynobj = htab->elf.dynobj;
++ BFD_ASSERT (dynobj != NULL);
++
++ /* Set up .got offsets for local syms, and space for local dynamic
++ relocs. */
++ for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
++ {
++ bfd_signed_vma *local_got;
++ bfd_signed_vma *end_local_got;
++ bfd_size_type locsymcount;
++ Elf_Internal_Shdr *symtab_hdr;
++ unsigned char *lgot_masks;
++ asection *srel;
++
++ if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour)
++ continue;
++
++ for (s = ibfd->sections; s != NULL; s = s->next)
++ {
++ struct elf64_mb_dyn_relocs *p;
++
++ for (p = ((struct elf64_mb_dyn_relocs *)
++ elf_section_data (s)->local_dynrel);
++ p != NULL;
++ p = p->next)
++ {
++ if (!bfd_is_abs_section (p->sec)
++ && bfd_is_abs_section (p->sec->output_section))
++ {
++ /* Input section has been discarded, either because
++ it is a copy of a linkonce section or due to
++ linker script /DISCARD/, so we'll be discarding
++ the relocs too. */
++ }
++ else if (p->count != 0)
++ {
++ srel = elf_section_data (p->sec)->sreloc;
++ srel->size += p->count * sizeof (Elf64_External_Rela);
++ if ((p->sec->output_section->flags & SEC_READONLY) != 0)
++ info->flags |= DF_TEXTREL;
++ }
++ }
++ }
++
++ local_got = elf_local_got_refcounts (ibfd);
++ if (!local_got)
++ continue;
++
++ symtab_hdr = &elf_tdata (ibfd)->symtab_hdr;
++ locsymcount = symtab_hdr->sh_info;
++ end_local_got = local_got + locsymcount;
++ lgot_masks = (unsigned char *) end_local_got;
++ s = htab->sgot;
++ srel = htab->srelgot;
++
++ for (; local_got < end_local_got; ++local_got, ++lgot_masks)
++ {
++ if (*local_got > 0)
++ {
++ unsigned int need = 0;
++ if ((*lgot_masks & TLS_TLS) != 0)
++ {
++ if ((*lgot_masks & TLS_GD) != 0)
++ need += 8;
++ if ((*lgot_masks & TLS_LD) != 0)
++ htab->tlsld_got.refcount += 1;
++ }
++ else
++ need += 4;
++
++ if (need == 0)
++ {
++ *local_got = (bfd_vma) -1;
++ }
++ else
++ {
++ *local_got = s->size;
++ s->size += need;
++ if (bfd_link_pic (info))
++ srel->size += need * (sizeof (Elf64_External_Rela) / 4);
++ }
++ }
++ else
++ *local_got = (bfd_vma) -1;
++ }
++ }
++
++ /* Allocate global sym .plt and .got entries, and space for global
++ sym dynamic relocs. */
++ elf_link_hash_traverse (elf_hash_table (info), allocate_dynrelocs, info);
++
++ if (htab->tlsld_got.refcount > 0)
++ {
++ htab->tlsld_got.offset = htab->sgot->size;
++ htab->sgot->size += 8;
++ if (bfd_link_pic (info))
++ htab->srelgot->size += sizeof (Elf64_External_Rela);
++ }
++ else
++ htab->tlsld_got.offset = (bfd_vma) -1;
++
++ if (elf_hash_table (info)->dynamic_sections_created)
++ {
++ /* Make space for the trailing nop in .plt. */
++ if (htab->splt->size > 0)
++ htab->splt->size += 4;
++ }
++
++ /* The check_relocs and adjust_dynamic_symbol entry points have
++ determined the sizes of the various dynamic sections. Allocate
++ memory for them. */
++ for (s = dynobj->sections; s != NULL; s = s->next)
++ {
++ const char *name;
++ bfd_boolean strip = FALSE;
++
++ if ((s->flags & SEC_LINKER_CREATED) == 0)
++ continue;
++
++ /* It's OK to base decisions on the section name, because none
++ of the dynobj section names depend upon the input files. */
++ name = bfd_section_name (s);
++
++ if (strncmp (name, ".rela", 5) == 0)
++ {
++ if (s->size == 0)
++ {
++ /* If we don't need this section, strip it from the
++ output file. This is to handle .rela.bss and
++ .rela.plt. We must create it in
++ create_dynamic_sections, because it must be created
++ before the linker maps input sections to output
++ sections. The linker does that before
++ adjust_dynamic_symbol is called, and it is that
++ function which decides whether anything needs to go
++ into these sections. */
++ strip = TRUE;
++ }
++ else
++ {
++ /* We use the reloc_count field as a counter if we need
++ to copy relocs into the output file. */
++ s->reloc_count = 0;
++ }
++ }
++ else if (s != htab->splt && s != htab->sgot && s != htab->sgotplt)
++ {
++ /* It's not one of our sections, so don't allocate space. */
++ continue;
++ }
++
++ if (strip)
++ {
++ s->flags |= SEC_EXCLUDE;
++ continue;
++ }
++
++ /* Allocate memory for the section contents. */
++ /* FIXME: This should be a call to bfd_alloc not bfd_zalloc.
++ Unused entries should be reclaimed before the section's contents
++ are written out, but at the moment this does not happen. Thus in
++ order to prevent writing out garbage, we initialise the section's
++ contents to zero. */
++ s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size);
++ if (s->contents == NULL && s->size != 0)
++ return FALSE;
++ }
++
++ if (elf_hash_table (info)->dynamic_sections_created)
++ {
++ /* Add some entries to the .dynamic section. We fill in the
++ values later, in microblaze_elf_finish_dynamic_sections, but we
++ must add the entries now so that we get the correct size for
++ the .dynamic section. The DT_DEBUG entry is filled in by the
++ dynamic linker and used by the debugger. */
++#define add_dynamic_entry(TAG, VAL) \
++ _bfd_elf_add_dynamic_entry (info, TAG, VAL)
++
++ if (bfd_link_executable (info))
++ {
++ if (!add_dynamic_entry (DT_DEBUG, 0))
++ return FALSE;
++ }
++
++ if (!add_dynamic_entry (DT_RELA, 0)
++ || !add_dynamic_entry (DT_RELASZ, 0)
++ || !add_dynamic_entry (DT_RELAENT, sizeof (Elf64_External_Rela)))
++ return FALSE;
++
++ if (htab->splt->size != 0)
++ {
++ if (!add_dynamic_entry (DT_PLTGOT, 0)
++ || !add_dynamic_entry (DT_PLTRELSZ, 0)
++ || !add_dynamic_entry (DT_PLTREL, DT_RELA)
++ || !add_dynamic_entry (DT_JMPREL, 0)
++ || !add_dynamic_entry (DT_BIND_NOW, 1))
++ return FALSE;
++ }
++
++ if (info->flags & DF_TEXTREL)
++ {
++ if (!add_dynamic_entry (DT_TEXTREL, 0))
++ return FALSE;
++ }
++ }
++#undef add_dynamic_entry
++ return TRUE;
++}
++
++/* Finish up dynamic symbol handling. We set the contents of various
++ dynamic sections here. */
++
++static bfd_boolean
++microblaze_elf_finish_dynamic_symbol (bfd *output_bfd,
++ struct bfd_link_info *info,
++ struct elf_link_hash_entry *h,
++ Elf_Internal_Sym *sym)
++{
++ struct elf64_mb_link_hash_table *htab;
++ struct elf64_mb_link_hash_entry *eh = elf64_mb_hash_entry(h);
++
++ htab = elf64_mb_hash_table (info);
++ if (htab == NULL)
++ return FALSE;
++
++ if (h->plt.offset != (bfd_vma) -1)
++ {
++ asection *splt;
++ asection *srela;
++ asection *sgotplt;
++ Elf_Internal_Rela rela;
++ bfd_byte *loc;
++ bfd_vma plt_index;
++ bfd_vma got_offset;
++ bfd_vma got_addr;
++
++ /* This symbol has an entry in the procedure linkage table. Set
++ it up. */
++ BFD_ASSERT (h->dynindx != -1);
++
++ splt = htab->splt;
++ srela = htab->srelplt;
++ sgotplt = htab->sgotplt;
++ BFD_ASSERT (splt != NULL && srela != NULL && sgotplt != NULL);
++
++ plt_index = h->plt.offset / PLT_ENTRY_SIZE - 1; /* first entry reserved. */
++ got_offset = (plt_index + 3) * 4; /* 3 reserved ??? */
++ got_addr = got_offset;
++
++ /* For non-PIC objects we need absolute address of the GOT entry. */
++ if (!bfd_link_pic (info))
++ got_addr += htab->sgotplt->output_section->vma + sgotplt->output_offset;
++
++ /* Fill in the entry in the procedure linkage table. */
++ bfd_put_32 (output_bfd, PLT_ENTRY_WORD_0 + ((got_addr >> 16) & 0xffff),
++ splt->contents + h->plt.offset);
++ if (bfd_link_pic (info))
++ bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1 + (got_addr & 0xffff),
++ splt->contents + h->plt.offset + 4);
++ else
++ bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1_NOPIC + (got_addr & 0xffff),
++ splt->contents + h->plt.offset + 4);
++ bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_2,
++ splt->contents + h->plt.offset + 8);
++ bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_3,
++ splt->contents + h->plt.offset + 12);
++
++ /* Any additions to the .got section??? */
++ /* bfd_put_32 (output_bfd,
++ splt->output_section->vma + splt->output_offset + h->plt.offset + 4,
++ sgotplt->contents + got_offset); */
++
++ /* Fill in the entry in the .rela.plt section. */
++ rela.r_offset = (sgotplt->output_section->vma
++ + sgotplt->output_offset
++ + got_offset);
++ rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_JUMP_SLOT);
++ rela.r_addend = 0;
++ loc = srela->contents;
++ loc += plt_index * sizeof (Elf64_External_Rela);
++ bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
++
++ if (!h->def_regular)
++ {
++ /* Mark the symbol as undefined, rather than as defined in
++ the .plt section. Zero the value. */
++ sym->st_shndx = SHN_UNDEF;
++ sym->st_value = 0;
++ }
++ }
++
++ /* h->got.refcount to be checked ? */
++ if (h->got.offset != (bfd_vma) -1 &&
++ ! ((h->got.offset & 1) ||
++ IS_TLS_LD(eh->tls_mask) || IS_TLS_GD(eh->tls_mask)))
++ {
++ asection *sgot;
++ asection *srela;
++ bfd_vma offset;
++
++ /* This symbol has an entry in the global offset table. Set it
++ up. */
++
++ sgot = htab->sgot;
++ srela = htab->srelgot;
++ BFD_ASSERT (sgot != NULL && srela != NULL);
++
++ offset = (sgot->output_section->vma + sgot->output_offset
++ + (h->got.offset &~ (bfd_vma) 1));
++
++ /* If this is a -Bsymbolic link, and the symbol is defined
++ locally, we just want to emit a RELATIVE reloc. Likewise if
++ the symbol was forced to be local because of a version file.
++ The entry in the global offset table will already have been
++ initialized in the relocate_section function. */
++ if (bfd_link_pic (info)
++ && ((info->symbolic && h->def_regular)
++ || h->dynindx == -1))
++ {
++ asection *sec = h->root.u.def.section;
++ microblaze_elf_output_dynamic_relocation (output_bfd,
++ srela, srela->reloc_count++,
++ /* symindex= */ 0,
++ R_MICROBLAZE_REL, offset,
++ h->root.u.def.value
++ + sec->output_section->vma
++ + sec->output_offset);
++ }
++ else
++ {
++ microblaze_elf_output_dynamic_relocation (output_bfd,
++ srela, srela->reloc_count++,
++ h->dynindx,
++ R_MICROBLAZE_GLOB_DAT,
++ offset, 0);
++ }
++
++ bfd_put_32 (output_bfd, (bfd_vma) 0,
++ sgot->contents + (h->got.offset &~ (bfd_vma) 1));
++ }
++
++ if (h->needs_copy)
++ {
++ asection *s;
++ Elf_Internal_Rela rela;
++ bfd_byte *loc;
++
++ /* This symbols needs a copy reloc. Set it up. */
++
++ BFD_ASSERT (h->dynindx != -1);
++
++ s = bfd_get_linker_section (htab->elf.dynobj, ".rela.bss");
++ BFD_ASSERT (s != NULL);
++
++ rela.r_offset = (h->root.u.def.value
++ + h->root.u.def.section->output_section->vma
++ + h->root.u.def.section->output_offset);
++ rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_COPY);
++ rela.r_addend = 0;
++ loc = s->contents + s->reloc_count++ * sizeof (Elf64_External_Rela);
++ bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
++ }
++
++ /* Mark some specially defined symbols as absolute. */
++ if (h == htab->elf.hdynamic
++ || h == htab->elf.hgot
++ || h == htab->elf.hplt)
++ sym->st_shndx = SHN_ABS;
++
++ return TRUE;
++}
++
++
++/* Finish up the dynamic sections. */
++
++static bfd_boolean
++microblaze_elf_finish_dynamic_sections (bfd *output_bfd,
++ struct bfd_link_info *info)
++{
++ bfd *dynobj;
++ asection *sdyn, *sgot;
++ struct elf64_mb_link_hash_table *htab;
++
++ htab = elf64_mb_hash_table (info);
++ if (htab == NULL)
++ return FALSE;
++
++ dynobj = htab->elf.dynobj;
++
++ sdyn = bfd_get_linker_section (dynobj, ".dynamic");
++
++ if (htab->elf.dynamic_sections_created)
++ {
++ asection *splt;
++ Elf64_External_Dyn *dyncon, *dynconend;
++
++ splt = bfd_get_linker_section (dynobj, ".plt");
++ BFD_ASSERT (splt != NULL && sdyn != NULL);
++
++ dyncon = (Elf64_External_Dyn *) sdyn->contents;
++ dynconend = (Elf64_External_Dyn *) (sdyn->contents + sdyn->size);
++ for (; dyncon < dynconend; dyncon++)
++ {
++ Elf_Internal_Dyn dyn;
++ const char *name;
++ bfd_boolean size;
++
++ bfd_elf64_swap_dyn_in (dynobj, dyncon, &dyn);
++
++ switch (dyn.d_tag)
++ {
++ case DT_PLTGOT: name = ".got.plt"; size = FALSE; break;
++ case DT_PLTRELSZ: name = ".rela.plt"; size = TRUE; break;
++ case DT_JMPREL: name = ".rela.plt"; size = FALSE; break;
++ case DT_RELA: name = ".rela.dyn"; size = FALSE; break;
++ case DT_RELASZ: name = ".rela.dyn"; size = TRUE; break;
++ default: name = NULL; size = FALSE; break;
++ }
++
++ if (name != NULL)
++ {
++ asection *s;
++
++ s = bfd_get_section_by_name (output_bfd, name);
++ if (s == NULL)
++ dyn.d_un.d_val = 0;
++ else
++ {
++ if (! size)
++ dyn.d_un.d_ptr = s->vma;
++ else
++ dyn.d_un.d_val = s->size;
++ }
++ bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon);
++ }
++ }
++
++ /* Clear the first entry in the procedure linkage table,
++ and put a nop in the last four bytes. */
++ if (splt->size > 0)
++ {
++ memset (splt->contents, 0, PLT_ENTRY_SIZE);
++ bfd_put_32 (output_bfd, (bfd_vma) 0x80000000 /* nop. */,
++ splt->contents + splt->size - 4);
++ }
++
++ elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
++ }
++
++ /* Set the first entry in the global offset table to the address of
++ the dynamic section. */
++ sgot = bfd_get_linker_section (dynobj, ".got.plt");
++ if (sgot && sgot->size > 0)
++ {
++ if (sdyn == NULL)
++ bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
++ else
++ bfd_put_32 (output_bfd,
++ sdyn->output_section->vma + sdyn->output_offset,
++ sgot->contents);
++ elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
++ }
++
++ if (htab->sgot && htab->sgot->size > 0)
++ elf_section_data (htab->sgot->output_section)->this_hdr.sh_entsize = 4;
++
++ return TRUE;
++}
++
++/* Hook called by the linker routine which adds symbols from an object
++ file. We use it to put .comm items in .sbss, and not .bss. */
++
++static bfd_boolean
++microblaze_elf_add_symbol_hook (bfd *abfd,
++ struct bfd_link_info *info,
++ Elf_Internal_Sym *sym,
++ const char **namep ATTRIBUTE_UNUSED,
++ flagword *flagsp ATTRIBUTE_UNUSED,
++ asection **secp,
++ bfd_vma *valp)
++{
++ if (sym->st_shndx == SHN_COMMON
++ && !bfd_link_relocatable (info)
++ && sym->st_size <= elf_gp_size (abfd))
++ {
++ /* Common symbols less than or equal to -G nn bytes are automatically
++ put into .sbss. */
++ *secp = bfd_make_section_old_way (abfd, ".sbss");
++ if (*secp == NULL
++ || ! bfd_set_section_flags (*secp, SEC_IS_COMMON))
++ return FALSE;
++
++ *valp = sym->st_size;
++ }
++
++ return TRUE;
++}
++
++#define TARGET_LITTLE_SYM microblaze_elf64_le_vec
++#define TARGET_LITTLE_NAME "elf64-microblazeel"
++
++#define TARGET_BIG_SYM microblaze_elf64_vec
++#define TARGET_BIG_NAME "elf64-microblaze"
++
++#define ELF_ARCH bfd_arch_microblaze
++#define ELF_TARGET_ID MICROBLAZE_ELF_DATA
++#define ELF_MACHINE_CODE EM_MICROBLAZE
++#define ELF_MACHINE_ALT1 EM_MICROBLAZE_OLD
++#define ELF_MAXPAGESIZE 0x1000
++#define elf_info_to_howto microblaze_elf_info_to_howto
++#define elf_info_to_howto_rel NULL
++
++#define bfd_elf64_bfd_reloc_type_lookup microblaze_elf_reloc_type_lookup
++#define bfd_elf64_bfd_is_local_label_name microblaze_elf_is_local_label_name
++#define elf_backend_relocate_section microblaze_elf_relocate_section
++#define bfd_elf64_bfd_relax_section microblaze_elf_relax_section
++#define bfd_elf64_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match
++#define bfd_elf64_bfd_reloc_name_lookup microblaze_elf_reloc_name_lookup
++
++#define elf_backend_gc_mark_hook microblaze_elf_gc_mark_hook
++#define elf_backend_check_relocs microblaze_elf_check_relocs
++#define elf_backend_copy_indirect_symbol microblaze_elf_copy_indirect_symbol
++#define bfd_elf64_bfd_link_hash_table_create microblaze_elf_link_hash_table_create
++#define elf_backend_can_gc_sections 1
++#define elf_backend_can_refcount 1
++#define elf_backend_want_got_plt 1
++#define elf_backend_plt_readonly 1
++#define elf_backend_got_header_size 12
++#define elf_backend_rela_normal 1
++
++#define elf_backend_adjust_dynamic_symbol microblaze_elf_adjust_dynamic_symbol
++#define elf_backend_create_dynamic_sections microblaze_elf_create_dynamic_sections
++#define elf_backend_finish_dynamic_sections microblaze_elf_finish_dynamic_sections
++#define elf_backend_finish_dynamic_symbol microblaze_elf_finish_dynamic_symbol
++#define elf_backend_size_dynamic_sections microblaze_elf_size_dynamic_sections
++#define elf_backend_add_symbol_hook microblaze_elf_add_symbol_hook
++
++#include "elf64-target.h"
+diff --git a/bfd/targets.c b/bfd/targets.c
+index fb0c669e7f7..97b0e473e16 100644
+--- a/bfd/targets.c
++++ b/bfd/targets.c
+@@ -779,6 +779,8 @@ extern const bfd_target mep_elf32_le_vec;
+ extern const bfd_target metag_elf32_vec;
+ extern const bfd_target microblaze_elf32_vec;
+ extern const bfd_target microblaze_elf32_le_vec;
++extern const bfd_target microblaze_elf64_vec;
++extern const bfd_target microblaze_elf64_le_vec;
+ extern const bfd_target mips_ecoff_be_vec;
+ extern const bfd_target mips_ecoff_le_vec;
+ extern const bfd_target mips_ecoff_bele_vec;
+@@ -1150,6 +1152,10 @@ static const bfd_target * const _bfd_target_vector[] =
+
+ &metag_elf32_vec,
+
++#ifdef BFD64
++ µblaze_elf64_vec,
++ µblaze_elf64_le_vec,
++#endif
+ µblaze_elf32_vec,
+
+ &mips_ecoff_be_vec,
+diff --git a/include/elf/common.h b/include/elf/common.h
+index 75c4fb7e9d7..1584e1c87d0 100644
+--- a/include/elf/common.h
++++ b/include/elf/common.h
+@@ -339,6 +339,7 @@
+ #define EM_RISCV 243 /* RISC-V */
+ #define EM_LANAI 244 /* Lanai 32-bit processor. */
+ #define EM_BPF 247 /* Linux BPF – in-kernel virtual machine. */
++#define EM_MB_64 248 /* Xilinx MicroBlaze 32-bit RISC soft processor core */
+ #define EM_NFP 250 /* Netronome Flow Processor. */
+ #define EM_CSKY 252 /* C-SKY processor family. */
+
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index 356f1da22ed..437f536e96a 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -33,6 +33,7 @@
+ #define get_field_r1(buf, instr) get_field (buf, instr, RA_MASK, RA_LOW)
+ #define get_field_r2(buf, instr) get_field (buf, instr, RB_MASK, RB_LOW)
+ #define get_int_field_imm(instr) ((instr & IMM_MASK) >> IMM_LOW)
++#define get_int_field_imml(instr) ((instr & IMML_MASK) >> IMM_LOW)
+ #define get_int_field_r1(instr) ((instr & RA_MASK) >> RA_LOW)
+
+ #define NUM_STRBUFS 3
+@@ -73,11 +74,20 @@ get_field_imm (struct string_buf *buf, long instr)
+ }
+
+ static char *
+-get_field_imm5 (struct string_buf *buf, long instr)
++get_field_imml (struct string_buf *buf, long instr)
+ {
+ char *p = strbuf (buf);
+
+- sprintf (p, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW));
++ sprintf (p, "%d", (short)((instr & IMML_MASK) >> IMM_LOW));
++ return p;
++}
++
++static char *
++get_field_imms (struct string_buf *buf, long instr)
++{
++ char *p = strbuf (buf);
++
++ sprintf (p, "%d", (short)((instr & IMM6_MASK) >> IMM_LOW));
+ return p;
+ }
+
+@@ -91,14 +101,14 @@ get_field_imm5_mbar (struct string_buf *buf, long instr)
+ }
+
+ static char *
+-get_field_imm5width (struct string_buf *buf, long instr)
++get_field_immw (struct string_buf *buf, long instr)
+ {
+ char *p = strbuf (buf);
+
+ if (instr & 0x00004000)
+- sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
++ sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
+ else
+- sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
++ sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM6_MASK) >> IMM_LOW) + 1)); /* bsifi */
+ return p;
+ }
+
+@@ -306,9 +316,14 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+ }
+ }
+ break;
+- case INST_TYPE_RD_R1_IMM5:
++ case INST_TYPE_RD_R1_IMML:
+ print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
+- get_field_r1 (&buf, inst), get_field_imm5 (&buf, inst));
++ get_field_r1(&buf, inst), get_field_imm (&buf, inst));
++ /* TODO: Also print symbol */
++ break;
++ case INST_TYPE_RD_R1_IMMS:
++ print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
++ get_field_r1(&buf, inst), get_field_imms (&buf, inst));
+ break;
+ case INST_TYPE_RD_RFSL:
+ print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
+@@ -412,9 +427,12 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+ }
+ }
+ break;
+- case INST_TYPE_RD_R2:
+- print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
+- get_field_r2 (&buf, inst));
++ case INST_TYPE_IMML:
++ print_func (stream, "\t%s", get_field_imml (&buf, inst));
++ /* TODO: Also print symbol */
++ break;
++ case INST_TYPE_RD_R2:
++ print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_r2 (&buf, inst));
+ break;
+ case INST_TYPE_R2:
+ print_func (stream, "\t%s", get_field_r2 (&buf, inst));
+@@ -439,8 +457,9 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+ break;
+ /* For tuqula instruction */
+ /* For bit field insns. */
+- case INST_TYPE_RD_R1_IMM5_IMM5:
+- print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst), get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst));
++ case INST_TYPE_RD_R1_IMMW_IMMS:
++ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst),
++ get_field_immw (&buf, inst), get_field_imms (&buf, inst));
+ break;
+ /* For tuqula instruction */
+ case INST_TYPE_RD:
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index d3b234e1fcd..28dc991c430 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -40,7 +40,7 @@
+ #define INST_TYPE_RD_SPECIAL 11
+ #define INST_TYPE_R1 12
+ /* New instn type for barrel shift imms. */
+-#define INST_TYPE_RD_R1_IMM5 13
++#define INST_TYPE_RD_R1_IMMS 13
+ #define INST_TYPE_RD_RFSL 14
+ #define INST_TYPE_R1_RFSL 15
+
+@@ -60,7 +60,13 @@
+ #define INST_TYPE_IMM5 20
+
+ /* For bsefi and bsifi */
+-#define INST_TYPE_RD_R1_IMM5_IMM5 21
++#define INST_TYPE_RD_R1_IMMW_IMMS 21
++
++/* For 64-bit instructions */
++#define INST_TYPE_IMML 22
++#define INST_TYPE_RD_R1_IMML 23
++#define INST_TYPE_R1_IMML 24
++#define INST_TYPE_RD_R1_IMMW_IMMS 21
+
+ #define INST_TYPE_NONE 25
+
+@@ -91,13 +97,14 @@
+ #define OPCODE_MASK_H24 0xFC1F07FF /* High 6, bits 20-16 and low 11 bits. */
+ #define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */
+ #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */
+-#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
+-#define OPCODE_MASK_H3B 0xFC00C600 /* High 6 bits and bits 16, 17, 21, 22. */
++#define OPCODE_MASK_H3 0xFC000700 /* High 6 bits and bits 21, 22, 23. */
++#define OPCODE_MASK_H3B 0xFC00E600 /* High 6 bits and bits 16, 17, 18, 21, 22. */
+ #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
+-#define OPCODE_MASK_H32B 0xFC00C000 /* High 6 bits and bit 16, 17. */
++#define OPCODE_MASK_H32B 0xFC00E000 /* High 6 bits and bit 16, 17, 18. */
+ #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
+ #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
++#define OPCODE_MASK_H8 0xFF000000 /* High 8 bits only. */
+
+ /* New Mask for msrset, msrclr insns. */
+ #define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */
+@@ -107,7 +114,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+
+-#define MAX_OPCODES 301
++#define MAX_OPCODES 412
+
+ struct op_code_struct
+ {
+@@ -125,6 +132,7 @@ struct op_code_struct
+ /* More info about output format here. */
+ } opcodes[MAX_OPCODES] =
+ {
++ /* 32-bit instructions */
+ {"add", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst },
+ {"rsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst },
+ {"addc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst },
+@@ -161,11 +169,11 @@ struct op_code_struct
+ {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
+ {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
+ {"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
+- {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
+- {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
+- {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
+- {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
+- {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
++ {"bslli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst },
++ {"bsrai", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst },
++ {"bsrli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst },
++ {"bsefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
++ {"bsifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
+ {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
+ {"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
+ {"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
+@@ -425,6 +433,129 @@ struct op_code_struct
+ {"suspend", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 24. */
+ {"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst },
+ {"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst },
++
++ /* 64-bit instructions */
++ {"addl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000100, OPCODE_MASK_H4, addl, arithmetic_inst },
++ {"rsubl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000100, OPCODE_MASK_H4, rsubl, arithmetic_inst },
++ {"addlc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000100, OPCODE_MASK_H4, addlc, arithmetic_inst },
++ {"rsublc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000100, OPCODE_MASK_H4, rsublc, arithmetic_inst },
++ {"addlk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000100, OPCODE_MASK_H4, addlk, arithmetic_inst },
++ {"rsublk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000100, OPCODE_MASK_H4, rsublk, arithmetic_inst },
++ {"addlkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000100, OPCODE_MASK_H4, addlkc, arithmetic_inst },
++ {"rsublkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000100, OPCODE_MASK_H4, rsublkc, arithmetic_inst },
++ {"cmpl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst },
++ {"cmplu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst },
++ {"addli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"rsubli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"addlic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"addlik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"mull", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst },
++ {"bslll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst },
++ {"bslra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst },
++ {"bslrl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000100, OPCODE_MASK_H3, bslrl, barrel_shift_inst },
++ {"bsllli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002400, OPCODE_MASK_H3B, bsllli, barrel_shift_inst },
++ {"bslrai", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002200, OPCODE_MASK_H3B, bslrai, barrel_shift_inst },
++ {"bslrli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002000, OPCODE_MASK_H3B, bslrli, barrel_shift_inst },
++ {"bslefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64006000, OPCODE_MASK_H32B, bslefi, barrel_shift_inst },
++ {"bslifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6400a000, OPCODE_MASK_H32B, bslifi, barrel_shift_inst },
++ {"orl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000100, OPCODE_MASK_H4, orl, logical_inst },
++ {"andl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000100, OPCODE_MASK_H4, andl, logical_inst },
++ {"xorl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000100, OPCODE_MASK_H4, xorl, logical_inst },
++ {"andnl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000100, OPCODE_MASK_H4, andnl, logical_inst },
++ {"pcmplbf", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000500, OPCODE_MASK_H4, pcmplbf, logical_inst },
++ {"pcmpleq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000500, OPCODE_MASK_H4, pcmpleq, logical_inst },
++ {"pcmplne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000500, OPCODE_MASK_H4, pcmplne, logical_inst },
++ {"srla", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000101, OPCODE_MASK_H34, srla, logical_inst },
++ {"srlc", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000121, OPCODE_MASK_H34, srlc, logical_inst },
++ {"srll", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000141, OPCODE_MASK_H34, srll, logical_inst },
++ {"sextl8", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000160, OPCODE_MASK_H34, sextl8, logical_inst },
++ {"sextl16", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000161, OPCODE_MASK_H34, sextl16, logical_inst },
++ {"sextl32", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000162, OPCODE_MASK_H34, sextl32, logical_inst },
++ {"brea", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98010000, OPCODE_MASK_H124, brea, branch_inst },
++ {"bread", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98110000, OPCODE_MASK_H124, bread, branch_inst },
++ {"breald", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98150000, OPCODE_MASK_H24, breald, branch_inst },
++ {"beaeq", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000000, OPCODE_MASK_H14, beaeq, branch_inst },
++ {"bealeq", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000100, OPCODE_MASK_H14, bealeq, branch_inst },
++ {"beaeqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000000, OPCODE_MASK_H14, beaeqd, branch_inst },
++ {"bealeqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000100, OPCODE_MASK_H14, bealeqd, branch_inst },
++ {"beane", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200000, OPCODE_MASK_H14, beane, branch_inst },
++ {"bealne", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200100, OPCODE_MASK_H14, bealne, branch_inst },
++ {"beaned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200000, OPCODE_MASK_H14, beaned, branch_inst },
++ {"bealned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200100, OPCODE_MASK_H14, bealned, branch_inst },
++ {"bealt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400000, OPCODE_MASK_H14, bealt, branch_inst },
++ {"beallt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400100, OPCODE_MASK_H14, beallt, branch_inst },
++ {"bealtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400000, OPCODE_MASK_H14, bealtd, branch_inst },
++ {"bealltd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400100, OPCODE_MASK_H14, bealltd, branch_inst },
++ {"beale", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600000, OPCODE_MASK_H14, beale, branch_inst },
++ {"bealle", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600100, OPCODE_MASK_H14, bealle, branch_inst },
++ {"bealed", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600000, OPCODE_MASK_H14, bealed, branch_inst },
++ {"bealled", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600100, OPCODE_MASK_H14, bealled, branch_inst },
++ {"beagt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800000, OPCODE_MASK_H14, beagt, branch_inst },
++ {"bealgt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800100, OPCODE_MASK_H14, bealgt, branch_inst },
++ {"beagtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800000, OPCODE_MASK_H14, beagtd, branch_inst },
++ {"bealgtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800100, OPCODE_MASK_H14, bealgtd, branch_inst },
++ {"beage", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00000, OPCODE_MASK_H14, beage, branch_inst },
++ {"bealge", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00100, OPCODE_MASK_H14, bealge, branch_inst },
++ {"beaged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst },
++ {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst },
++ {"orli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
++ {"andli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
++ {"xorli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
++ {"andnli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
++ {"imml", INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst },
++ {"breai", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst },
++ {"breaid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst },
++ {"brealid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8150000, OPCODE_MASK_H2, brealid, branch_inst },
++ {"beaeqi", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, beaeqi, branch_inst },
++ {"bealeqi", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaeqi */
++ {"beaeqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, beaeqid, branch_inst },
++ {"bealeqid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaeqid */
++ {"beanei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, beanei, branch_inst },
++ {"bealnei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beanei */
++ {"beaneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, beaneid, branch_inst },
++ {"bealneid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaneid */
++ {"bealti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, bealti, branch_inst },
++ {"beallti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealti */
++ {"bealtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, bealtid, branch_inst },
++ {"bealltid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealtid */
++ {"bealei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, bealei, branch_inst },
++ {"beallei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealei */
++ {"bealeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, bealeid, branch_inst },
++ {"bealleid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealeid */
++ {"beagti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, beagti, branch_inst },
++ {"bealgti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagti */
++ {"beagtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, beagtid, branch_inst },
++ {"bealgtid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagtid */
++ {"beagei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, beagei, branch_inst },
++ {"bealgei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagei */
++ {"beageid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, beageid, branch_inst },
++ {"bealgeid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beageid */
++ {"ll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000100, OPCODE_MASK_H4, ll, memory_load_inst },
++ {"llr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000300, OPCODE_MASK_H4, llr, memory_load_inst },
++ {"sl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000100, OPCODE_MASK_H4, sl, memory_store_inst },
++ {"slr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000300, OPCODE_MASK_H4, slr, memory_store_inst },
++ {"lli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst }, /* Identical to 32-bit */
++ {"sli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */
++ {"lla", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* lla translates to addlik */
++ {"dadd", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst },
++ {"drsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst },
++ {"dmul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000500, OPCODE_MASK_H4, dmul, arithmetic_inst },
++ {"ddiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000580, OPCODE_MASK_H4, ddiv, arithmetic_inst },
++ {"dcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000610, OPCODE_MASK_H4, dcmp_lt, arithmetic_inst },
++ {"dcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000620, OPCODE_MASK_H4, dcmp_eq, arithmetic_inst },
++ {"dcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000630, OPCODE_MASK_H4, dcmp_le, arithmetic_inst },
++ {"dcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000640, OPCODE_MASK_H4, dcmp_gt, arithmetic_inst },
++ {"dcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000650, OPCODE_MASK_H4, dcmp_ne, arithmetic_inst },
++ {"dcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000660, OPCODE_MASK_H4, dcmp_ge, arithmetic_inst },
++ {"dcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000600, OPCODE_MASK_H4, dcmp_un, arithmetic_inst },
++ {"dbl", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000680, OPCODE_MASK_H4, dbl, arithmetic_inst },
++ {"dlong", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000700, OPCODE_MASK_H4, dlong, arithmetic_inst },
++ {"dsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000780, OPCODE_MASK_H4, dsqrt, arithmetic_inst },
++
+ {"", 0, 0, 0, 0, 0, 0, 0, 0},
+ };
+
+@@ -445,8 +576,17 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM5 ((int) 0x00000000)
+ #define MAX_IMM5 ((int) 0x0000001f)
+
++#define MIN_IMM6 ((int) 0x00000000)
++#define MAX_IMM6 ((int) 0x0000003f)
++
+ #define MIN_IMM_WIDTH ((int) 0x00000001)
+ #define MAX_IMM_WIDTH ((int) 0x00000020)
+
++#define MIN_IMM6_WIDTH ((int) 0x00000001)
++#define MAX_IMM6_WIDTH ((int) 0x00000040)
++
++#define MIN_IMML ((long) 0xffffff8000000000L)
++#define MAX_IMML ((long) 0x0000007fffffffffL)
++
+ #endif /* MICROBLAZE_OPC */
+
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index c3b2b8f0f6e..ad475a4af15 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -25,6 +25,7 @@
+
+ enum microblaze_instr
+ {
++ /* 32-bit instructions */
+ add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu,
+ addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
+ mulh, mulhu, mulhsu,swapb,swaph,
+@@ -58,6 +59,18 @@ enum microblaze_instr
+ aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd,
+ eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd,
+ eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
++
++ /* 64-bit instructions */
++ addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
++ bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl,
++ andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32,
++ brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned,
++ bealned, bealt, beallt, bealtd, bealltd, beale, bealle, bealed, bealled, beagt,
++ bealgt, beagtd, bealgtd, beage, bealge, beaged, bealged, breai, breaid, brealid,
++ beaeqi, beaeqid, beanei, beaneid, bealti, bealtid, bealei, bealeid, beagti,
++ beagtid, beagei, beageid, imml, ll, llr, sl, slr,
++ dadd, drsub, dmul, ddiv, dcmp_lt, dcmp_eq, dcmp_le, dcmp_gt, dcmp_ne, dcmp_ge,
++ dcmp_un, dbl, dlong, dsqrt,
+ invalid_inst
+ };
+
+@@ -135,15 +148,18 @@ enum microblaze_instr_type
+ #define RA_MASK 0x001F0000
+ #define RB_MASK 0x0000F800
+ #define IMM_MASK 0x0000FFFF
++#define IMML_MASK 0x00FFFFFF
+
+-/* Imm mask for barrel shifts. */
++/* Imm masks for barrel shifts. */
+ #define IMM5_MASK 0x0000001F
++#define IMM6_MASK 0x0000003F
+
+ /* Imm mask for mbar. */
+ #define IMM5_MBAR_MASK 0x03E00000
+
+-/* Imm mask for extract/insert width. */
++/* Imm masks for extract/insert width. */
+ #define IMM5_WIDTH_MASK 0x000007C0
++#define IMM6_WIDTH_MASK 0x00000FC0
+
+ /* FSL imm mask for get, put instructions. */
+ #define RFSL_MASK 0x000000F
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0016-MB-X-initial-commit.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0016-MB-X-initial-commit.patch
new file mode 100644
index 0000000..8bf0739
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0016-MB-X-initial-commit.patch
@@ -0,0 +1,337 @@
+From f82b24b2685d0cde8f8fdd0a1dcffe7b76b2027c Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Sun, 30 Sep 2018 16:31:26 +0530
+Subject: [PATCH 16/40] MB-X initial commit code cleanup is needed.
+
+---
+ bfd/bfd-in2.h | 10 +++
+ bfd/elf32-microblaze.c | 63 +++++++++++++++++-
+ bfd/elf64-microblaze.c | 59 +++++++++++++++++
+ bfd/libbfd.h | 2 +
+ bfd/reloc.c | 12 ++++
+ include/elf/microblaze.h | 2 +
+ opcodes/microblaze-opc.h | 4 +-
+ opcodes/microblaze-opcm.h | 4 +-
+ 9 files changed, 243 insertions(+), 40 deletions(-)
+
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 52c81b10b6d..c6738960bb2 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -5373,11 +5373,21 @@ value in two words (with an imm instruction). No relocation is
+ done here - only used for relaxing */
+ BFD_RELOC_MICROBLAZE_64_NONE,
+
++/* This is a 64 bit reloc that stores the 32 bit pc relative
++value in two words (with an imml instruction). No relocation is
++done here - only used for relaxing */
++ BFD_RELOC_MICROBLAZE_64,
++
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction). The relocation is
+ PC-relative GOT offset */
+ BFD_RELOC_MICROBLAZE_64_GOTPC,
+
++/* This is a 64 bit reloc that stores the 32 bit pc relative
++value in two words (with an imml instruction). The relocation is
++PC-relative GOT offset */
++ BFD_RELOC_MICROBLAZE_64_GPC,
++
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction). The relocation is
+ GOT offset */
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index cb7271f5017..a31b407cfbf 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -116,6 +116,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+ 0x0000ffff, /* Dest Mask. */
+ TRUE), /* PC relative offset? */
+
++ HOWTO (R_MICROBLAZE_IMML_64, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 16, /* Bitsize. */
++ TRUE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_dont, /* Complain on overflow. */
++ bfd_elf_generic_reloc,/* Special Function. */
++ "R_MICROBLAZE_IMML_64", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0x0000ffff, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
++
+ /* A 64 bit relocation. Table entry not really used. */
+ HOWTO (R_MICROBLAZE_64, /* Type. */
+ 0, /* Rightshift. */
+@@ -280,6 +294,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+ 0x0000ffff, /* Dest Mask. */
+ TRUE), /* PC relative offset? */
+
++ /* A 64 bit GOTPC relocation. Table-entry not really used. */
++ HOWTO (R_MICROBLAZE_GPC_64, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 16, /* Bitsize. */
++ TRUE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_dont, /* Complain on overflow. */
++ bfd_elf_generic_reloc, /* Special Function. */
++ "R_MICROBLAZE_GPC_64", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0x0000ffff, /* Dest Mask. */
++ TRUE), /* PC relative offset? */
++
+ /* A 64 bit GOT relocation. Table-entry not really used. */
+ HOWTO (R_MICROBLAZE_GOT_64, /* Type. */
+ 0, /* Rightshift. */
+@@ -619,9 +648,15 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+ case BFD_RELOC_VTABLE_ENTRY:
+ microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
+ break;
++ case BFD_RELOC_MICROBLAZE_64:
++ microblaze_reloc = R_MICROBLAZE_IMML_64;
++ break;
+ case BFD_RELOC_MICROBLAZE_64_GOTPC:
+ microblaze_reloc = R_MICROBLAZE_GOTPC_64;
+ break;
++ case BFD_RELOC_MICROBLAZE_64_GPC:
++ microblaze_reloc = R_MICROBLAZE_GPC_64;
++ break;
+ case BFD_RELOC_MICROBLAZE_64_GOT:
+ microblaze_reloc = R_MICROBLAZE_GOT_64;
+ break;
+@@ -1933,6 +1968,28 @@ microblaze_elf_relax_section (bfd *abfd,
+ irel->r_addend -= calc_fixup (irel->r_addend, 0, sec);
+ }
+ break;
++ case R_MICROBLAZE_IMML_64:
++ {
++ /* This was a PC-relative instruction that was
++ completely resolved. */
++ int sfix, efix;
++ unsigned int val;
++ bfd_vma target_address;
++ target_address = irel->r_addend + irel->r_offset;
++ sfix = calc_fixup (irel->r_offset, 0, sec);
++ efix = calc_fixup (target_address, 0, sec);
++
++ /* Validate the in-band val. */
++ val = bfd_get_32 (abfd, contents + irel->r_offset);
++ if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++ }
++ irel->r_addend -= (efix - sfix);
++ /* Should use HOWTO. */
++ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset,
++ irel->r_addend);
++ }
++ break;
+ case R_MICROBLAZE_NONE:
+ case R_MICROBLAZE_32_NONE:
+ {
+@@ -2038,9 +2095,9 @@ microblaze_elf_relax_section (bfd *abfd,
+ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
+ irelscan->r_addend);
+ }
+- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+- {
+- isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
++ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
++ {
++ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+
+ /* Look at the reloc only if the value has been resolved. */
+ if (isym->st_shndx == shndx
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+index fa4b95e47e0..d55700fc513 100644
+--- a/bfd/elf64-microblaze.c
++++ b/bfd/elf64-microblaze.c
+@@ -116,6 +116,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+ 0x0000ffff, /* Dest Mask. */
+ TRUE), /* PC relative offset? */
+
++ /* A 64 bit relocation. Table entry not really used. */
++ HOWTO (R_MICROBLAZE_IMML_64, /* Type. */
++ 0, /* Rightshift. */
++ 4, /* Size (0 = byte, 1 = short, 2 = long). */
++ 64, /* Bitsize. */
++ TRUE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_dont, /* Complain on overflow. */
++ bfd_elf_generic_reloc,/* Special Function. */
++ "R_MICROBLAZE_IMML_64", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0x0000ffff, /* Dest Mask. */
++ TRUE), /* PC relative offset? */
++
+ /* A 64 bit relocation. Table entry not really used. */
+ HOWTO (R_MICROBLAZE_64, /* Type. */
+ 0, /* Rightshift. */
+@@ -265,6 +280,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+ 0x0000ffff, /* Dest Mask. */
+ TRUE), /* PC relative offset? */
+
++ /* A 64 bit GOTPC relocation. Table-entry not really used. */
++ HOWTO (R_MICROBLAZE_GPC_64, /* Type. */
++ 0, /* Rightshift. */
++ 2, /* Size (0 = byte, 1 = short, 2 = long). */
++ 16, /* Bitsize. */
++ TRUE, /* PC_relative. */
++ 0, /* Bitpos. */
++ complain_overflow_dont, /* Complain on overflow. */
++ bfd_elf_generic_reloc, /* Special Function. */
++ "R_MICROBLAZE_GPC_64", /* Name. */
++ FALSE, /* Partial Inplace. */
++ 0, /* Source Mask. */
++ 0x0000ffff, /* Dest Mask. */
++ TRUE), /* PC relative offset? */
++
+ /* A 64 bit GOT relocation. Table-entry not really used. */
+ HOWTO (R_MICROBLAZE_GOT_64, /* Type. */
+ 0, /* Rightshift. */
+@@ -589,9 +619,15 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+ case BFD_RELOC_VTABLE_ENTRY:
+ microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
+ break;
++ case BFD_RELOC_MICROBLAZE_64:
++ microblaze_reloc = R_MICROBLAZE_IMML_64;
++ break;
+ case BFD_RELOC_MICROBLAZE_64_GOTPC:
+ microblaze_reloc = R_MICROBLAZE_GOTPC_64;
+ break;
++ case BFD_RELOC_MICROBLAZE_64_GPC:
++ microblaze_reloc = R_MICROBLAZE_GPC_64;
++ break;
+ case BFD_RELOC_MICROBLAZE_64_GOT:
+ microblaze_reloc = R_MICROBLAZE_GOT_64;
+ break;
+@@ -1162,6 +1198,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ break; /* Do nothing. */
+
+ case (int) R_MICROBLAZE_GOTPC_64:
++ case (int) R_MICROBLAZE_GPC_64:
+ relocation = htab->sgotplt->output_section->vma
+ + htab->sgotplt->output_offset;
+ relocation -= (input_section->output_section->vma
+@@ -1863,6 +1900,28 @@ microblaze_elf_relax_section (bfd *abfd,
+ irel->r_addend -= calc_fixup (irel->r_addend, 0, sec);
+ }
+ break;
++ case R_MICROBLAZE_IMML_64:
++ {
++ /* This was a PC-relative instruction that was
++ completely resolved. */
++ int sfix, efix;
++ unsigned int val;
++ bfd_vma target_address;
++ target_address = irel->r_addend + irel->r_offset;
++ sfix = calc_fixup (irel->r_offset, 0, sec);
++ efix = calc_fixup (target_address, 0, sec);
++
++ /* Validate the in-band val. */
++ val = bfd_get_32 (abfd, contents + irel->r_offset);
++ if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++ }
++ irel->r_addend -= (efix - sfix);
++ /* Should use HOWTO. */
++ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset,
++ irel->r_addend);
++ }
++ break;
+ case R_MICROBLAZE_NONE:
+ case R_MICROBLAZE_32_NONE:
+ {
+diff --git a/bfd/libbfd.h b/bfd/libbfd.h
+index a01891f3423..4e71991273e 100644
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -2905,7 +2905,9 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+ "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
+ "BFD_RELOC_MICROBLAZE_32_NONE",
+ "BFD_RELOC_MICROBLAZE_64_NONE",
++ "BFD_RELOC_MICROBLAZE_64",
+ "BFD_RELOC_MICROBLAZE_64_GOTPC",
++ "BFD_RELOC_MICROBLAZE_64_GPC",
+ "BFD_RELOC_MICROBLAZE_64_GOT",
+ "BFD_RELOC_MICROBLAZE_64_PLT",
+ "BFD_RELOC_MICROBLAZE_64_GOTOFF",
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index 78f13180c71..8b3cc604738 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6814,12 +6814,24 @@ ENUMDOC
+ done here - only used for relaxing
+ ENUM
+ BFD_RELOC_MICROBLAZE_64_NONE
++ENUMDOC
++ This is a 32 bit reloc that stores the 32 bit pc relative
++ value in two words (with an imml instruction). No relocation is
++ done here - only used for relaxing
++ENUM
++ BFD_RELOC_MICROBLAZE_64
+ ENUMDOC
+ This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction). No relocation is
+ done here - only used for relaxing
+ ENUM
+ BFD_RELOC_MICROBLAZE_64_GOTPC
++ENUMDOC
++ This is a 64 bit reloc that stores the 32 bit pc relative
++ value in two words (with an imml instruction). No relocation is
++ done here - only used for relaxing
++ENUM
++ BFD_RELOC_MICROBLAZE_64_GPC
+ ENUMDOC
+ This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction). The relocation is
+diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
+index 0dba2c0f44f..030eb99a1a0 100644
+--- a/include/elf/microblaze.h
++++ b/include/elf/microblaze.h
+@@ -62,6 +62,8 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
+ RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31) /* TEXT Entry offset 64-bit. */
+ RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit. */
+ RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33)
++ RELOC_NUMBER (R_MICROBLAZE_IMML_64, 34)
++ RELOC_NUMBER (R_MICROBLAZE_GPC_64, 35) /* GOT entry offset. */
+ END_RELOC_NUMBERS (R_MICROBLAZE_max)
+
+ /* Global base address names. */
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 28dc991c430..46263bc7e16 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -538,8 +538,8 @@ struct op_code_struct
+ {"llr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000300, OPCODE_MASK_H4, llr, memory_load_inst },
+ {"sl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000100, OPCODE_MASK_H4, sl, memory_store_inst },
+ {"slr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000300, OPCODE_MASK_H4, slr, memory_store_inst },
+- {"lli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst }, /* Identical to 32-bit */
+- {"sli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */
++ {"lli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xEC000000, OPCODE_MASK_H, invalid_inst, memory_load_inst }, /* Identical to 32-bit */
++ {"sli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xFC000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */
+ {"lla", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* lla translates to addlik */
+ {"dadd", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst },
+ {"drsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index ad475a4af15..ee01cdb7d9b 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -40,8 +40,8 @@ enum microblaze_instr
+ imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+ brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+ bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
+- sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi,
+- sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
++ sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi, lli,
++ sbi, shi, sli, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
+ fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
+ fint, fsqrt,
+ tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch
new file mode 100644
index 0000000..eaf2450
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch
@@ -0,0 +1,37 @@
+From b6ec3e2295ba33d2c8f48500d75a147ffd84a656 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 11 Sep 2018 13:48:33 +0530
+Subject: [PATCH 17/40] [Patch,Microblaze] : negl instruction is overriding
+ rsubl
+
+fixed it by changing the instruction order...
+---
+ opcodes/microblaze-opc.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 46263bc7e16..f4ee8f43372 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -275,9 +275,7 @@ struct op_code_struct
+ {"la", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik. */
+ {"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42. */
+ {"not", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1. */
+- {"neg", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0. */
+ {"rtb", INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4. */
+- {"sub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra. */
+ {"lmi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },
+ {"smi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst },
+ {"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst },
+@@ -555,6 +553,8 @@ struct op_code_struct
+ {"dbl", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000680, OPCODE_MASK_H4, dbl, arithmetic_inst },
+ {"dlong", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000700, OPCODE_MASK_H4, dlong, arithmetic_inst },
+ {"dsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000780, OPCODE_MASK_H4, dsqrt, arithmetic_inst },
++ {"neg", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0. */
++ {"sub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra. */
+
+ {"", 0, 0, 0, 0, 0, 0, 0, 0},
+ };
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0018-Added-relocations-for-MB-X.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0018-Added-relocations-for-MB-X.patch
new file mode 100644
index 0000000..742f9e3
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0018-Added-relocations-for-MB-X.patch
@@ -0,0 +1,113 @@
+From 982f37caabea84cee52426844e73365f0cb93f3d Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Tue, 11 Sep 2018 17:30:17 +0530
+Subject: [PATCH 18/40] Added relocations for MB-X
+
+---
+ bfd/bfd-in2.h | 11 +++++---
+ bfd/libbfd.h | 4 +--
+ bfd/reloc.c | 26 +++++++++---------
+ 4 files changed, 63 insertions(+), 32 deletions(-)
+
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index c6738960bb2..3899352b1d5 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -5369,15 +5369,20 @@ done here - only used for relaxing */
+ BFD_RELOC_MICROBLAZE_32_NONE,
+
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+-value in two words (with an imm instruction). No relocation is
++value in two words (with an imml instruction). No relocation is
+ done here - only used for relaxing */
+- BFD_RELOC_MICROBLAZE_64_NONE,
++ BFD_RELOC_MICROBLAZE_64_PCREL,
+
+-/* This is a 64 bit reloc that stores the 32 bit pc relative
++/* This is a 64 bit reloc that stores the 32 bit relative
+ value in two words (with an imml instruction). No relocation is
+ done here - only used for relaxing */
+ BFD_RELOC_MICROBLAZE_64,
+
++/* This is a 64 bit reloc that stores the 32 bit pc relative
++value in two words (with an imm instruction). No relocation is
++done here - only used for relaxing */
++ BFD_RELOC_MICROBLAZE_64_NONE,
++
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction). The relocation is
+ PC-relative GOT offset */
+diff --git a/bfd/libbfd.h b/bfd/libbfd.h
+index 4e71991273e..46be3891390 100644
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -2905,14 +2905,14 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+ "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
+ "BFD_RELOC_MICROBLAZE_32_NONE",
+ "BFD_RELOC_MICROBLAZE_64_NONE",
+- "BFD_RELOC_MICROBLAZE_64",
+ "BFD_RELOC_MICROBLAZE_64_GOTPC",
+- "BFD_RELOC_MICROBLAZE_64_GPC",
+ "BFD_RELOC_MICROBLAZE_64_GOT",
+ "BFD_RELOC_MICROBLAZE_64_PLT",
+ "BFD_RELOC_MICROBLAZE_64_GOTOFF",
+ "BFD_RELOC_MICROBLAZE_32_GOTOFF",
+ "BFD_RELOC_MICROBLAZE_COPY",
++ "BFD_RELOC_MICROBLAZE_64",
++ "BFD_RELOC_MICROBLAZE_64_PCREL",
+ "BFD_RELOC_MICROBLAZE_64_TLS",
+ "BFD_RELOC_MICROBLAZE_64_TLSGD",
+ "BFD_RELOC_MICROBLAZE_64_TLSLD",
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index 8b3cc604738..98a156f061f 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6814,24 +6814,12 @@ ENUMDOC
+ done here - only used for relaxing
+ ENUM
+ BFD_RELOC_MICROBLAZE_64_NONE
+-ENUMDOC
+- This is a 32 bit reloc that stores the 32 bit pc relative
+- value in two words (with an imml instruction). No relocation is
+- done here - only used for relaxing
+-ENUM
+- BFD_RELOC_MICROBLAZE_64
+ ENUMDOC
+ This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction). No relocation is
+ done here - only used for relaxing
+ ENUM
+ BFD_RELOC_MICROBLAZE_64_GOTPC
+-ENUMDOC
+- This is a 64 bit reloc that stores the 32 bit pc relative
+- value in two words (with an imml instruction). No relocation is
+- done here - only used for relaxing
+-ENUM
+- BFD_RELOC_MICROBLAZE_64_GPC
+ ENUMDOC
+ This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction). The relocation is
+@@ -6917,6 +6905,20 @@ ENUMDOC
+ value in two words (with an imm instruction). The relocation is
+ relative offset from start of TEXT.
+
++ This is a 64 bit reloc that stores 64-bit thread pointer relative offset
++ to two words (uses imml instruction).
++ENUM
++BFD_RELOC_MICROBLAZE_64,
++ENUMDOC
++ This is a 64 bit reloc that stores the 64 bit pc relative
++ value in two words (with an imml instruction). No relocation is
++ done here - only used for relaxing
++ENUM
++BFD_RELOC_MICROBLAZE_64_PCREL,
++ENUMDOC
++ This is a 32 bit reloc that stores the 32 bit pc relative
++ value in two words (with an imml instruction). No relocation is
++ done here - only used for relaxing
+ ENUM
+ BFD_RELOC_AARCH64_RELOC_START
+ ENUMDOC
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0019-Update-MB-x.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0019-Update-MB-x.patch
new file mode 100644
index 0000000..fc5c946
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0019-Update-MB-x.patch
@@ -0,0 +1,116 @@
+From 0bb779328b8564b008a6134826f043b4326f4904 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Fri, 28 Sep 2018 12:04:55 +0530
+Subject: [PATCH 19/40] Update MB-x
+
+-Fixed MB-x relocation issues
+-Added imml for required MB-x instructions
+---
+ bfd/elf64-microblaze.c | 68 ++++++++++--
+ 3 files changed, 209 insertions(+), 82 deletions(-)
+
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+index d55700fc513..f8f52870639 100644
+--- a/bfd/elf64-microblaze.c
++++ b/bfd/elf64-microblaze.c
+@@ -1478,8 +1478,17 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ relocation -= (input_section->output_section->vma
+ + input_section->output_offset
+ + offset + INST_WORD_SIZE);
+- bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++ unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian);
++ if (insn == 0xb2000000 || insn == 0xb2ffffff)
++ {
++ insn &= ~0x00ffffff;
++ insn |= (relocation >> 16) & 0xffffff;
++ bfd_put_32 (input_bfd, insn,
+ contents + offset + endian);
++ }
++ else
++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++ contents + offset + endian);
+ bfd_put_16 (input_bfd, relocation & 0xffff,
+ contents + offset + endian + INST_WORD_SIZE);
+ }
+@@ -1569,11 +1578,28 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ else
+ {
+ if (r_type == R_MICROBLAZE_64_PCREL)
+- relocation -= (input_section->output_section->vma
+- + input_section->output_offset
+- + offset + INST_WORD_SIZE);
+- bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++ {
++ if (!input_section->output_section->vma &&
++ !input_section->output_offset && !offset)
++ relocation -= (input_section->output_section->vma
++ + input_section->output_offset
++ + offset);
++ else
++ relocation -= (input_section->output_section->vma
++ + input_section->output_offset
++ + offset + INST_WORD_SIZE);
++ }
++ unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian);
++ if (insn == 0xb2000000 || insn == 0xb2ffffff)
++ {
++ insn &= ~0x00ffffff;
++ insn |= (relocation >> 16) & 0xffffff;
++ bfd_put_32 (input_bfd, insn,
+ contents + offset + endian);
++ }
++ else
++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++ contents + offset + endian);
+ bfd_put_16 (input_bfd, relocation & 0xffff,
+ contents + offset + endian + INST_WORD_SIZE);
+ }
+@@ -1677,9 +1703,19 @@ static void
+ microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
+ {
+ unsigned long instr = bfd_get_32 (abfd, bfd_addr);
+- instr &= ~0x0000ffff;
+- instr |= (val & 0x0000ffff);
+- bfd_put_32 (abfd, instr, bfd_addr);
++
++ if (instr == 0xb2000000 || instr == 0xb2ffffff)
++ {
++ instr &= ~0x00ffffff;
++ instr |= (val & 0xffffff);
++ bfd_put_32 (abfd, instr, bfd_addr);
++ }
++ else
++ {
++ instr &= ~0x0000ffff;
++ instr |= (val & 0x0000ffff);
++ bfd_put_32 (abfd, instr, bfd_addr);
++ }
+ }
+
+ /* Read-modify-write into the bfd, an immediate value into appropriate fields of
+@@ -1691,10 +1727,18 @@ microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
+ unsigned long instr_lo;
+
+ instr_hi = bfd_get_32 (abfd, bfd_addr);
+- instr_hi &= ~0x0000ffff;
+- instr_hi |= ((val >> 16) & 0x0000ffff);
+- bfd_put_32 (abfd, instr_hi, bfd_addr);
+-
++ if (instr_hi == 0xb2000000 || instr_hi == 0xb2ffffff)
++ {
++ instr_hi &= ~0x00ffffff;
++ instr_hi |= (val >> 16) & 0xffffff;
++ bfd_put_32 (abfd, instr_hi,bfd_addr);
++ }
++ else
++ {
++ instr_hi &= ~0x0000ffff;
++ instr_hi |= ((val >> 16) & 0x0000ffff);
++ bfd_put_32 (abfd, instr_hi, bfd_addr);
++ }
+ instr_lo = bfd_get_32 (abfd, bfd_addr + INST_WORD_SIZE);
+ instr_lo &= ~0x0000ffff;
+ instr_lo |= (val & 0x0000ffff);
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0020-Various-fixes.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0020-Various-fixes.patch
new file mode 100644
index 0000000..eb0bc98
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0020-Various-fixes.patch
@@ -0,0 +1,98 @@
+From 188a60b441711f663f07dc3c3902c8c5d590eb6c Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Tue, 9 Oct 2018 10:14:22 +0530
+Subject: [PATCH 20/40] Various fixes
+
+- Fixed address computation issues with 64bit address
+- Fixed imml dissassamble issue
+---
+ bfd/bfd-in2.h | 5 +++
+ bfd/elf64-microblaze.c | 14 ++++----
+ opcodes/microblaze-dis.c | 2 +-
+ 4 files changed, 79 insertions(+), 16 deletions(-)
+
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 3899352b1d5..91761bf6964 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -5378,6 +5378,11 @@ value in two words (with an imml instruction). No relocation is
+ done here - only used for relaxing */
+ BFD_RELOC_MICROBLAZE_64,
+
++/* This is a 64 bit reloc that stores the 32 bit relative
++value in two words (with an imml instruction). No relocation is
++done here - only used for relaxing */
++ BFD_RELOC_MICROBLAZE_EA64,
++
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction). No relocation is
+ done here - only used for relaxing */
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+index f8f52870639..17e58748a0b 100644
+--- a/bfd/elf64-microblaze.c
++++ b/bfd/elf64-microblaze.c
+@@ -121,15 +121,15 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+ 0, /* Rightshift. */
+ 4, /* Size (0 = byte, 1 = short, 2 = long). */
+ 64, /* Bitsize. */
+- TRUE, /* PC_relative. */
++ FALSE, /* PC_relative. */
+ 0, /* Bitpos. */
+ complain_overflow_dont, /* Complain on overflow. */
+ bfd_elf_generic_reloc,/* Special Function. */
+ "R_MICROBLAZE_IMML_64", /* Name. */
+ FALSE, /* Partial Inplace. */
+ 0, /* Source Mask. */
+- 0x0000ffff, /* Dest Mask. */
+- TRUE), /* PC relative offset? */
++ 0xffffffffffffff, /* Dest Mask. */
++ FALSE), /* PC relative offset? */
+
+ /* A 64 bit relocation. Table entry not really used. */
+ HOWTO (R_MICROBLAZE_64, /* Type. */
+@@ -585,9 +585,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+ case BFD_RELOC_32:
+ microblaze_reloc = R_MICROBLAZE_32;
+ break;
+- /* RVA is treated the same as 32 */
++ /* RVA is treated the same as 64 */
+ case BFD_RELOC_RVA:
+- microblaze_reloc = R_MICROBLAZE_32;
++ microblaze_reloc = R_MICROBLAZE_IMML_64;
+ break;
+ case BFD_RELOC_32_PCREL:
+ microblaze_reloc = R_MICROBLAZE_32_PCREL;
+@@ -619,7 +619,7 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+ case BFD_RELOC_VTABLE_ENTRY:
+ microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
+ break;
+- case BFD_RELOC_MICROBLAZE_64:
++ case BFD_RELOC_MICROBLAZE_EA64:
+ microblaze_reloc = R_MICROBLAZE_IMML_64;
+ break;
+ case BFD_RELOC_MICROBLAZE_64_GOTPC:
+@@ -1956,7 +1956,7 @@ microblaze_elf_relax_section (bfd *abfd,
+ efix = calc_fixup (target_address, 0, sec);
+
+ /* Validate the in-band val. */
+- val = bfd_get_32 (abfd, contents + irel->r_offset);
++ val = bfd_get_64 (abfd, contents + irel->r_offset);
+ if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
+ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
+ }
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index 437f536e96a..24ede714858 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -78,7 +78,7 @@ get_field_imml (struct string_buf *buf, long instr)
+ {
+ char *p = strbuf (buf);
+
+- sprintf (p, "%d", (short)((instr & IMML_MASK) >> IMM_LOW));
++ sprintf (p, "%d", (int)((instr & IMML_MASK) >> IMM_LOW));
+ return p;
+ }
+
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0021-Adding-new-relocation-to-support-64bit-rodata.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0021-Adding-new-relocation-to-support-64bit-rodata.patch
new file mode 100644
index 0000000..0d212cc
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0021-Adding-new-relocation-to-support-64bit-rodata.patch
@@ -0,0 +1,69 @@
+From a485fdf959afb6cd079f482eeea9d3186e6393f8 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Sat, 13 Oct 2018 21:17:01 +0530
+Subject: [PATCH 21/40] Adding new relocation to support 64bit rodata
+
+---
+ bfd/elf64-microblaze.c | 11 +++++++--
+ 2 files changed, 54 insertions(+), 6 deletions(-)
+
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+index 17e58748a0b..b62c47e8514 100644
+--- a/bfd/elf64-microblaze.c
++++ b/bfd/elf64-microblaze.c
+@@ -1463,6 +1463,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ case (int) R_MICROBLAZE_64_PCREL :
+ case (int) R_MICROBLAZE_64:
+ case (int) R_MICROBLAZE_32:
++ case (int) R_MICROBLAZE_IMML_64:
+ {
+ /* r_symndx will be STN_UNDEF (zero) only for relocs against symbols
+ from removed linkonce sections, or sections discarded by
+@@ -1472,6 +1473,8 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ relocation += addend;
+ if (r_type == R_MICROBLAZE_32)
+ bfd_put_32 (input_bfd, relocation, contents + offset);
++ else if (r_type == R_MICROBLAZE_IMML_64)
++ bfd_put_64 (input_bfd, relocation, contents + offset);
+ else
+ {
+ if (r_type == R_MICROBLAZE_64_PCREL)
+@@ -1549,7 +1552,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ }
+ else
+ {
+- if (r_type == R_MICROBLAZE_32)
++ if (r_type == R_MICROBLAZE_32 || r_type == R_MICROBLAZE_IMML_64)
+ {
+ outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL);
+ outrel.r_addend = relocation + addend;
+@@ -1575,6 +1578,8 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ relocation += addend;
+ if (r_type == R_MICROBLAZE_32)
+ bfd_put_32 (input_bfd, relocation, contents + offset);
++ else if (r_type == R_MICROBLAZE_IMML_64)
++ bfd_put_64 (input_bfd, relocation, contents + offset + endian);
+ else
+ {
+ if (r_type == R_MICROBLAZE_64_PCREL)
+@@ -2072,7 +2077,8 @@ microblaze_elf_relax_section (bfd *abfd,
+ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
+ irelscan->r_addend);
+ }
+- if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
++ if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32
++ || ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_IMML_64)
+ {
+ isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
+
+@@ -2568,6 +2574,7 @@ microblaze_elf_check_relocs (bfd * abfd,
+ case R_MICROBLAZE_64:
+ case R_MICROBLAZE_64_PCREL:
+ case R_MICROBLAZE_32:
++ case R_MICROBLAZE_IMML_64:
+ {
+ if (h != NULL && !bfd_link_pic (info))
+ {
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0022-fixing-the-.bss-relocation-issue.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0022-fixing-the-.bss-relocation-issue.patch
new file mode 100644
index 0000000..aa512b8
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0022-fixing-the-.bss-relocation-issue.patch
@@ -0,0 +1,76 @@
+From 24f96f4e86895b41aae21f775599a857939d002f Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Wed, 24 Oct 2018 12:34:37 +0530
+Subject: [PATCH 22/40] fixing the .bss relocation issue
+
+---
+ bfd/elf64-microblaze.c | 18 ++++++++++++------
+ 1 file changed, 12 insertions(+), 6 deletions(-)
+
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+index b62c47e8514..cb3b40b574c 100644
+--- a/bfd/elf64-microblaze.c
++++ b/bfd/elf64-microblaze.c
+@@ -1482,7 +1482,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ + input_section->output_offset
+ + offset + INST_WORD_SIZE);
+ unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian);
+- if (insn == 0xb2000000 || insn == 0xb2ffffff)
++ if ((insn & 0xff000000) == 0xb2000000)
+ {
+ insn &= ~0x00ffffff;
+ insn |= (relocation >> 16) & 0xffffff;
+@@ -1595,7 +1595,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ + offset + INST_WORD_SIZE);
+ }
+ unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian);
+- if (insn == 0xb2000000 || insn == 0xb2ffffff)
++ if ((insn & 0xff000000) == 0xb2000000)
+ {
+ insn &= ~0x00ffffff;
+ insn |= (relocation >> 16) & 0xffffff;
+@@ -1709,7 +1709,7 @@ microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
+ {
+ unsigned long instr = bfd_get_32 (abfd, bfd_addr);
+
+- if (instr == 0xb2000000 || instr == 0xb2ffffff)
++ if ((instr & 0xff000000) == 0xb2000000)
+ {
+ instr &= ~0x00ffffff;
+ instr |= (val & 0xffffff);
+@@ -1732,7 +1732,7 @@ microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
+ unsigned long instr_lo;
+
+ instr_hi = bfd_get_32 (abfd, bfd_addr);
+- if (instr_hi == 0xb2000000 || instr_hi == 0xb2ffffff)
++ if ((instr_hi & 0xff000000) == 0xb2000000)
+ {
+ instr_hi &= ~0x00ffffff;
+ instr_hi |= (val >> 16) & 0xffffff;
+@@ -2225,7 +2225,10 @@ microblaze_elf_relax_section (bfd *abfd,
+ unsigned long instr_lo = bfd_get_32 (abfd, ocontents
+ + irelscan->r_offset
+ + INST_WORD_SIZE);
+- immediate = (instr_hi & 0x0000ffff) << 16;
++ if ((instr_hi & 0xff000000) == 0xb2000000)
++ immediate = (instr_hi & 0x00ffffff) << 24;
++ else
++ immediate = (instr_hi & 0x0000ffff) << 16;
+ immediate |= (instr_lo & 0x0000ffff);
+ offset = calc_fixup (irelscan->r_addend, 0, sec);
+ immediate -= offset;
+@@ -2269,7 +2272,10 @@ microblaze_elf_relax_section (bfd *abfd,
+ unsigned long instr_lo = bfd_get_32 (abfd, ocontents
+ + irelscan->r_offset
+ + INST_WORD_SIZE);
+- immediate = (instr_hi & 0x0000ffff) << 16;
++ if ((instr_hi & 0xff000000) == 0xb2000000)
++ immediate = (instr_hi & 0x00ffffff) << 24;
++ else
++ immediate = (instr_hi & 0x0000ffff) << 16;
+ immediate |= (instr_lo & 0x0000ffff);
+ target_address = immediate;
+ offset = calc_fixup (target_address, 0, sec);
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0023-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0023-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch
new file mode 100644
index 0000000..c645781
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0023-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch
@@ -0,0 +1,44 @@
+From cd5868dca5b4a728e6418459d871f5c9ca68253e Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Wed, 28 Nov 2018 14:00:29 +0530
+Subject: [PATCH 23/40] Fixed the bug in the R_MICROBLAZE_64_NONE relocation.
+ It was adjusting only lower 16bits.
+
+---
+ bfd/elf32-microblaze.c | 4 ++--
+ bfd/elf64-microblaze.c | 4 ++--
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index a31b407cfbf..04816a4a187 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -2023,8 +2023,8 @@ microblaze_elf_relax_section (bfd *abfd,
+ sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec);
+ efix = calc_fixup (target_address, 0, sec);
+ irel->r_addend -= (efix - sfix);
+- microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset
+- + INST_WORD_SIZE, irel->r_addend);
++ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset,
++ irel->r_addend);
+ }
+ break;
+ }
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+index cb3b40b574c..b002b414d64 100644
+--- a/bfd/elf64-microblaze.c
++++ b/bfd/elf64-microblaze.c
+@@ -2004,8 +2004,8 @@ microblaze_elf_relax_section (bfd *abfd,
+ sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec);
+ efix = calc_fixup (target_address, 0, sec);
+ irel->r_addend -= (efix - sfix);
+- microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset
+- + INST_WORD_SIZE, irel->r_addend);
++ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset,
++ irel->r_addend);
+ }
+ break;
+ }
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0025-Patch-Microblaze-Binutils-security-check-is-causing-.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0025-Patch-Microblaze-Binutils-security-check-is-causing-.patch
new file mode 100644
index 0000000..f5bf917
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0025-Patch-Microblaze-Binutils-security-check-is-causing-.patch
@@ -0,0 +1,34 @@
+From 25a67af22ad040f87b3c14185c338828d4e26908 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 11 Mar 2019 14:23:58 +0530
+Subject: [PATCH 25/40] [Patch,Microblaze] : Binutils security check is causing
+ build error for windows builds.commenting for now.
+
+---
+ bfd/elf-attrs.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/bfd/elf-attrs.c b/bfd/elf-attrs.c
+index bfe135e7fbb..abf267ad42e 100644
+--- a/bfd/elf-attrs.c
++++ b/bfd/elf-attrs.c
+@@ -440,6 +440,8 @@ _bfd_elf_parse_attributes (bfd *abfd, Elf_Internal_Shdr * hdr)
+ /* PR 17512: file: 2844a11d. */
+ if (hdr->sh_size == 0)
+ return;
++
++ #if 0
+ if (hdr->sh_size > bfd_get_file_size (abfd))
+ {
+ /* xgettext:c-format */
+@@ -448,6 +450,7 @@ _bfd_elf_parse_attributes (bfd *abfd, Elf_Internal_Shdr * hdr)
+ bfd_set_error (bfd_error_invalid_operation);
+ return;
+ }
++ #endif
+
+ contents = (bfd_byte *) bfd_malloc (hdr->sh_size + 1);
+ if (!contents)
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0026-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0026-fixing-the-long-long-long-mingw-toolchain-issue.patch
new file mode 100644
index 0000000..f5ddce4
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0026-fixing-the-long-long-long-mingw-toolchain-issue.patch
@@ -0,0 +1,27 @@
+From b9e89f0698fd0e3b0e965986681f9fd90d3dc313 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Thu, 29 Nov 2018 17:59:25 +0530
+Subject: [PATCH 26/40] fixing the long & long long mingw toolchain issue
+
+---
+ opcodes/microblaze-opc.h | 4 ++--
+ 2 files changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index f4ee8f43372..c8c2addc351 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -585,8 +585,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM6_WIDTH ((int) 0x00000001)
+ #define MAX_IMM6_WIDTH ((int) 0x00000040)
+
+-#define MIN_IMML ((long) 0xffffff8000000000L)
+-#define MAX_IMML ((long) 0x0000007fffffffffL)
++#define MIN_IMML ((long long) 0xffffff8000000000L)
++#define MAX_IMML ((long long) 0x0000007fffffffffL)
+
+ #endif /* MICROBLAZE_OPC */
+
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0027-Added-support-to-new-arithmetic-single-register-inst.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0027-Added-support-to-new-arithmetic-single-register-inst.patch
new file mode 100644
index 0000000..bf05816
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0027-Added-support-to-new-arithmetic-single-register-inst.patch
@@ -0,0 +1,181 @@
+From efc3fd518cdb7e8bf82ac27b98b946001f83a2bf Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Fri, 23 Aug 2019 16:18:43 +0530
+Subject: [PATCH 27/40] Added support to new arithmetic single register
+ instructions
+
+---
+ opcodes/microblaze-dis.c | 13 +++-
+ opcodes/microblaze-opc.h | 45 +++++++++++-
+ opcodes/microblaze-opcm.h | 5 +-
+ 4 files changed, 201 insertions(+), 7 deletions(-)
+
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index 24ede714858..e93d9b890ba 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -131,6 +131,15 @@ get_field_imm15 (struct string_buf *buf, long instr)
+ return p;
+ }
+
++static char *
++get_field_imm16 (struct string_buf *buf, long instr)
++{
++ char *p = strbuf (buf);
++
++ sprintf (p, "%d", (short)((instr & IMM16_MASK) >> IMM_LOW));
++ return p;
++}
++
+ static char *
+ get_field_special (struct string_buf *buf, long instr,
+ struct op_code_struct *op)
+@@ -448,6 +457,9 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+ print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
+ get_field_imm15 (&buf, inst));
+ break;
++ case INST_TYPE_RD_IMML:
++ print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_imm16 (&buf, inst));
++ break;
+ /* For mbar insn. */
+ case INST_TYPE_IMM5:
+ print_func (stream, "\t%s", get_field_imm5_mbar (&buf, inst));
+@@ -455,7 +467,6 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+ /* For mbar 16 or sleep insn. */
+ case INST_TYPE_NONE:
+ break;
+- /* For tuqula instruction */
+ /* For bit field insns. */
+ case INST_TYPE_RD_R1_IMMW_IMMS:
+ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst),
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index c8c2addc351..eaf4a1bd9f9 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -69,6 +69,7 @@
+ #define INST_TYPE_RD_R1_IMMW_IMMS 21
+
+ #define INST_TYPE_NONE 25
++#define INST_TYPE_RD_IMML 26
+
+
+
+@@ -84,6 +85,7 @@
+ #define IMMVAL_MASK_MFS 0x0000
+
+ #define OPCODE_MASK_H 0xFC000000 /* High 6 bits only. */
++#define OPCODE_MASK_LIMM 0xFC1F0000 /* High 6 bits and 12-16 bits */
+ #define OPCODE_MASK_H1 0xFFE00000 /* High 11 bits. */
+ #define OPCODE_MASK_H2 0xFC1F0000 /* High 6 and bits 20-16. */
+ #define OPCODE_MASK_H12 0xFFFF0000 /* High 16. */
+@@ -106,6 +108,33 @@
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
+ #define OPCODE_MASK_H8 0xFF000000 /* High 8 bits only. */
+
++/*Defines to identify 64-bit single reg instructions */
++#define ADDLI_ONE_REG_MASK 0x68000000
++#define ADDLIC_ONE_REG_MASK 0x68020000
++#define ADDLIK_ONE_REG_MASK 0x68040000
++#define ADDLIKC_ONE_REG_MASK 0x68060000
++#define RSUBLI_ONE_REG_MASK 0x68010000
++#define RSUBLIC_ONE_REG_MASK 0x68030000
++#define RSUBLIK_ONE_REG_MASK 0x68050000
++#define RSUBLIKC_ONE_REG_MASK 0x68070000
++#define ORLI_ONE_REG_MASK 0x68100000
++#define ANDLI_ONE_REG_MASK 0x68110000
++#define XORLI_ONE_REG_MASK 0x68120000
++#define ANDLNI_ONE_REG_MASK 0x68130000
++#define ADDLI_MASK 0x20000000
++#define ADDLIC_MASK 0x28000000
++#define ADDLIK_MASK 0x30000000
++#define ADDLIKC_MASK 0x38000000
++#define RSUBLI_MASK 0x24000000
++#define RSUBLIC_MASK 0x2C000000
++#define RSUBLIK_MASK 0x34000000
++#define RSUBLIKC_MASK 0x3C000000
++#define ANDLI_MASK 0xA4000000
++#define ANDLNI_MASK 0xAC000000
++#define ORLI_MASK 0xA0000000
++#define XORLI_MASK 0xA8000000
++
++
+ /* New Mask for msrset, msrclr insns. */
+ #define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */
+ /* Mask for mbar insn. */
+@@ -114,13 +143,13 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+
+-#define MAX_OPCODES 412
++#define MAX_OPCODES 424
+
+ struct op_code_struct
+ {
+ const char * name;
+ short inst_type; /* Registers and immediate values involved. */
+- short inst_offset_type; /* Immediate vals offset from PC? (= 1 for branches). */
++ int inst_offset_type; /* Immediate vals offset from PC? (= 1 for branches). */
+ short delay_slots; /* Info about delay slots needed after this instr. */
+ short immval_mask;
+ unsigned long bit_sequence; /* All the fixed bits for the op are set and
+@@ -444,13 +473,21 @@ struct op_code_struct
+ {"cmpl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst },
+ {"cmplu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst },
+ {"addli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"addli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68000000, OPCODE_MASK_LIMM, addli, arithmetic_inst },
+ {"rsubli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"rsubli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68010000, OPCODE_MASK_LIMM, rsubli, arithmetic_inst },
+ {"addlic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"addlic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68020000, OPCODE_MASK_LIMM, addlic, arithmetic_inst },
+ {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"rsublic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68030000, OPCODE_MASK_LIMM, rsublic, arithmetic_inst },
+ {"addlik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"addlik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68040000, OPCODE_MASK_LIMM, addlik, arithmetic_inst },
+ {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"rsublik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68050000, OPCODE_MASK_LIMM, rsublik, arithmetic_inst },
+ {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"addlikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68060000, OPCODE_MASK_LIMM, addlikc, arithmetic_inst },
+ {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
++ {"rsublikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68070000, OPCODE_MASK_LIMM, rsublikc, arithmetic_inst },
+ {"mull", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst },
+ {"bslll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst },
+ {"bslra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst },
+@@ -501,9 +538,13 @@ struct op_code_struct
+ {"beaged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst },
+ {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst },
+ {"orli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
++ {"orli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68100000, OPCODE_MASK_LIMM, orli, arithmetic_inst },
+ {"andli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
++ {"andli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68110000, OPCODE_MASK_LIMM, andli, arithmetic_inst },
+ {"xorli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
++ {"xorli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68120000, OPCODE_MASK_LIMM, xorli, arithmetic_inst },
+ {"andnli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
++ {"andnli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68130000, OPCODE_MASK_LIMM, andnli, arithmetic_inst },
+ {"imml", INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst },
+ {"breai", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst },
+ {"breaid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index ee01cdb7d9b..31726c9b01a 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -61,7 +61,9 @@ enum microblaze_instr
+ eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
+
+ /* 64-bit instructions */
+- addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
++ addl, addli, addlic, addlik, addlikc, rsubl, rsubli, rsublic, rsublik, rsublikc,
++ addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
++ andli, andnli, orli, xorli,
+ bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl,
+ andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32,
+ brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned,
+@@ -166,5 +168,6 @@ enum microblaze_instr_type
+
+ /* Imm mask for msrset, msrclr instructions. */
+ #define IMM15_MASK 0x00007FFF
++#define IMM16_MASK 0x0000FFFF
+
+ #endif /* MICROBLAZE-OPCM */
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0028-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0028-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch
new file mode 100644
index 0000000..01d615d
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0028-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch
@@ -0,0 +1,28 @@
+From 953a4eb8152c0aca3e36ccc22a8950c9e68965b5 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 26 Aug 2019 15:29:42 +0530
+Subject: [PATCH 28/40] [Patch,MicroBlaze] : double imml generation for 64 bit
+ values.
+
+---
+ opcodes/microblaze-opc.h | 4 +-
+ 2 files changed, 264 insertions(+), 64 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index eaf4a1bd9f9..79c3cf0d1a1 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -626,8 +626,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM6_WIDTH ((int) 0x00000001)
+ #define MAX_IMM6_WIDTH ((int) 0x00000040)
+
+-#define MIN_IMML ((long long) 0xffffff8000000000L)
+-#define MAX_IMML ((long long) 0x0000007fffffffffL)
++#define MIN_IMML ((long long) -9223372036854775807)
++#define MAX_IMML ((long long) 9223372036854775807)
+
+ #endif /* MICROBLAZE_OPC */
+
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0033-Fix-various-compile-warnings.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0033-Fix-various-compile-warnings.patch
new file mode 100644
index 0000000..4172595
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0033-Fix-various-compile-warnings.patch
@@ -0,0 +1,60 @@
+From c59684852ecd37d6f82363f2cf0e1de1f770aab7 Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@kernel.crashing.org>
+Date: Fri, 17 Jul 2020 09:20:54 -0500
+Subject: [PATCH 33/40] Fix various compile warnings
+
+Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
+---
+ bfd/elf64-microblaze.c | 9 +++++----
+ 2 files changed, 10 insertions(+), 10 deletions(-)
+
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+index b002b414d64..8308f1ebd09 100644
+--- a/bfd/elf64-microblaze.c
++++ b/bfd/elf64-microblaze.c
+@@ -692,7 +692,7 @@ microblaze_elf_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
+ /* Set the howto pointer for a RCE ELF reloc. */
+
+ static bfd_boolean
+-microblaze_elf_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED,
++microblaze_elf_info_to_howto (bfd * abfd,
+ arelent * cache_ptr,
+ Elf_Internal_Rela * dst)
+ {
+@@ -705,14 +705,14 @@ microblaze_elf_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED,
+ r_type = ELF64_R_TYPE (dst->r_info);
+ if (r_type >= R_MICROBLAZE_max)
+ {
+- (*_bfd_error_handler) (_("%pB: unrecognised MicroBlaze reloc number: %d"),
++ _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
+ abfd, r_type);
+ bfd_set_error (bfd_error_bad_value);
+ return FALSE;
+ }
+
+ cache_ptr->howto = microblaze_elf_howto_table [r_type];
+- return TRUE;
++ return TRUE;
+ }
+
+ /* Microblaze ELF local labels start with 'L.' or '$L', not '.L'. */
+@@ -1560,7 +1560,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ else
+ {
+ BFD_FAIL ();
+- (*_bfd_error_handler)
++ _bfd_error_handler
+ (_("%pB: probably compiled without -fPIC?"),
+ input_bfd);
+ bfd_set_error (bfd_error_bad_value);
+@@ -2554,6 +2554,7 @@ microblaze_elf_check_relocs (bfd * abfd,
+ goto dogottls;
+ case R_MICROBLAZE_TLSLD:
+ tls_type |= (TLS_TLS | TLS_LD);
++ /* Fall through. */
+ dogottls:
+ sec->has_tls_reloc = 1;
+ /* Fall through. */
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0034-Add-initial-port-of-linux-gdbserver.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0034-Add-initial-port-of-linux-gdbserver.patch
new file mode 100644
index 0000000..ff1c606
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0034-Add-initial-port-of-linux-gdbserver.patch
@@ -0,0 +1,500 @@
+From c5eee33cd39dbb9c44bdad2025a5c848139c55f2 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 23 Jan 2017 19:07:44 +0530
+Subject: [PATCH 34/40] Add initial port of linux gdbserver add
+ gdb_proc_service_h to gdbserver microblaze-linux
+
+gdbserver needs to initialise the microblaze registers
+
+other archs use this step to run a *_arch_setup() to carry out all
+architecture specific setup - may need to add in future
+
+ * add linux-ptrace.o to gdbserver configure
+ * Update breakpoint opcode
+ * fix segfault on connecting gdbserver
+ * add microblaze_linux_memory_remove_breakpoint
+ * add set_solib_svr4_fetch_link_map_offsets
+ * add set_gdbarch_fetch_tls_load_module_address
+ * Force reading of r0 as 0, prevent stores
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+---
+ gdb/configure.host | 3 +
+ gdb/features/microblaze-linux.xml | 12 ++
+ gdb/gdbserver/Makefile.in | 4 +
+ gdb/gdbserver/configure.srv | 8 ++
+ gdb/gdbserver/linux-microblaze-low.c | 189 +++++++++++++++++++++++++++
+ gdb/microblaze-linux-tdep.c | 29 +++-
+ gdb/microblaze-tdep.c | 35 ++++-
+ gdb/microblaze-tdep.h | 4 +-
+ gdb/regformats/reg-microblaze.dat | 41 ++++++
+ 9 files changed, 322 insertions(+), 3 deletions(-)
+ create mode 100644 gdb/features/microblaze-linux.xml
+ create mode 100644 gdb/gdbserver/linux-microblaze-low.c
+ create mode 100644 gdb/regformats/reg-microblaze.dat
+
+diff --git a/gdb/configure.host b/gdb/configure.host
+index ce528237291..cf1a08e8b28 100644
+--- a/gdb/configure.host
++++ b/gdb/configure.host
+@@ -65,6 +65,7 @@ hppa*) gdb_host_cpu=pa ;;
+ i[34567]86*) gdb_host_cpu=i386 ;;
+ m68*) gdb_host_cpu=m68k ;;
+ mips*) gdb_host_cpu=mips ;;
++microblaze*) gdb_host_cpu=microblaze ;;
+ powerpc* | rs6000) gdb_host_cpu=powerpc ;;
+ sparcv9 | sparc64) gdb_host_cpu=sparc ;;
+ s390*) gdb_host_cpu=s390 ;;
+@@ -133,6 +134,8 @@ mips*-*-netbsd* | mips*-*-knetbsd*-gnu)
+ mips*-*-freebsd*) gdb_host=fbsd ;;
+ mips64*-*-openbsd*) gdb_host=obsd64 ;;
+
++microblaze*-*linux*) gdb_host=linux ;;
++
+ powerpc-*-aix* | rs6000-*-* | powerpc64-*-aix*)
+ gdb_host=aix ;;
+ powerpc*-*-freebsd*) gdb_host=fbsd ;;
+diff --git a/gdb/features/microblaze-linux.xml b/gdb/features/microblaze-linux.xml
+new file mode 100644
+index 00000000000..8983e66eb3d
+--- /dev/null
++++ b/gdb/features/microblaze-linux.xml
+@@ -0,0 +1,12 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++ Copying and distribution of this file, with or without modification,
++ are permitted in any medium without royalty provided the copyright
++ notice and this notice are preserved. -->
++
++<!DOCTYPE target SYSTEM "gdb-target.dtd">
++<target>
++ <osabi>GNU/Linux</osabi>
++ <xi:include href="microblaze-core.xml"/>
++</target>
+diff --git a/gdb/gdbserver/Makefile.in b/gdb/gdbserver/Makefile.in
+index 16a9f2fd380..fb4762a22d5 100644
+--- a/gdb/gdbserver/Makefile.in
++++ b/gdb/gdbserver/Makefile.in
+@@ -172,6 +172,7 @@ SFILES = \
+ $(srcdir)/linux-low.c \
+ $(srcdir)/linux-m32r-low.c \
+ $(srcdir)/linux-m68k-low.c \
++ $(srcdir)/linux-microblaze-low.c \
+ $(srcdir)/linux-mips-low.c \
+ $(srcdir)/linux-nios2-low.c \
+ $(srcdir)/linux-ppc-low.c \
+@@ -231,6 +232,7 @@ SFILES = \
+ $(srcdir)/nat/linux-namespaces.c \
+ $(srcdir)/nat/linux-osdata.c \
+ $(srcdir)/nat/linux-personality.c \
++ $(srcdir)/nat/microblaze-linux.c \
+ $(srcdir)/nat/mips-linux-watch.c \
+ $(srcdir)/nat/ppc-linux.c \
+ $(srcdir)/nat/fork-inferior.c \
+@@ -657,6 +659,8 @@ gdbsupport/%.o: ../gdbsupport/%.c
+
+ %-generated.c: ../regformats/rs6000/%.dat | $(regdat_sh)
+ $(ECHO_REGDAT) $(SHELL) $(regdat_sh) $< $@
++microblaze-linux.c : $(srcdir)/../regformats/reg-microblaze.dat $(regdat_sh)
++ $(ECHO_REGDAT) $(SHELL) $(regdat_sh) $(srcdir)/../regformats/reg-microblaze.dat microblaze-linux.c
+
+ #
+ # Dependency tracking.
+diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
+index 1a4ab8e3361..e0d2b2fe04a 100644
+--- a/gdb/gdbserver/configure.srv
++++ b/gdb/gdbserver/configure.srv
+@@ -184,6 +184,14 @@ case "${target}" in
+ srv_linux_usrregs=yes
+ srv_linux_thread_db=yes
+ ;;
++ microblaze*-*-linux*) srv_regobj="microblaze-linux.o"
++ srv_tgtobj="linux-low.o linux-osdata.o linux-microblaze-low.o "
++ srv_tgtobj="${srv_tgtobj} linux-procfs.o linux-ptrace.o"
++ srv_xmlfiles="microblaze-linux.xml"
++ srv_linux_regsets=yes
++ srv_linux_usrregs=yes
++ srv_linux_thread_db=yes
++ ;;
+ powerpc*-*-linux*) srv_regobj="powerpc-32l.o"
+ srv_regobj="${srv_regobj} powerpc-altivec32l.o"
+ srv_regobj="${srv_regobj} powerpc-vsx32l.o"
+diff --git a/gdb/gdbserver/linux-microblaze-low.c b/gdb/gdbserver/linux-microblaze-low.c
+new file mode 100644
+index 00000000000..cba5d6fc585
+--- /dev/null
++++ b/gdb/gdbserver/linux-microblaze-low.c
+@@ -0,0 +1,189 @@
++/* GNU/Linux/Microblaze specific low level interface, for the remote server for
++ GDB.
++ Copyright (C) 1995-2013 Free Software Foundation, Inc.
++
++ This file is part of GDB.
++
++ This program is free software; you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 3 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program. If not, see <http://www.gnu.org/licenses/>. */
++
++#include "server.h"
++#include "linux-low.h"
++
++#include <asm/ptrace.h>
++#include <sys/procfs.h>
++#include <sys/ptrace.h>
++
++#include "gdb_proc_service.h"
++
++static int microblaze_regmap[] =
++ {PT_GPR(0), PT_GPR(1), PT_GPR(2), PT_GPR(3),
++ PT_GPR(4), PT_GPR(5), PT_GPR(6), PT_GPR(7),
++ PT_GPR(8), PT_GPR(9), PT_GPR(10), PT_GPR(11),
++ PT_GPR(12), PT_GPR(13), PT_GPR(14), PT_GPR(15),
++ PT_GPR(16), PT_GPR(17), PT_GPR(18), PT_GPR(19),
++ PT_GPR(20), PT_GPR(21), PT_GPR(22), PT_GPR(23),
++ PT_GPR(24), PT_GPR(25), PT_GPR(26), PT_GPR(27),
++ PT_GPR(28), PT_GPR(29), PT_GPR(30), PT_GPR(31),
++ PT_PC, PT_MSR, PT_EAR, PT_ESR,
++ PT_FSR
++ };
++
++#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0])
++
++/* Defined in auto-generated file microblaze-linux.c. */
++void init_registers_microblaze (void);
++
++static int
++microblaze_cannot_store_register (int regno)
++{
++ if (microblaze_regmap[regno] == -1 || regno == 0)
++ return 1;
++
++ return 0;
++}
++
++static int
++microblaze_cannot_fetch_register (int regno)
++{
++ return 0;
++}
++
++static CORE_ADDR
++microblaze_get_pc (struct regcache *regcache)
++{
++ unsigned long pc;
++
++ collect_register_by_name (regcache, "pc", &pc);
++ return (CORE_ADDR) pc;
++}
++
++static void
++microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc)
++{
++ unsigned long newpc = pc;
++
++ supply_register_by_name (regcache, "pc", &newpc);
++}
++
++/* dbtrap insn */
++/* brki r16, 0x18; */
++static const unsigned long microblaze_breakpoint = 0xba0c0018;
++#define microblaze_breakpoint_len 4
++
++static int
++microblaze_breakpoint_at (CORE_ADDR where)
++{
++ unsigned long insn;
++
++ (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
++ if (insn == microblaze_breakpoint)
++ return 1;
++ /* If necessary, recognize more trap instructions here. GDB only uses the
++ one. */
++ return 0;
++}
++
++static CORE_ADDR
++microblaze_reinsert_addr (struct regcache *regcache)
++{
++ unsigned long pc;
++ collect_register_by_name (regcache, "r15", &pc);
++ return pc;
++}
++
++#ifdef HAVE_PTRACE_GETREGS
++
++static void
++microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
++{
++ int size = register_size (regno);
++
++ memset (buf, 0, sizeof (long));
++
++ if (size < sizeof (long))
++ collect_register (regcache, regno, buf + sizeof (long) - size);
++ else
++ collect_register (regcache, regno, buf);
++}
++
++static void
++microblaze_supply_ptrace_register (struct regcache *regcache,
++ int regno, const char *buf)
++{
++ int size = register_size (regno);
++
++ if (regno == 0) {
++ unsigned long regbuf_0 = 0;
++ /* clobbering r0 so that it is always 0 as enforced by hardware */
++ supply_register (regcache, regno, (const char*)®buf_0);
++ } else {
++ if (size < sizeof (long))
++ supply_register (regcache, regno, buf + sizeof (long) - size);
++ else
++ supply_register (regcache, regno, buf);
++ }
++}
++
++/* Provide only a fill function for the general register set. ps_lgetregs
++ will use this for NPTL support. */
++
++static void microblaze_fill_gregset (struct regcache *regcache, void *buf)
++{
++ int i;
++
++ for (i = 0; i < 32; i++)
++ microblaze_collect_ptrace_register (regcache, i, (char *) buf + microblaze_regmap[i]);
++}
++
++static void
++microblaze_store_gregset (struct regcache *regcache, const void *buf)
++{
++ int i;
++
++ for (i = 0; i < 32; i++)
++ supply_register (regcache, i, (char *) buf + microblaze_regmap[i]);
++}
++
++#endif /* HAVE_PTRACE_GETREGS */
++
++struct regset_info target_regsets[] = {
++#ifdef HAVE_PTRACE_GETREGS
++ { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset },
++ { 0, 0, 0, -1, -1, NULL, NULL },
++#endif /* HAVE_PTRACE_GETREGS */
++ { 0, 0, 0, -1, -1, NULL, NULL }
++};
++
++struct linux_target_ops the_low_target = {
++ init_registers_microblaze,
++ microblaze_num_regs,
++ microblaze_regmap,
++ NULL,
++ microblaze_cannot_fetch_register,
++ microblaze_cannot_store_register,
++ NULL, /* fetch_register */
++ microblaze_get_pc,
++ microblaze_set_pc,
++ (const unsigned char *) µblaze_breakpoint,
++ microblaze_breakpoint_len,
++ microblaze_reinsert_addr,
++ 0,
++ microblaze_breakpoint_at,
++ NULL,
++ NULL,
++ NULL,
++ NULL,
++ microblaze_collect_ptrace_register,
++ microblaze_supply_ptrace_register,
++};
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index 3bb9b5682ac..42c219d32f3 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -37,6 +37,22 @@
+ #include "tramp-frame.h"
+ #include "linux-tdep.h"
+
++static int microblaze_debug_flag = 0;
++
++static void
++microblaze_debug (const char *fmt, ...)
++{
++ if (microblaze_debug_flag)
++ {
++ va_list args;
++
++ va_start (args, fmt);
++ printf_unfiltered ("MICROBLAZE LINUX: ");
++ vprintf_unfiltered (fmt, args);
++ va_end (args);
++ }
++}
++
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ struct bp_target_info *bp_tgt)
+@@ -50,13 +66,20 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ /* Determine appropriate breakpoint contents and size for this address. */
+ bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
+
++ /* Make sure we see the memory breakpoints. */
++ scoped_restore restore_memory
++ = make_scoped_restore_show_memory_breakpoints (1);
++
+ val = target_read_memory (addr, old_contents, bplen);
+
+ /* If our breakpoint is no longer at the address, this means that the
+ program modified the code on us, so it is wrong to put back the
+ old value. */
+ if (val == 0 && memcmp (bp, old_contents, bplen) == 0)
+- val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++ {
++ val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++ microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr);
++ }
+
+ return val;
+ }
+@@ -129,6 +152,10 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+ /* Trampolines. */
+ tramp_frame_prepend_unwinder (gdbarch,
+ µblaze_linux_sighandler_tramp_frame);
++
++ /* Enable TLS support. */
++ set_gdbarch_fetch_tls_load_module_address (gdbarch,
++ svr4_fetch_objfile_link_map);
+ }
+
+ void
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 17871229c80..0168e4881ed 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -137,7 +137,38 @@ microblaze_fetch_instruction (CORE_ADDR pc)
+ constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT;
+
+ typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint;
+-
++static int
++microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
++ struct bp_target_info *bp_tgt)
++{
++ CORE_ADDR addr = bp_tgt->placed_address;
++ const unsigned char *bp;
++ int val;
++ int bplen;
++ gdb_byte old_contents[BREAKPOINT_MAX];
++
++ /* Determine appropriate breakpoint contents and size for this address. */
++ bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
++ if (bp == NULL)
++ error (_("Software breakpoints not implemented for this target."));
++
++ /* Make sure we see the memory breakpoints. */
++ scoped_restore restore_memory
++ = make_scoped_restore_show_memory_breakpoints (1);
++
++ val = target_read_memory (addr, old_contents, bplen);
++
++ /* If our breakpoint is no longer at the address, this means that the
++ program modified the code on us, so it is wrong to put back the
++ old value. */
++ if (val == 0 && memcmp (bp, old_contents, bplen) == 0)
++ {
++ val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++ microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr);
++ }
++
++ return val;
++}
+
+ /* Allocate and initialize a frame cache. */
+
+@@ -731,6 +762,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ microblaze_breakpoint::kind_from_pc);
+ set_gdbarch_sw_breakpoint_from_kind (gdbarch,
+ microblaze_breakpoint::bp_from_kind);
++ set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
+
+ set_gdbarch_frame_args_skip (gdbarch, 8);
+
+@@ -770,4 +802,5 @@ When non-zero, microblaze specific debugging is enabled."),
+ NULL,
+ &setdebuglist, &showdebuglist);
+
++
+ }
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index 4fbdf9933f0..db0772643dc 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -117,6 +117,8 @@ struct microblaze_frame_cache
+
+ /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used.
+ Only used for native debugging. */
+-#define MICROBLAZE_BREAKPOINT {0xb9, 0xcc, 0x00, 0x60}
++#define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18}
++#define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba}
++
+
+ #endif /* microblaze-tdep.h */
+diff --git a/gdb/regformats/reg-microblaze.dat b/gdb/regformats/reg-microblaze.dat
+new file mode 100644
+index 00000000000..bd8a4384424
+--- /dev/null
++++ b/gdb/regformats/reg-microblaze.dat
+@@ -0,0 +1,41 @@
++name:microblaze
++expedite:r1,pc
++32:r0
++32:r1
++32:r2
++32:r3
++32:r4
++32:r5
++32:r6
++32:r7
++32:r8
++32:r9
++32:r10
++32:r11
++32:r12
++32:r13
++32:r14
++32:r15
++32:r16
++32:r17
++32:r18
++32:r19
++32:r20
++32:r21
++32:r22
++32:r23
++32:r24
++32:r25
++32:r26
++32:r27
++32:r28
++32:r29
++32:r30
++32:r31
++32:pc
++32:msr
++32:ear
++32:esr
++32:fsr
++32:slr
++32:shr
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0035-Initial-port-of-core-reading-support.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0035-Initial-port-of-core-reading-support.patch
new file mode 100644
index 0000000..171a0bf
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0035-Initial-port-of-core-reading-support.patch
@@ -0,0 +1,298 @@
+From f8cbcd1ef78f6ce9ae8d3382bf2bb0d1e770d201 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 24 Jan 2017 14:55:56 +0530
+Subject: [PATCH 35/40] Initial port of core reading support Added support for
+ reading notes in linux core dumps Support for reading of PRSTATUS and PSINFO
+ information for rebuilding ".reg" sections of core dumps at run time.
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+---
+ bfd/elf32-microblaze.c | 84 +++++++++++++++++++++++++++++++++++++
+ gdb/configure.tgt | 2 +-
+ gdb/microblaze-linux-tdep.c | 17 +++++++-
+ gdb/microblaze-tdep.c | 48 +++++++++++++++++++++
+ gdb/microblaze-tdep.h | 27 ++++++++++++
+ 5 files changed, 176 insertions(+), 2 deletions(-)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index 04816a4a187..cb7a98d307e 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -767,6 +767,87 @@ microblaze_elf_is_local_label_name (bfd *abfd, const char *name)
+ return _bfd_elf_is_local_label_name (abfd, name);
+ }
+
++/* Support for core dump NOTE sections. */
++static bfd_boolean
++microblaze_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
++{
++ int offset;
++ unsigned int size;
++
++ switch (note->descsz)
++ {
++ default:
++ return FALSE;
++
++ case 228: /* Linux/MicroBlaze */
++ /* pr_cursig */
++ elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
++
++ /* pr_pid */
++ elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24);
++
++ /* pr_reg */
++ offset = 72;
++ size = 50 * 4;
++
++ break;
++ }
++
++ /* Make a ".reg/999" section. */
++ return _bfd_elfcore_make_pseudosection (abfd, ".reg",
++ size, note->descpos + offset);
++}
++
++static bfd_boolean
++microblaze_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
++{
++ switch (note->descsz)
++ {
++ default:
++ return FALSE;
++
++ case 128: /* Linux/MicroBlaze elf_prpsinfo */
++ elf_tdata (abfd)->core->program
++ = _bfd_elfcore_strndup (abfd, note->descdata + 32, 16);
++ elf_tdata (abfd)->core->command
++ = _bfd_elfcore_strndup (abfd, note->descdata + 48, 80);
++ }
++
++ /* Note that for some reason, a spurious space is tacked
++ onto the end of the args in some (at least one anyway)
++ implementations, so strip it off if it exists. */
++
++ {
++ char *command = elf_tdata (abfd)->core->command;
++ int n = strlen (command);
++
++ if (0 < n && command[n - 1] == ' ')
++ command[n - 1] = '\0';
++ }
++
++ return TRUE;
++}
++
++/* The microblaze linker (like many others) needs to keep track of
++ the number of relocs that it decides to copy as dynamic relocs in
++ check_relocs for each symbol. This is so that it can later discard
++ them if they are found to be unnecessary. We store the information
++ in a field extending the regular ELF linker hash table. */
++
++struct elf32_mb_dyn_relocs
++{
++ struct elf32_mb_dyn_relocs *next;
++
++ /* The input section of the reloc. */
++ asection *sec;
++
++ /* Total number of relocs copied for the input section. */
++ bfd_size_type count;
++
++ /* Number of pc-relative relocs copied for the input section. */
++ bfd_size_type pc_count;
++};
++
+ /* ELF linker hash entry. */
+
+ struct elf32_mb_link_hash_entry
+@@ -3673,4 +3754,7 @@ microblaze_elf_add_symbol_hook (bfd *abfd,
+ #define elf_backend_size_dynamic_sections microblaze_elf_size_dynamic_sections
+ #define elf_backend_add_symbol_hook microblaze_elf_add_symbol_hook
+
++#define elf_backend_grok_prstatus microblaze_elf_grok_prstatus
++#define elf_backend_grok_psinfo microblaze_elf_grok_psinfo
++
+ #include "elf32-target.h"
+diff --git a/gdb/configure.tgt b/gdb/configure.tgt
+index caa42be1c01..f0386568460 100644
+--- a/gdb/configure.tgt
++++ b/gdb/configure.tgt
+@@ -400,7 +400,7 @@ mep-*-*)
+
+ microblaze*-linux-*|microblaze*-*-linux*)
+ # Target: Xilinx MicroBlaze running Linux
+- gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o \
++ gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o glibc-tdep.o \
+ symfile-mem.o linux-tdep.o"
+ gdb_sim=../sim/microblaze/libsim.a
+ ;;
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index 42c219d32f3..0afb6efeba3 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -36,6 +36,7 @@
+ #include "frame-unwind.h"
+ #include "tramp-frame.h"
+ #include "linux-tdep.h"
++#include "glibc-tdep.h"
+
+ static int microblaze_debug_flag = 0;
+
+@@ -135,11 +136,14 @@ static struct tramp_frame microblaze_linux_sighandler_tramp_frame =
+ microblaze_linux_sighandler_cache_init
+ };
+
+-
+ static void
+ microblaze_linux_init_abi (struct gdbarch_info info,
+ struct gdbarch *gdbarch)
+ {
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++
++ tdep->sizeof_gregset = 200;
++
+ linux_init_abi (info, gdbarch);
+
+ set_gdbarch_memory_remove_breakpoint (gdbarch,
+@@ -153,6 +157,17 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+ tramp_frame_prepend_unwinder (gdbarch,
+ µblaze_linux_sighandler_tramp_frame);
+
++ /* BFD target for core files. */
++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++ else
++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++
++
++ /* Shared library handling. */
++ set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
++ set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
++
+ /* Enable TLS support. */
+ set_gdbarch_fetch_tls_load_module_address (gdbarch,
+ svr4_fetch_objfile_link_map);
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 0168e4881ed..98944f38d2a 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -677,6 +677,43 @@ microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
+ tdesc_microblaze_with_stack_protect);
+ }
+
++void
++microblaze_supply_gregset (const struct regset *regset,
++ struct regcache *regcache,
++ int regnum, const void *gregs)
++{
++ const unsigned int *regs = (const unsigned int *)gregs;
++ if (regnum >= 0)
++ regcache->raw_supply (regnum, regs + regnum);
++
++ if (regnum == -1) {
++ int i;
++
++ for (i = 0; i < 50; i++) {
++ regcache->raw_supply (i, regs + i);
++ }
++ }
++}
++
++
++/* Return the appropriate register set for the core section identified
++ by SECT_NAME and SECT_SIZE. */
++
++static void
++microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch,
++ iterate_over_regset_sections_cb *cb,
++ void *cb_data,
++ const struct regcache *regcache)
++{
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++
++ cb(".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, cb_data);
++
++ cb(".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
++}
++
++
++
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ {
+@@ -733,6 +770,10 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ tdep = XCNEW (struct gdbarch_tdep);
+ gdbarch = gdbarch_alloc (&info, tdep);
+
++ tdep->gregset = NULL;
++ tdep->sizeof_gregset = 0;
++ tdep->fpregset = NULL;
++ tdep->sizeof_fpregset = 0;
+ set_gdbarch_long_double_bit (gdbarch, 128);
+
+ set_gdbarch_num_regs (gdbarch, MICROBLAZE_NUM_REGS);
+@@ -781,6 +822,13 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
+ if (tdesc_data != NULL)
+ tdesc_use_registers (gdbarch, tdesc, tdesc_data);
++ //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer);
++
++ /* If we have register sets, enable the generic core file support. */
++ if (tdep->gregset) {
++ set_gdbarch_iterate_over_regset_sections (gdbarch,
++ microblaze_iterate_over_regset_sections);
++ }
+
+ return gdbarch;
+ }
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index db0772643dc..8f41ba19351 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -22,8 +22,22 @@
+
+
+ /* Microblaze architecture-specific information. */
++struct microblaze_gregset
++{
++ unsigned int gregs[32];
++ unsigned int fpregs[32];
++ unsigned int pregs[16];
++};
++
+ struct gdbarch_tdep
+ {
++ int dummy; // declare something.
++
++ /* Register sets. */
++ struct regset *gregset;
++ size_t sizeof_gregset;
++ struct regset *fpregset;
++ size_t sizeof_fpregset;
+ };
+
+ /* Register numbers. */
+@@ -120,5 +134,18 @@ struct microblaze_frame_cache
+ #define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18}
+ #define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba}
+
++extern void microblaze_supply_gregset (const struct regset *regset,
++ struct regcache *regcache,
++ int regnum, const void *gregs);
++extern void microblaze_collect_gregset (const struct regset *regset,
++ const struct regcache *regcache,
++ int regnum, void *gregs);
++extern void microblaze_supply_fpregset (struct regcache *regcache,
++ int regnum, const void *fpregs);
++extern void microblaze_collect_fpregset (const struct regcache *regcache,
++ int regnum, void *fpregs);
++
++extern const struct regset * microblaze_regset_from_core_section (struct gdbarch *gdbarch,
++ const char *sect_name, size_t sect_size);
+
+ #endif /* microblaze-tdep.h */
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0036-Fix-debug-message-when-register-is-unavailable.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0036-Fix-debug-message-when-register-is-unavailable.patch
new file mode 100644
index 0000000..f0c182d
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0036-Fix-debug-message-when-register-is-unavailable.patch
@@ -0,0 +1,40 @@
+From 41fd9d3645d610ff65171e9a44427711232cb4b8 Mon Sep 17 00:00:00 2001
+From: Nathan Rossi <nathan.rossi@petalogix.com>
+Date: Tue, 8 May 2012 18:11:17 +1000
+Subject: [PATCH 36/40] Fix debug message when register is unavailable
+
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+---
+ gdb/frame.c | 13 ++++++++++---
+ 1 file changed, 10 insertions(+), 3 deletions(-)
+
+diff --git a/gdb/frame.c b/gdb/frame.c
+index c746a6a231e..571722c7351 100644
+--- a/gdb/frame.c
++++ b/gdb/frame.c
+@@ -1255,12 +1255,19 @@ frame_unwind_register_value (frame_info *next_frame, int regnum)
+ else
+ {
+ int i;
+- const gdb_byte *buf = value_contents (value);
++ const gdb_byte *buf = NULL;
++ if (value_entirely_available(value)) {
++ buf = value_contents (value);
++ }
+
+ fprintf_unfiltered (gdb_stdlog, " bytes=");
+ fprintf_unfiltered (gdb_stdlog, "[");
+- for (i = 0; i < register_size (gdbarch, regnum); i++)
+- fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]);
++ if (buf != NULL) {
++ for (i = 0; i < register_size (gdbarch, regnum); i++)
++ fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]);
++ } else {
++ fprintf_unfiltered (gdb_stdlog, "unavailable");
++ }
+ fprintf_unfiltered (gdb_stdlog, "]");
+ }
+ }
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch
new file mode 100644
index 0000000..1e0bffb
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch
@@ -0,0 +1,32 @@
+From 7b22823ae82445f52384e6c0bd85431294868eb7 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Mon, 16 Dec 2013 16:37:32 +1000
+Subject: [PATCH 37/40] microblaze: Add build_gdbserver=yes to top level
+ configure.tgt
+
+For Microblaze linux toolchains, set the build_gdbserver=yes
+to allow driving gdbserver configuration from the upper level
+
+This patch has been absorbed into the original patch to add
+linux gdbserver support for Microblaze.
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gdb/configure.tgt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/gdb/configure.tgt b/gdb/configure.tgt
+index f0386568460..ae238c17cd5 100644
+--- a/gdb/configure.tgt
++++ b/gdb/configure.tgt
+@@ -408,6 +408,7 @@ microblaze*-*-*)
+ # Target: Xilinx MicroBlaze running standalone
+ gdb_target_obs="microblaze-tdep.o"
+ gdb_sim=../sim/microblaze/libsim.a
++ build_gdbserver=yes
+ ;;
+
+ mips*-*-linux*)
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0038-Initial-support-for-native-gdb.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0038-Initial-support-for-native-gdb.patch
new file mode 100644
index 0000000..afde3ce
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0038-Initial-support-for-native-gdb.patch
@@ -0,0 +1,492 @@
+From a06b9c4860af1f8f18ccb7c0653c76c623636034 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@petalogix.com>
+Date: Fri, 20 Jul 2012 15:18:35 +1000
+Subject: [PATCH 38/40] Initial support for native gdb
+
+microblaze: Follow PPC method of getting setting registers
+using PTRACE PEEK/POKE
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+---
+ gdb/Makefile.in | 2 +
+ gdb/config/microblaze/linux.mh | 9 +
+ gdb/microblaze-linux-nat.c | 431 +++++++++++++++++++++++++++++++++
+ 3 files changed, 442 insertions(+)
+ create mode 100644 gdb/config/microblaze/linux.mh
+ create mode 100644 gdb/microblaze-linux-nat.c
+
+diff --git a/gdb/Makefile.in b/gdb/Makefile.in
+index c3e074b21fe..cbcd8f43326 100644
+--- a/gdb/Makefile.in
++++ b/gdb/Makefile.in
+@@ -1337,6 +1337,7 @@ HFILES_NO_SRCDIR = \
+ memory-map.h \
+ memrange.h \
+ microblaze-tdep.h \
++ microblaze-linux-tdep.h \
+ mips-linux-tdep.h \
+ mips-nbsd-tdep.h \
+ mips-tdep.h \
+@@ -2261,6 +2262,7 @@ ALLDEPFILES = \
+ m68k-tdep.c \
+ microblaze-linux-tdep.c \
+ microblaze-tdep.c \
++ microblaze-linux-nat.c \
+ mingw-hdep.c \
+ mips-fbsd-nat.c \
+ mips-fbsd-tdep.c \
+diff --git a/gdb/config/microblaze/linux.mh b/gdb/config/microblaze/linux.mh
+new file mode 100644
+index 00000000000..a4eaf540e1d
+--- /dev/null
++++ b/gdb/config/microblaze/linux.mh
+@@ -0,0 +1,9 @@
++# Host: Microblaze, running Linux
++
++NAT_FILE= config/nm-linux.h
++NATDEPFILES= inf-ptrace.o fork-child.o \
++ microblaze-linux-nat.o proc-service.o linux-thread-db.o \
++ linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o
++NAT_CDEPS = $(srcdir)/proc-service.list
++
++LOADLIBES = -ldl $(RDYNAMIC)
+diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c
+new file mode 100644
+index 00000000000..e9b8c9c5221
+--- /dev/null
++++ b/gdb/microblaze-linux-nat.c
+@@ -0,0 +1,431 @@
++/* Microblaze GNU/Linux native support.
++
++ Copyright (C) 1988-1989, 1991-1992, 1994, 1996, 2000-2012 Free
++ Software Foundation, Inc.
++
++ This file is part of GDB.
++
++ This program is free software; you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 3 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program. If not, see <http://www.gnu.org/licenses/>. */
++
++#include "defs.h"
++#include "arch-utils.h"
++#include "dis-asm.h"
++#include "frame.h"
++#include "trad-frame.h"
++#include "symtab.h"
++#include "value.h"
++#include "gdbcmd.h"
++#include "breakpoint.h"
++#include "inferior.h"
++#include "regcache.h"
++#include "target.h"
++#include "frame.h"
++#include "frame-base.h"
++#include "frame-unwind.h"
++#include "dwarf2-frame.h"
++#include "osabi.h"
++
++#include "gdb_assert.h"
++#include "gdb_string.h"
++#include "target-descriptions.h"
++#include "opcodes/microblaze-opcm.h"
++#include "opcodes/microblaze-dis.h"
++
++#include "linux-nat.h"
++#include "target-descriptions.h"
++
++#include <sys/user.h>
++#include <sys/utsname.h>
++#include <sys/procfs.h>
++#include <sys/ptrace.h>
++
++/* Prototypes for supply_gregset etc. */
++#include "gregset.h"
++
++#include "microblaze-tdep.h"
++
++#include <elf/common.h>
++#include "auxv.h"
++
++/* Defines ps_err_e, struct ps_prochandle. */
++#include "gdb_proc_service.h"
++
++/* On GNU/Linux, threads are implemented as pseudo-processes, in which
++ case we may be tracing more than one process at a time. In that
++ case, inferior_ptid will contain the main process ID and the
++ individual thread (process) ID. get_thread_id () is used to get
++ the thread id if it's available, and the process id otherwise. */
++
++int
++get_thread_id (ptid_t ptid)
++{
++ int tid = TIDGET (ptid);
++ if (0 == tid)
++ tid = PIDGET (ptid);
++ return tid;
++}
++
++#define GET_THREAD_ID(PTID) get_thread_id (PTID)
++
++/* Non-zero if our kernel may support the PTRACE_GETREGS and
++ PTRACE_SETREGS requests, for reading and writing the
++ general-purpose registers. Zero if we've tried one of
++ them and gotten an error. */
++int have_ptrace_getsetregs = 1;
++
++static int
++microblaze_register_u_addr (struct gdbarch *gdbarch, int regno)
++{
++ int u_addr = -1;
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
++ interface, and not the wordsize of the program's ABI. */
++ int wordsize = sizeof (long);
++
++ /* General purpose registers occupy 1 slot each in the buffer. */
++ if (regno >= MICROBLAZE_R0_REGNUM
++ && regno <= MICROBLAZE_FSR_REGNUM)
++ u_addr = (regno * wordsize);
++
++ return u_addr;
++}
++
++
++static void
++fetch_register (struct regcache *regcache, int tid, int regno)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ /* This isn't really an address. But ptrace thinks of it as one. */
++ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
++ int bytes_transferred;
++ unsigned int offset; /* Offset of registers within the u area. */
++ char buf[MAX_REGISTER_SIZE];
++
++ if (regaddr == -1)
++ {
++ memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */
++ regcache_raw_supply (regcache, regno, buf);
++ return;
++ }
++
++ /* Read the raw register using sizeof(long) sized chunks. On a
++ 32-bit platform, 64-bit floating-point registers will require two
++ transfers. */
++ for (bytes_transferred = 0;
++ bytes_transferred < register_size (gdbarch, regno);
++ bytes_transferred += sizeof (long))
++ {
++ long l;
++
++ errno = 0;
++ l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
++ regaddr += sizeof (long);
++ if (errno != 0)
++ {
++ char message[128];
++ sprintf (message, "reading register %s (#%d)",
++ gdbarch_register_name (gdbarch, regno), regno);
++ perror_with_name (message);
++ }
++ memcpy (&buf[bytes_transferred], &l, sizeof (l));
++ }
++
++ /* Now supply the register. Keep in mind that the regcache's idea
++ of the register's size may not be a multiple of sizeof
++ (long). */
++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
++ {
++ /* Little-endian values are always found at the left end of the
++ bytes transferred. */
++ regcache_raw_supply (regcache, regno, buf);
++ }
++ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++ {
++ /* Big-endian values are found at the right end of the bytes
++ transferred. */
++ size_t padding = (bytes_transferred - register_size (gdbarch, regno));
++ regcache_raw_supply (regcache, regno, buf + padding);
++ }
++ else
++ internal_error (__FILE__, __LINE__,
++ _("fetch_register: unexpected byte order: %d"),
++ gdbarch_byte_order (gdbarch));
++}
++
++/* This function actually issues the request to ptrace, telling
++ it to get all general-purpose registers and put them into the
++ specified regset.
++
++ If the ptrace request does not exist, this function returns 0
++ and properly sets the have_ptrace_* flag. If the request fails,
++ this function calls perror_with_name. Otherwise, if the request
++ succeeds, then the regcache gets filled and 1 is returned. */
++static int
++fetch_all_gp_regs (struct regcache *regcache, int tid)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ gdb_gregset_t gregset;
++
++ if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
++ {
++ if (errno == EIO)
++ {
++ have_ptrace_getsetregs = 0;
++ return 0;
++ }
++ perror_with_name (_("Couldn't get general-purpose registers."));
++ }
++
++ supply_gregset (regcache, (const gdb_gregset_t *) &gregset);
++
++ return 1;
++}
++
++
++/* This is a wrapper for the fetch_all_gp_regs function. It is
++ responsible for verifying if this target has the ptrace request
++ that can be used to fetch all general-purpose registers at one
++ shot. If it doesn't, then we should fetch them using the
++ old-fashioned way, which is to iterate over the registers and
++ request them one by one. */
++static void
++fetch_gp_regs (struct regcache *regcache, int tid)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ int i;
++
++ if (have_ptrace_getsetregs)
++ if (fetch_all_gp_regs (regcache, tid))
++ return;
++
++ /* If we've hit this point, it doesn't really matter which
++ architecture we are using. We just need to read the
++ registers in the "old-fashioned way". */
++ for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)
++ fetch_register (regcache, tid, i);
++}
++
++
++static void
++store_register (const struct regcache *regcache, int tid, int regno)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ /* This isn't really an address. But ptrace thinks of it as one. */
++ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
++ int i;
++ size_t bytes_to_transfer;
++ char buf[MAX_REGISTER_SIZE];
++
++ if (regaddr == -1)
++ return;
++
++ /* First collect the register. Keep in mind that the regcache's
++ idea of the register's size may not be a multiple of sizeof
++ (long). */
++ memset (buf, 0, sizeof buf);
++ bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
++ {
++ /* Little-endian values always sit at the left end of the buffer. */
++ regcache_raw_collect (regcache, regno, buf);
++ }
++ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++ {
++ /* Big-endian values sit at the right end of the buffer. */
++ size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
++ regcache_raw_collect (regcache, regno, buf + padding);
++ }
++
++ for (i = 0; i < bytes_to_transfer; i += sizeof (long))
++ {
++ long l;
++
++ memcpy (&l, &buf[i], sizeof (l));
++ errno = 0;
++ ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l);
++ regaddr += sizeof (long);
++
++ if (errno != 0)
++ {
++ char message[128];
++ sprintf (message, "writing register %s (#%d)",
++ gdbarch_register_name (gdbarch, regno), regno);
++ perror_with_name (message);
++ }
++ }
++}
++
++/* This function actually issues the request to ptrace, telling
++ it to store all general-purpose registers present in the specified
++ regset.
++
++ If the ptrace request does not exist, this function returns 0
++ and properly sets the have_ptrace_* flag. If the request fails,
++ this function calls perror_with_name. Otherwise, if the request
++ succeeds, then the regcache is stored and 1 is returned. */
++static int
++store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ gdb_gregset_t gregset;
++
++ if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
++ {
++ if (errno == EIO)
++ {
++ have_ptrace_getsetregs = 0;
++ return 0;
++ }
++ perror_with_name (_("Couldn't get general-purpose registers."));
++ }
++
++ fill_gregset (regcache, &gregset, regno);
++
++ if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0)
++ {
++ if (errno == EIO)
++ {
++ have_ptrace_getsetregs = 0;
++ return 0;
++ }
++ perror_with_name (_("Couldn't set general-purpose registers."));
++ }
++
++ return 1;
++}
++
++/* This is a wrapper for the store_all_gp_regs function. It is
++ responsible for verifying if this target has the ptrace request
++ that can be used to store all general-purpose registers at one
++ shot. If it doesn't, then we should store them using the
++ old-fashioned way, which is to iterate over the registers and
++ store them one by one. */
++static void
++store_gp_regs (const struct regcache *regcache, int tid, int regno)
++{
++ struct gdbarch *gdbarch = get_regcache_arch (regcache);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++ int i;
++
++ if (have_ptrace_getsetregs)
++ if (store_all_gp_regs (regcache, tid, regno))
++ return;
++
++ /* If we hit this point, it doesn't really matter which
++ architecture we are using. We just need to store the
++ registers in the "old-fashioned way". */
++ for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)
++ store_register (regcache, tid, i);
++}
++
++
++/* Fetch registers from the child process. Fetch all registers if
++ regno == -1, otherwise fetch all general registers or all floating
++ point registers depending upon the value of regno. */
++
++static void
++microblaze_linux_fetch_inferior_registers (struct target_ops *ops,
++ struct regcache *regcache, int regno)
++{
++ /* Get the thread id for the ptrace call. */
++ int tid = GET_THREAD_ID (inferior_ptid);
++
++ if (regno == -1)
++ fetch_gp_regs (regcache, tid);
++ else
++ fetch_register (regcache, tid, regno);
++}
++
++/* Store registers back into the inferior. Store all registers if
++ regno == -1, otherwise store all general registers or all floating
++ point registers depending upon the value of regno. */
++
++static void
++microblaze_linux_store_inferior_registers (struct target_ops *ops,
++ struct regcache *regcache, int regno)
++{
++ /* Get the thread id for the ptrace call. */
++ int tid = GET_THREAD_ID (inferior_ptid);
++
++ if (regno >= 0)
++ store_register (regcache, tid, regno);
++ else
++ store_gp_regs (regcache, tid, -1);
++}
++
++/* Wrapper functions for the standard regset handling, used by
++ thread debugging. */
++
++void
++fill_gregset (const struct regcache *regcache,
++ gdb_gregset_t *gregsetp, int regno)
++{
++ microblaze_collect_gregset (NULL, regcache, regno, gregsetp);
++}
++
++void
++supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
++{
++ microblaze_supply_gregset (NULL, regcache, -1, gregsetp);
++}
++
++void
++fill_fpregset (const struct regcache *regcache,
++ gdb_fpregset_t *fpregsetp, int regno)
++{
++ /* FIXME. */
++}
++
++void
++supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
++{
++ /* FIXME. */
++}
++
++static const struct target_desc *
++microblaze_linux_read_description (struct target_ops *ops)
++{
++ CORE_ADDR microblaze_hwcap = 0;
++
++ if (target_auxv_search (ops, AT_HWCAP, µblaze_hwcap) != 1)
++ return NULL;
++
++ return NULL;
++}
++
++
++void _initialize_microblaze_linux_nat (void);
++
++void
++_initialize_microblaze_linux_nat (void)
++{
++ struct target_ops *t;
++
++ /* Fill in the generic GNU/Linux methods. */
++ t = linux_target ();
++
++ /* Add our register access methods. */
++ t->to_fetch_registers = microblaze_linux_fetch_inferior_registers;
++ t->to_store_registers = microblaze_linux_store_inferior_registers;
++
++ t->to_read_description = microblaze_linux_read_description;
++
++ /* Register the target. */
++ linux_nat_add_target (t);
++}
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0039-Fixing-the-issues-related-to-GDB-7.12.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0039-Fixing-the-issues-related-to-GDB-7.12.patch
new file mode 100644
index 0000000..fb4b35e
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0039-Fixing-the-issues-related-to-GDB-7.12.patch
@@ -0,0 +1,216 @@
+From f13ffe15c10e5d4b5c87761ae9735144d4c8da17 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Fri, 17 Feb 2017 14:09:40 +0530
+Subject: [PATCH 39/40] Fixing the issues related to GDB-7.12
+
+added all the required function which are new in 7.12 and removed
+few deprecated functions from 7.6
+---
+ gdb/config/microblaze/linux.mh | 4 +-
+ gdb/gdbserver/configure.srv | 3 +-
+ gdb/gdbserver/linux-microblaze-low.c | 97 ++++++++++++++++++++++++----
+ gdb/microblaze-tdep.h | 1 +
+ 4 files changed, 89 insertions(+), 16 deletions(-)
+
+diff --git a/gdb/config/microblaze/linux.mh b/gdb/config/microblaze/linux.mh
+index a4eaf540e1d..74a53b854a4 100644
+--- a/gdb/config/microblaze/linux.mh
++++ b/gdb/config/microblaze/linux.mh
+@@ -1,9 +1,11 @@
+ # Host: Microblaze, running Linux
+
++#linux-nat.o linux-waitpid.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o
+ NAT_FILE= config/nm-linux.h
+ NATDEPFILES= inf-ptrace.o fork-child.o \
+ microblaze-linux-nat.o proc-service.o linux-thread-db.o \
+- linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o
++ linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o \
++ linux-waitpid.o linux-personality.o linux-namespaces.o
+ NAT_CDEPS = $(srcdir)/proc-service.list
+
+ LOADLIBES = -ldl $(RDYNAMIC)
+diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
+index e0d2b2fe04a..26db2dd2461 100644
+--- a/gdb/gdbserver/configure.srv
++++ b/gdb/gdbserver/configure.srv
+@@ -185,8 +185,7 @@ case "${target}" in
+ srv_linux_thread_db=yes
+ ;;
+ microblaze*-*-linux*) srv_regobj="microblaze-linux.o"
+- srv_tgtobj="linux-low.o linux-osdata.o linux-microblaze-low.o "
+- srv_tgtobj="${srv_tgtobj} linux-procfs.o linux-ptrace.o"
++ srv_tgtobj="$srv_linux_obj linux-microblaze-low.o "
+ srv_xmlfiles="microblaze-linux.xml"
+ srv_linux_regsets=yes
+ srv_linux_usrregs=yes
+diff --git a/gdb/gdbserver/linux-microblaze-low.c b/gdb/gdbserver/linux-microblaze-low.c
+index cba5d6fc585..a2733f3c21c 100644
+--- a/gdb/gdbserver/linux-microblaze-low.c
++++ b/gdb/gdbserver/linux-microblaze-low.c
+@@ -39,10 +39,11 @@ static int microblaze_regmap[] =
+ PT_FSR
+ };
+
+-#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0])
++#define microblaze_num_regs (sizeof (microblaze_regmap) / sizeof (microblaze_regmap[0]))
+
+ /* Defined in auto-generated file microblaze-linux.c. */
+ void init_registers_microblaze (void);
++extern const struct target_desc *tdesc_microblaze;
+
+ static int
+ microblaze_cannot_store_register (int regno)
+@@ -81,6 +82,15 @@ microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc)
+ static const unsigned long microblaze_breakpoint = 0xba0c0018;
+ #define microblaze_breakpoint_len 4
+
++/* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
++
++static const gdb_byte *
++microblaze_sw_breakpoint_from_kind (int kind, int *size)
++{
++ *size = microblaze_breakpoint_len;
++ return (const gdb_byte *) µblaze_breakpoint;
++}
++
+ static int
+ microblaze_breakpoint_at (CORE_ADDR where)
+ {
+@@ -107,7 +117,7 @@ microblaze_reinsert_addr (struct regcache *regcache)
+ static void
+ microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
+ {
+- int size = register_size (regno);
++ int size = register_size (regcache->tdesc, regno);
+
+ memset (buf, 0, sizeof (long));
+
+@@ -121,7 +131,7 @@ static void
+ microblaze_supply_ptrace_register (struct regcache *regcache,
+ int regno, const char *buf)
+ {
+- int size = register_size (regno);
++ int size = register_size (regcache->tdesc, regno);
+
+ if (regno == 0) {
+ unsigned long regbuf_0 = 0;
+@@ -157,33 +167,94 @@ microblaze_store_gregset (struct regcache *regcache, const void *buf)
+
+ #endif /* HAVE_PTRACE_GETREGS */
+
+-struct regset_info target_regsets[] = {
++static struct regset_info microblaze_regsets[] = {
+ #ifdef HAVE_PTRACE_GETREGS
+ { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset },
+- { 0, 0, 0, -1, -1, NULL, NULL },
++ { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL },
+ #endif /* HAVE_PTRACE_GETREGS */
+- { 0, 0, 0, -1, -1, NULL, NULL }
++ { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL },
++ NULL_REGSET
+ };
+
++static struct usrregs_info microblaze_usrregs_info =
++ {
++ microblaze_num_regs,
++ microblaze_regmap,
++ };
++
++static struct regsets_info microblaze_regsets_info =
++ {
++ microblaze_regsets, /* regsets */
++ 0, /* num_regsets */
++ NULL, /* disabled_regsets */
++ };
++
++static struct regs_info regs_info =
++ {
++ NULL, /* regset_bitmap */
++ µblaze_usrregs_info,
++ µblaze_regsets_info
++ };
++
++static const struct regs_info *
++microblaze_regs_info (void)
++{
++ return ®s_info;
++}
++
++/* Support for hardware single step. */
++
++static int
++microblaze_supports_hardware_single_step (void)
++{
++ return 1;
++}
++
++
++static void
++microblaze_arch_setup (void)
++{
++ current_process ()->tdesc = tdesc_microblaze;
++}
++
+ struct linux_target_ops the_low_target = {
+- init_registers_microblaze,
+- microblaze_num_regs,
+- microblaze_regmap,
+- NULL,
++ microblaze_arch_setup,
++ microblaze_regs_info,
+ microblaze_cannot_fetch_register,
+ microblaze_cannot_store_register,
+ NULL, /* fetch_register */
+ microblaze_get_pc,
+ microblaze_set_pc,
+- (const unsigned char *) µblaze_breakpoint,
+- microblaze_breakpoint_len,
+- microblaze_reinsert_addr,
++ NULL,
++ microblaze_sw_breakpoint_from_kind,
++ NULL,
+ 0,
+ microblaze_breakpoint_at,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
++ NULL,
+ microblaze_collect_ptrace_register,
+ microblaze_supply_ptrace_register,
++ NULL, /* siginfo_fixup */
++ NULL, /* new_process */
++ NULL, /* new_thread */
++ NULL, /* new_fork */
++ NULL, /* prepare_to_resume */
++ NULL, /* process_qsupported */
++ NULL, /* supports_tracepoints */
++ NULL, /* get_thread_area */
++ NULL, /* install_fast_tracepoint_jump_pad */
++ NULL, /* emit_ops */
++ NULL, /* get_min_fast_tracepoint_insn_len */
++ NULL, /* supports_range_stepping */
++ NULL, /* breakpoint_kind_from_current_state */
++ microblaze_supports_hardware_single_step,
+ };
++
++void
++initialize_low_arch (void)
++{
++ init_registers_microblaze ();
++}
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index 8f41ba19351..d2112dc07e1 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -24,6 +24,7 @@
+ /* Microblaze architecture-specific information. */
+ struct microblaze_gregset
+ {
++ microblaze_gregset() {}
+ unsigned int gregs[32];
+ unsigned int fpregs[32];
+ unsigned int pregs[16];
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0040-Patch-microblaze-Adding-64-bit-MB-support.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0040-Patch-microblaze-Adding-64-bit-MB-support.patch
new file mode 100644
index 0000000..7ac8f07
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0040-Patch-microblaze-Adding-64-bit-MB-support.patch
@@ -0,0 +1,949 @@
+From 4e5a4e94cb1dd61646230100f883bd27a39cd896 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Thu, 31 Jan 2019 14:36:00 +0530
+Subject: [PATCH 40/40] [Patch, microblaze]: Adding 64 bit MB support
+
+Added new architecture to Microblaze 64-bit support to GDB
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+---
+ bfd/archures.c | 2 +
+ bfd/bfd-in2.h | 2 +
+ bfd/cpu-microblaze.c | 16 +-
+ bfd/elf32-microblaze.c | 9 +
+ gdb/features/Makefile | 3 +
+ gdb/features/microblaze-core.xml | 6 +-
+ gdb/features/microblaze-with-stack-protect.c | 4 +-
+ gdb/features/microblaze.c | 6 +-
+ gdb/features/microblaze64-core.xml | 69 +++++++
+ gdb/features/microblaze64-stack-protect.xml | 12 ++
+ .../microblaze64-with-stack-protect.c | 79 ++++++++
+ .../microblaze64-with-stack-protect.xml | 12 ++
+ gdb/features/microblaze64.c | 77 ++++++++
+ gdb/features/microblaze64.xml | 11 ++
+ gdb/microblaze-linux-tdep.c | 29 ++-
+ gdb/microblaze-tdep.c | 176 ++++++++++++++++--
+ gdb/microblaze-tdep.h | 9 +-
+ .../microblaze-with-stack-protect.dat | 4 +-
+ 20 files changed, 504 insertions(+), 40 deletions(-)
+ create mode 100644 gdb/features/microblaze64-core.xml
+ create mode 100644 gdb/features/microblaze64-stack-protect.xml
+ create mode 100644 gdb/features/microblaze64-with-stack-protect.c
+ create mode 100644 gdb/features/microblaze64-with-stack-protect.xml
+ create mode 100644 gdb/features/microblaze64.c
+ create mode 100644 gdb/features/microblaze64.xml
+
+diff --git a/bfd/archures.c b/bfd/archures.c
+index 7866c6095b5..abc1541afe6 100644
+--- a/bfd/archures.c
++++ b/bfd/archures.c
+@@ -513,6 +513,8 @@ DESCRIPTION
+ . bfd_arch_lm32, {* Lattice Mico32. *}
+ .#define bfd_mach_lm32 1
+ . bfd_arch_microblaze,{* Xilinx MicroBlaze. *}
++.#define bfd_mach_microblaze 1
++.#define bfd_mach_microblaze64 2
+ . bfd_arch_tilepro, {* Tilera TILEPro. *}
+ . bfd_arch_tilegx, {* Tilera TILE-Gx. *}
+ .#define bfd_mach_tilepro 1
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 91761bf6964..cc34ce0d8c3 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -1896,6 +1896,8 @@ enum bfd_architecture
+ bfd_arch_lm32, /* Lattice Mico32. */
+ #define bfd_mach_lm32 1
+ bfd_arch_microblaze,/* Xilinx MicroBlaze. */
++#define bfd_mach_microblaze 1
++#define bfd_mach_microblaze64 2
+ bfd_arch_tilepro, /* Tilera TILEPro. */
+ bfd_arch_tilegx, /* Tilera TILE-Gx. */
+ #define bfd_mach_tilepro 1
+diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c
+index 4b48b310c6a..a32c4a33d75 100644
+--- a/bfd/cpu-microblaze.c
++++ b/bfd/cpu-microblaze.c
+@@ -30,8 +30,8 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
+ 64, /* 32 bits in a word. */
+ 64, /* 32 bits in an address. */
+ 8, /* 8 bits in a byte. */
+- bfd_arch_microblaze, /* Architecture. */
+- 0, /* Machine number - 0 for now. */
++ bfd_arch_microblaze, /* Architecture. */
++ bfd_mach_microblaze64, /* 64 bit Machine */
+ "microblaze", /* Architecture name. */
+ "MicroBlaze", /* Printable name. */
+ 3, /* Section align power. */
+@@ -43,11 +43,11 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
+ 0 /* Maximum offset of a reloc from the start of an insn. */
+ },
+ {
+- 32, /* Bits in a word. */
+- 32, /* Bits in an address. */
+- 8, /* Bits in a byte. */
++ 32, /* 32 bits in a word. */
++ 32, /* 32 bits in an address. */
++ 8, /* 8 bits in a byte. */
+ bfd_arch_microblaze, /* Architecture number. */
+- 0, /* Machine number - 0 for now. */
++ bfd_mach_microblaze, /* 32 bit Machine */
+ "microblaze", /* Architecture name. */
+ "MicroBlaze", /* Printable name. */
+ 3, /* Section align power. */
+@@ -64,7 +64,7 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
+ 32, /* 32 bits in an address. */
+ 8, /* 8 bits in a byte. */
+ bfd_arch_microblaze, /* Architecture. */
+- 0, /* Machine number - 0 for now. */
++ bfd_mach_microblaze, /* 32 bit Machine */
+ "microblaze", /* Architecture name. */
+ "MicroBlaze", /* Printable name. */
+ 3, /* Section align power. */
+@@ -80,7 +80,7 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
+ 64, /* 32 bits in an address. */
+ 8, /* 8 bits in a byte. */
+ bfd_arch_microblaze, /* Architecture. */
+- 0, /* Machine number - 0 for now. */
++ bfd_mach_microblaze64, /* 64 bit Machine */
+ "microblaze", /* Architecture name. */
+ "MicroBlaze", /* Printable name. */
+ 3, /* Section align power. */
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index cb7a98d307e..e4a70150190 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -3684,6 +3684,14 @@ microblaze_elf_finish_dynamic_sections (bfd *output_bfd,
+ return TRUE;
+ }
+
++
++static bfd_boolean
++elf_microblaze_object_p (bfd *abfd)
++{
++ /* Set the right machine number for an s390 elf32 file. */
++ return bfd_default_set_arch_mach (abfd, bfd_arch_microblaze, bfd_mach_microblaze);
++}
++
+ /* Hook called by the linker routine which adds symbols from an object
+ file. We use it to put .comm items in .sbss, and not .bss. */
+
+@@ -3756,5 +3764,6 @@ microblaze_elf_add_symbol_hook (bfd *abfd,
+
+ #define elf_backend_grok_prstatus microblaze_elf_grok_prstatus
+ #define elf_backend_grok_psinfo microblaze_elf_grok_psinfo
++#define elf_backend_object_p elf_microblaze_object_p
+
+ #include "elf32-target.h"
+diff --git a/gdb/features/Makefile b/gdb/features/Makefile
+index 9a98b0542c4..438e0c5a3fe 100644
+--- a/gdb/features/Makefile
++++ b/gdb/features/Makefile
+@@ -48,6 +48,7 @@ WHICH = arm/arm-with-iwmmxt arm/arm-with-vfpv2 arm/arm-with-vfpv3 \
+ arm/arm-with-neon \
+ mips-linux mips-dsp-linux \
+ microblaze-with-stack-protect \
++ microblaze64-with-stack-protect \
+ mips64-linux mips64-dsp-linux \
+ nios2-linux \
+ rs6000/powerpc-32 \
+@@ -111,7 +112,9 @@ XMLTOC = \
+ arc-v2.xml \
+ arc-arcompact.xml \
+ microblaze-with-stack-protect.xml \
++ microblaze64-with-stack-protect.xml \
+ microblaze.xml \
++ microblaze64.xml \
+ mips-dsp-linux.xml \
+ mips-linux.xml \
+ mips64-dsp-linux.xml \
+diff --git a/gdb/features/microblaze-core.xml b/gdb/features/microblaze-core.xml
+index f272650a41b..d1f2282fd1e 100644
+--- a/gdb/features/microblaze-core.xml
++++ b/gdb/features/microblaze-core.xml
+@@ -8,7 +8,7 @@
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <feature name="org.gnu.gdb.microblaze.core">
+ <reg name="r0" bitsize="32" regnum="0"/>
+- <reg name="r1" bitsize="32" type="data_ptr"/>
++ <reg name="r1" bitsize="32"/>
+ <reg name="r2" bitsize="32"/>
+ <reg name="r3" bitsize="32"/>
+ <reg name="r4" bitsize="32"/>
+@@ -39,7 +39,7 @@
+ <reg name="r29" bitsize="32"/>
+ <reg name="r30" bitsize="32"/>
+ <reg name="r31" bitsize="32"/>
+- <reg name="rpc" bitsize="32" type="code_ptr"/>
++ <reg name="rpc" bitsize="32"/>
+ <reg name="rmsr" bitsize="32"/>
+ <reg name="rear" bitsize="32"/>
+ <reg name="resr" bitsize="32"/>
+@@ -64,4 +64,6 @@
+ <reg name="rtlbsx" bitsize="32"/>
+ <reg name="rtlblo" bitsize="32"/>
+ <reg name="rtlbhi" bitsize="32"/>
++ <reg name="rslr" bitsize="32"/>
++ <reg name="rshr" bitsize="32"/>
+ </feature>
+diff --git a/gdb/features/microblaze-with-stack-protect.c b/gdb/features/microblaze-with-stack-protect.c
+index b39aa198874..ab162fd2588 100644
+--- a/gdb/features/microblaze-with-stack-protect.c
++++ b/gdb/features/microblaze-with-stack-protect.c
+@@ -14,7 +14,7 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.core");
+ tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
+- tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
+@@ -45,7 +45,7 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+ tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
+- tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
+diff --git a/gdb/features/microblaze.c b/gdb/features/microblaze.c
+index 6c86fc07700..7919ac96e62 100644
+--- a/gdb/features/microblaze.c
++++ b/gdb/features/microblaze.c
+@@ -14,7 +14,7 @@ initialize_tdesc_microblaze (void)
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.core");
+ tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
+- tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
+@@ -45,7 +45,7 @@ initialize_tdesc_microblaze (void)
+ tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
+- tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
+@@ -70,6 +70,8 @@ initialize_tdesc_microblaze (void)
+ tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64");
+
+ tdesc_microblaze = result;
+ }
+diff --git a/gdb/features/microblaze64-core.xml b/gdb/features/microblaze64-core.xml
+new file mode 100644
+index 00000000000..b9adadfade6
+--- /dev/null
++++ b/gdb/features/microblaze64-core.xml
+@@ -0,0 +1,69 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++ Copying and distribution of this file, with or without modification,
++ are permitted in any medium without royalty provided the copyright
++ notice and this notice are preserved. -->
++
++<!DOCTYPE feature SYSTEM "gdb-target.dtd">
++<feature name="org.gnu.gdb.microblaze64.core">
++ <reg name="r0" bitsize="64" regnum="0"/>
++ <reg name="r1" bitsize="64"/>
++ <reg name="r2" bitsize="64"/>
++ <reg name="r3" bitsize="64"/>
++ <reg name="r4" bitsize="64"/>
++ <reg name="r5" bitsize="64"/>
++ <reg name="r6" bitsize="64"/>
++ <reg name="r7" bitsize="64"/>
++ <reg name="r8" bitsize="64"/>
++ <reg name="r9" bitsize="64"/>
++ <reg name="r10" bitsize="64"/>
++ <reg name="r11" bitsize="64"/>
++ <reg name="r12" bitsize="64"/>
++ <reg name="r13" bitsize="64"/>
++ <reg name="r14" bitsize="64"/>
++ <reg name="r15" bitsize="64"/>
++ <reg name="r16" bitsize="64"/>
++ <reg name="r17" bitsize="64"/>
++ <reg name="r18" bitsize="64"/>
++ <reg name="r19" bitsize="64"/>
++ <reg name="r20" bitsize="64"/>
++ <reg name="r21" bitsize="64"/>
++ <reg name="r22" bitsize="64"/>
++ <reg name="r23" bitsize="64"/>
++ <reg name="r24" bitsize="64"/>
++ <reg name="r25" bitsize="64"/>
++ <reg name="r26" bitsize="64"/>
++ <reg name="r27" bitsize="64"/>
++ <reg name="r28" bitsize="64"/>
++ <reg name="r29" bitsize="64"/>
++ <reg name="r30" bitsize="64"/>
++ <reg name="r31" bitsize="64"/>
++ <reg name="rpc" bitsize="64"/>
++ <reg name="rmsr" bitsize="32"/>
++ <reg name="rear" bitsize="64"/>
++ <reg name="resr" bitsize="32"/>
++ <reg name="rfsr" bitsize="32"/>
++ <reg name="rbtr" bitsize="64"/>
++ <reg name="rpvr0" bitsize="32"/>
++ <reg name="rpvr1" bitsize="32"/>
++ <reg name="rpvr2" bitsize="32"/>
++ <reg name="rpvr3" bitsize="32"/>
++ <reg name="rpvr4" bitsize="32"/>
++ <reg name="rpvr5" bitsize="32"/>
++ <reg name="rpvr6" bitsize="32"/>
++ <reg name="rpvr7" bitsize="32"/>
++ <reg name="rpvr8" bitsize="64"/>
++ <reg name="rpvr9" bitsize="64"/>
++ <reg name="rpvr10" bitsize="32"/>
++ <reg name="rpvr11" bitsize="32"/>
++ <reg name="redr" bitsize="32"/>
++ <reg name="rpid" bitsize="32"/>
++ <reg name="rzpr" bitsize="32"/>
++ <reg name="rtlbx" bitsize="32"/>
++ <reg name="rtlbsx" bitsize="32"/>
++ <reg name="rtlblo" bitsize="32"/>
++ <reg name="rtlbhi" bitsize="32"/>
++ <reg name="rslr" bitsize="64"/>
++ <reg name="rshr" bitsize="64"/>
++</feature>
+diff --git a/gdb/features/microblaze64-stack-protect.xml b/gdb/features/microblaze64-stack-protect.xml
+new file mode 100644
+index 00000000000..9d7ea8b9fd7
+--- /dev/null
++++ b/gdb/features/microblaze64-stack-protect.xml
+@@ -0,0 +1,12 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++ Copying and distribution of this file, with or without modification,
++ are permitted in any medium without royalty provided the copyright
++ notice and this notice are preserved. -->
++
++<!DOCTYPE feature SYSTEM "gdb-target.dtd">
++<feature name="org.gnu.gdb.microblaze64.stack-protect">
++ <reg name="rslr" bitsize="64"/>
++ <reg name="rshr" bitsize="64"/>
++</feature>
+diff --git a/gdb/features/microblaze64-with-stack-protect.c b/gdb/features/microblaze64-with-stack-protect.c
+new file mode 100644
+index 00000000000..249cb534daa
+--- /dev/null
++++ b/gdb/features/microblaze64-with-stack-protect.c
+@@ -0,0 +1,79 @@
++/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
++ Original: microblaze-with-stack-protect.xml */
++
++#include "defs.h"
++#include "osabi.h"
++#include "target-descriptions.h"
++
++struct target_desc *tdesc_microblaze64_with_stack_protect;
++static void
++initialize_tdesc_microblaze64_with_stack_protect (void)
++{
++ struct target_desc *result = allocate_target_description ();
++ struct tdesc_feature *feature;
++
++ feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.core");
++ tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "int");
++ tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
++
++ feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.stack-protect");
++ tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64");
++
++ tdesc_microblaze64_with_stack_protect = result;
++}
+diff --git a/gdb/features/microblaze64-with-stack-protect.xml b/gdb/features/microblaze64-with-stack-protect.xml
+new file mode 100644
+index 00000000000..0e9f01611f3
+--- /dev/null
++++ b/gdb/features/microblaze64-with-stack-protect.xml
+@@ -0,0 +1,12 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++ Copying and distribution of this file, with or without modification,
++ are permitted in any medium without royalty provided the copyright
++ notice and this notice are preserved. -->
++
++<!DOCTYPE target SYSTEM "gdb-target.dtd">
++<target>
++ <xi:include href="microblaze64-core.xml"/>
++ <xi:include href="microblaze64-stack-protect.xml"/>
++</target>
+diff --git a/gdb/features/microblaze64.c b/gdb/features/microblaze64.c
+new file mode 100644
+index 00000000000..5d3e2c8cd91
+--- /dev/null
++++ b/gdb/features/microblaze64.c
+@@ -0,0 +1,77 @@
++/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
++ Original: microblaze.xml */
++
++#include "defs.h"
++#include "osabi.h"
++#include "target-descriptions.h"
++
++struct target_desc *tdesc_microblaze64;
++static void
++initialize_tdesc_microblaze64 (void)
++{
++ struct target_desc *result = allocate_target_description ();
++ struct tdesc_feature *feature;
++
++ feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.core");
++ tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
++ tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64");
++ tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64");
++
++ tdesc_microblaze64 = result;
++}
+diff --git a/gdb/features/microblaze64.xml b/gdb/features/microblaze64.xml
+new file mode 100644
+index 00000000000..515d18e65cf
+--- /dev/null
++++ b/gdb/features/microblaze64.xml
+@@ -0,0 +1,11 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++ Copying and distribution of this file, with or without modification,
++ are permitted in any medium without royalty provided the copyright
++ notice and this notice are preserved. -->
++
++<!DOCTYPE target SYSTEM "gdb-target.dtd">
++<target>
++ <xi:include href="microblaze64-core.xml"/>
++</target>
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index 0afb6efeba3..48459a76991 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -159,9 +159,30 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+
+ /* BFD target for core files. */
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+- set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++ {
++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) {
++ set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblaze");
++ MICROBLAZE_REGISTER_SIZE=8;
++ }
++ else
++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++ }
+ else
+- set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++ {
++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) {
++ set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblazeel");
++ MICROBLAZE_REGISTER_SIZE=8;
++ }
++ else
++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++ }
++
++ switch (info.bfd_arch_info->mach)
++ {
++ case bfd_mach_microblaze64:
++ set_gdbarch_ptr_bit (gdbarch, 64);
++ break;
++ }
+
+
+ /* Shared library handling. */
+@@ -176,6 +197,8 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+ void
+ _initialize_microblaze_linux_tdep (void)
+ {
+- gdbarch_register_osabi (bfd_arch_microblaze, 0, GDB_OSABI_LINUX,
++ gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze, GDB_OSABI_LINUX,
++ microblaze_linux_init_abi);
++ gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze64, GDB_OSABI_LINUX,
+ microblaze_linux_init_abi);
+ }
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 98944f38d2a..5c0d6dd48ae 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -40,7 +40,9 @@
+ #include "remote.h"
+
+ #include "features/microblaze-with-stack-protect.c"
++#include "features/microblaze64-with-stack-protect.c"
+ #include "features/microblaze.c"
++#include "features/microblaze64.c"
+
+ /* Instruction macros used for analyzing the prologue. */
+ /* This set of instruction macros need to be changed whenever the
+@@ -79,8 +81,9 @@ static const char *microblaze_register_names[] =
+ };
+
+ #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names)
+-
++
+ static unsigned int microblaze_debug_flag = 0;
++int MICROBLAZE_REGISTER_SIZE = 4;
+
+ static void ATTRIBUTE_PRINTF (1, 2)
+ microblaze_debug (const char *fmt, ...)
+@@ -137,6 +140,7 @@ microblaze_fetch_instruction (CORE_ADDR pc)
+ constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT;
+
+ typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint;
++#if 0
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ struct bp_target_info *bp_tgt)
+@@ -169,6 +173,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+
+ return val;
+ }
++#endif
+
+ /* Allocate and initialize a frame cache. */
+
+@@ -556,7 +561,6 @@ microblaze_extract_return_value (struct type *type, struct regcache *regcache,
+ gdb_byte *valbuf)
+ {
+ gdb_byte buf[8];
+-
+ /* Copy the return value (starting) in RETVAL_REGNUM to VALBUF. */
+ switch (TYPE_LENGTH (type))
+ {
+@@ -633,7 +637,113 @@ microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
+ return (TYPE_LENGTH (type) == 16);
+ }
+
+-
++#if 0
++static std::vector<CORE_ADDR>
++microblaze_software_single_step (struct regcache *regcache)
++{
++// struct gdbarch *arch = get_frame_arch(frame);
++ struct gdbarch *arch = get_regcache_arch (regcache);
++ struct address_space *aspace = get_regcache_aspace (regcache);
++// struct address_space *aspace = get_frame_address_space (frame);
++ struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
++ static char le_breakp[] = MICROBLAZE_BREAKPOINT_LE;
++ static char be_breakp[] = MICROBLAZE_BREAKPOINT;
++ enum bfd_endian byte_order = gdbarch_byte_order (arch);
++ char *breakp = byte_order == BFD_ENDIAN_BIG ? be_breakp : le_breakp;
++ std::vector<CORE_ADDR> ret = 0;
++
++ /* Save the address and the values of the next_pc and the target */
++ static struct sstep_breaks
++ {
++ CORE_ADDR address;
++ bfd_boolean valid;
++ /* Shadow contents. */
++ char data[INST_WORD_SIZE];
++ } stepbreaks[2];
++ int ii;
++
++ if (1)
++ {
++ CORE_ADDR pc;
++ std::vector<CORE_ADDR> *next_pcs = NULL;
++ long insn;
++ enum microblaze_instr minstr;
++ bfd_boolean isunsignednum;
++ enum microblaze_instr_type insn_type;
++ short delay_slots;
++ int imm;
++ bfd_boolean immfound = FALSE;
++
++ /* Set a breakpoint at the next instruction */
++ /* If the current instruction is an imm, set it at the inst after */
++ /* If the instruction has a delay slot, skip the delay slot */
++ pc = regcache_read_pc (regcache);
++ insn = microblaze_fetch_instruction (pc);
++ minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots);
++ if (insn_type == immediate_inst)
++ {
++ int rd, ra, rb;
++ immfound = TRUE;
++ minstr = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
++ pc = pc + INST_WORD_SIZE;
++ insn = microblaze_fetch_instruction (pc);
++ minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots);
++ }
++ stepbreaks[0].address = pc + (delay_slots * INST_WORD_SIZE) + INST_WORD_SIZE;
++ if (insn_type != return_inst) {
++ stepbreaks[0].valid = TRUE;
++ } else {
++ stepbreaks[0].valid = FALSE;
++ }
++
++ microblaze_debug ("single-step insn_type=%x insn=%x\n", insn_type, insn);
++ /* Now check for branch or return instructions */
++ if (insn_type == branch_inst || insn_type == return_inst) {
++ int limm;
++ int lrd, lra, lrb;
++ int ra, rb;
++ bfd_boolean targetvalid;
++ bfd_boolean unconditionalbranch;
++ microblaze_decode_insn(insn, &lrd, &lra, &lrb, &limm);
++ if (lra >= 0 && lra < MICROBLAZE_NUM_REGS)
++ ra = regcache_raw_get_unsigned(regcache, lra);
++ else
++ ra = 0;
++ if (lrb >= 0 && lrb < MICROBLAZE_NUM_REGS)
++ rb = regcache_raw_get_unsigned(regcache, lrb);
++ else
++ rb = 0;
++ stepbreaks[1].address = microblaze_get_target_address (insn, immfound, imm, pc, ra, rb, &targetvalid, &unconditionalbranch);
++ microblaze_debug ("single-step uncondbr=%d targetvalid=%d target=%x\n", unconditionalbranch, targetvalid, stepbreaks[1].address);
++ if (unconditionalbranch)
++ stepbreaks[0].valid = FALSE; /* This is a unconditional branch: will not come to the next address */
++ if (targetvalid && (stepbreaks[0].valid == FALSE ||
++ (stepbreaks[0].address != stepbreaks[1].address))
++ && (stepbreaks[1].address != pc)) {
++ stepbreaks[1].valid = TRUE;
++ } else {
++ stepbreaks[1].valid = FALSE;
++ }
++ } else {
++ stepbreaks[1].valid = FALSE;
++ }
++
++ /* Insert the breakpoints */
++ for (ii = 0; ii < 2; ++ii)
++ {
++
++ /* ignore invalid breakpoint. */
++ if (stepbreaks[ii].valid) {
++ VEC_safe_push (CORE_ADDR, next_pcs, stepbreaks[ii].address);;
++// insert_single_step_breakpoint (arch, aspace, stepbreaks[ii].address);
++ ret = next_pcs;
++ }
++ }
++ }
++ return ret;
++}
++#endif
++
+ static int dwarf2_to_reg_map[78] =
+ { 0 /* r0 */, 1 /* r1 */, 2 /* r2 */, 3 /* r3 */, /* 0- 3 */
+ 4 /* r4 */, 5 /* r5 */, 6 /* r6 */, 7 /* r7 */, /* 4- 7 */
+@@ -665,24 +775,27 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
+ return -1;
+ }
+
++#if 0
+ static void
+ microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
+ {
++
+ register_remote_g_packet_guess (gdbarch,
+- 4 * MICROBLAZE_NUM_CORE_REGS,
+- tdesc_microblaze);
++ 4 * MICROBLAZE_NUM_REGS,
++ tdesc_microblaze64);
+
+ register_remote_g_packet_guess (gdbarch,
+ 4 * MICROBLAZE_NUM_REGS,
+- tdesc_microblaze_with_stack_protect);
++ tdesc_microblaze64_with_stack_protect);
+ }
++#endif
+
+ void
+ microblaze_supply_gregset (const struct regset *regset,
+ struct regcache *regcache,
+ int regnum, const void *gregs)
+ {
+- const unsigned int *regs = (const unsigned int *)gregs;
++ const gdb_byte *regs = (const gdb_byte *) gregs;
+ if (regnum >= 0)
+ regcache->raw_supply (regnum, regs + regnum);
+
+@@ -713,7 +826,6 @@ microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch,
+ }
+
+
+-
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ {
+@@ -727,8 +839,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ if (arches != NULL)
+ return arches->gdbarch;
+ if (tdesc == NULL)
+- tdesc = tdesc_microblaze;
+-
++ {
++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
++ {
++ tdesc = tdesc_microblaze64;
++ MICROBLAZE_REGISTER_SIZE = 8;
++ }
++ else
++ tdesc = tdesc_microblaze;
++ }
+ /* Check any target description for validity. */
+ if (tdesc_has_registers (tdesc))
+ {
+@@ -736,27 +855,35 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ int valid_p;
+ int i;
+
+- feature = tdesc_find_feature (tdesc,
++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
++ feature = tdesc_find_feature (tdesc,
++ "org.gnu.gdb.microblaze64.core");
++ else
++ feature = tdesc_find_feature (tdesc,
+ "org.gnu.gdb.microblaze.core");
+ if (feature == NULL)
+ return NULL;
+ tdesc_data = tdesc_data_alloc ();
+
+ valid_p = 1;
+- for (i = 0; i < MICROBLAZE_NUM_CORE_REGS; i++)
++ for (i = 0; i < MICROBLAZE_NUM_REGS; i++)
+ valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
+ microblaze_register_names[i]);
+- feature = tdesc_find_feature (tdesc,
++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
++ feature = tdesc_find_feature (tdesc,
++ "org.gnu.gdb.microblaze64.stack-protect");
++ else
++ feature = tdesc_find_feature (tdesc,
+ "org.gnu.gdb.microblaze.stack-protect");
+ if (feature != NULL)
+ {
+ valid_p = 1;
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ MICROBLAZE_SLR_REGNUM,
+- "rslr");
++ "slr");
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ MICROBLAZE_SHR_REGNUM,
+- "rshr");
++ "shr");
+ }
+
+ if (!valid_p)
+@@ -764,6 +891,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ tdesc_data_cleanup (tdesc_data);
+ return NULL;
+ }
++
+ }
+
+ /* Allocate space for the new architecture. */
+@@ -783,7 +911,17 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ /* Register numbers of various important registers. */
+ set_gdbarch_sp_regnum (gdbarch, MICROBLAZE_SP_REGNUM);
+ set_gdbarch_pc_regnum (gdbarch, MICROBLAZE_PC_REGNUM);
++
++ /* Register set.
++ make_regs (gdbarch); */
++ switch (info.bfd_arch_info->mach)
++ {
++ case bfd_mach_microblaze64:
++ set_gdbarch_ptr_bit (gdbarch, 64);
++ break;
++ }
+
++
+ /* Map Dwarf2 registers to GDB registers. */
+ set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum);
+
+@@ -803,13 +941,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ microblaze_breakpoint::kind_from_pc);
+ set_gdbarch_sw_breakpoint_from_kind (gdbarch,
+ microblaze_breakpoint::bp_from_kind);
+- set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
++// set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
++
++// set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
+
+ set_gdbarch_frame_args_skip (gdbarch, 8);
+
+ set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc);
+
+- microblaze_register_g_packet_guesses (gdbarch);
++ //microblaze_register_g_packet_guesses (gdbarch);
+
+ frame_base_set_default (gdbarch, µblaze_frame_base);
+
+@@ -840,6 +980,8 @@ _initialize_microblaze_tdep (void)
+
+ initialize_tdesc_microblaze_with_stack_protect ();
+ initialize_tdesc_microblaze ();
++ initialize_tdesc_microblaze64_with_stack_protect ();
++ initialize_tdesc_microblaze64 ();
+ /* Debug this files internals. */
+ add_setshow_zuinteger_cmd ("microblaze", class_maintenance,
+ µblaze_debug_flag, _("\
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index d2112dc07e1..bd03e969b9b 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -27,7 +27,7 @@ struct microblaze_gregset
+ microblaze_gregset() {}
+ unsigned int gregs[32];
+ unsigned int fpregs[32];
+- unsigned int pregs[16];
++ unsigned int pregs[18];
+ };
+
+ struct gdbarch_tdep
+@@ -101,9 +101,9 @@ enum microblaze_regnum
+ MICROBLAZE_RTLBSX_REGNUM,
+ MICROBLAZE_RTLBLO_REGNUM,
+ MICROBLAZE_RTLBHI_REGNUM,
+- MICROBLAZE_SLR_REGNUM, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_SLR_REGNUM,
++ MICROBLAZE_SLR_REGNUM,
+ MICROBLAZE_SHR_REGNUM,
+- MICROBLAZE_NUM_REGS
++ MICROBLAZE_NUM_REGS, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_NUM_REGS
+ };
+
+ struct microblaze_frame_cache
+@@ -128,7 +128,8 @@ struct microblaze_frame_cache
+ struct trad_frame_saved_reg *saved_regs;
+ };
+ /* All registers are 32 bits. */
+-#define MICROBLAZE_REGISTER_SIZE 4
++extern int microblaze_reg_size;
++#define MICROBLAZE_REGISTER_SIZE microblaze_reg_size
+
+ /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used.
+ Only used for native debugging. */
+diff --git a/gdb/regformats/microblaze-with-stack-protect.dat b/gdb/regformats/microblaze-with-stack-protect.dat
+index 8040a7b3fd0..450e321d49e 100644
+--- a/gdb/regformats/microblaze-with-stack-protect.dat
++++ b/gdb/regformats/microblaze-with-stack-protect.dat
+@@ -60,5 +60,5 @@ expedite:r1,rpc
+ 32:rtlbsx
+ 32:rtlblo
+ 32:rtlbhi
+-32:rslr
+-32:rshr
++32:slr
++32:shr
+--
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb_%.bbappend b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb_%.bbappend
new file mode 100644
index 0000000..ceb7b02
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb_%.bbappend
@@ -0,0 +1,4 @@
+MICROBLAZEPATCHES = ""
+MICROBLAZEPATCHES_microblaze = "gdb-microblaze.inc"
+
+require ${MICROBLAZEPATCHES}