subtree updates
meta-security: 3d9dab6d14..7eed4a60f5:
Armin Kuster (2):
linux-yocto.bbappend: bump to kernel version 6.x
meta-tpm: bump linux-yocto to 6.x kernel
Max Krummenacher (1):
samhain: rework due to changed cache handling
meta-openembedded: 2ab113e8be..ea63f13846:
Beniamin Sandu (1):
mbedtls: export source files/headers needed by ATF
Khem Raj (13):
poco: Do not use std::atomic<bool>
libwebsockets: Fix build with gcc13
v4l-utils: Fix build with gcc13
proj: Upgrade to 9.1.1 release
mpd: Upgrade to 0.23.12 release
geos: Upgrade to 3.9.4
geos: Fix build with gcc13
libinih: Upgrade to version 56
python3-pybind11: Upgrade to 2.10.3
waylandpp: Fix build with gcc-13
sedutil: Fix build with gcc13
usbguard: Fix build with gcc13
minifi-cpp: Fix build with gcc13
Martin Jansa (6):
keyutils: fix Upstream-Status formatting
gphoto2: fix Upstream-Status formatting
.patch: fix Upstream-Status formatting issues reported by patchreview tool from oe-core
android-tools: fix Upstream-Status formatting
mm-common: fix Upstream-Status formatting
.patch: fix Signed-off-by formatting issues reported by patchreview tool from oe-core
poky: 5e249ec855..29afbb5e14:
Alejandro Hernandez Samaniego (1):
newlib: Upgrade 4.2.0 -> 4.3.0
Alexander Kanavin (1):
gdk-pixbuf: do not use tools from gdk-pixbuf-native when building tests
Armin Kuster (1):
lttng-modules: Fix for 5.10.163 kernel version
Khem Raj (3):
valgrind: Include missing <cstdint>
webkitgtk: Fix build with gcc 13
gdb: Define alignof using _Alignof when using C11 or newer
Richard Purdie (3):
make-mod-scripts: Ensure kernel build output is deterministic
bitbake.conf: Inject a dash into PN for BB_HASH_CODEPARSER_VALS
scripts/bitbake-prserv-tool: Fix to work with memres bitbake
Ross Burton (1):
Revert "cve-update-db-native: show IP on failure"
meta-arm: 3d51e1117d..aecbb77f72:
Jon Mason (4):
arm/qemuarm-secureboot: Changes for v2023.01 u-boot
arm-bsp/juno: update to use u-boot v2023.01
arm-bsp/juno: update kernel patches for 6.1
arm-bsp/fvp-base: update kernel config to remove warning
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Change-Id: Ia335876b7ce9a4c9d19ca41ae321b266b3b6d00e
diff --git a/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0003-arm64-dts-fvp-Add-information-about-L1-and-L2-caches.patch b/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0003-arm64-dts-fvp-Add-information-about-L1-and-L2-caches.patch
new file mode 100644
index 0000000..fc02751
--- /dev/null
+++ b/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0003-arm64-dts-fvp-Add-information-about-L1-and-L2-caches.patch
@@ -0,0 +1,146 @@
+From 22e740d069e14875a64864bf86e0826a96560b44 Mon Sep 17 00:00:00 2001
+From: Sudeep Holla <sudeep.holla@arm.com>
+Date: Fri, 18 Nov 2022 15:10:17 +0000
+Subject: [PATCH] arm64: dts: fvp: Add information about L1 and L2 caches
+
+Add the information about L1 and L2 caches on FVP RevC platform.
+Though the cache size is configurable through the model parameters,
+having default values in the device tree helps to exercise and debug
+any code utilising the cache information without the need of real
+hardware.
+
+Link: https://lore.kernel.org/r/20221118151017.704716-1-sudeep.holla@arm.com
+Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
+
+Signed-off-by: Jon Mason <jon.mason@arm.com>
+Upstream-Status: Backport
+---
+ arch/arm64/boot/dts/arm/fvp-base-revc.dts | 73 +++++++++++++++++++++++
+ 1 file changed, 73 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
+index 5f6f30c801a7..60472d65a355 100644
+--- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts
++++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
+@@ -47,48 +47,121 @@ cpu0: cpu@0 {
+ compatible = "arm,armv8";
+ reg = <0x0 0x000>;
+ enable-method = "psci";
++ i-cache-size = <0x8000>;
++ i-cache-line-size = <64>;
++ i-cache-sets = <256>;
++ d-cache-size = <0x8000>;
++ d-cache-line-size = <64>;
++ d-cache-sets = <256>;
++ next-level-cache = <&C0_L2>;
+ };
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
++ i-cache-size = <0x8000>;
++ i-cache-line-size = <64>;
++ i-cache-sets = <256>;
++ d-cache-size = <0x8000>;
++ d-cache-line-size = <64>;
++ d-cache-sets = <256>;
++ next-level-cache = <&C0_L2>;
+ };
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
++ i-cache-size = <0x8000>;
++ i-cache-line-size = <64>;
++ i-cache-sets = <256>;
++ d-cache-size = <0x8000>;
++ d-cache-line-size = <64>;
++ d-cache-sets = <256>;
++ next-level-cache = <&C0_L2>;
+ };
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
++ i-cache-size = <0x8000>;
++ i-cache-line-size = <64>;
++ i-cache-sets = <256>;
++ d-cache-size = <0x8000>;
++ d-cache-line-size = <64>;
++ d-cache-sets = <256>;
++ next-level-cache = <&C0_L2>;
+ };
+ cpu4: cpu@10000 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x10000>;
+ enable-method = "psci";
++ i-cache-size = <0x8000>;
++ i-cache-line-size = <64>;
++ i-cache-sets = <256>;
++ d-cache-size = <0x8000>;
++ d-cache-line-size = <64>;
++ d-cache-sets = <256>;
++ next-level-cache = <&C1_L2>;
+ };
+ cpu5: cpu@10100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x10100>;
+ enable-method = "psci";
++ i-cache-size = <0x8000>;
++ i-cache-line-size = <64>;
++ i-cache-sets = <256>;
++ d-cache-size = <0x8000>;
++ d-cache-line-size = <64>;
++ d-cache-sets = <256>;
++ next-level-cache = <&C1_L2>;
+ };
+ cpu6: cpu@10200 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x10200>;
+ enable-method = "psci";
++ i-cache-size = <0x8000>;
++ i-cache-line-size = <64>;
++ i-cache-sets = <256>;
++ d-cache-size = <0x8000>;
++ d-cache-line-size = <64>;
++ d-cache-sets = <256>;
++ next-level-cache = <&C1_L2>;
+ };
+ cpu7: cpu@10300 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x10300>;
+ enable-method = "psci";
++ i-cache-size = <0x8000>;
++ i-cache-line-size = <64>;
++ i-cache-sets = <256>;
++ d-cache-size = <0x8000>;
++ d-cache-line-size = <64>;
++ d-cache-sets = <256>;
++ next-level-cache = <&C1_L2>;
++ };
++ C0_L2: l2-cache0 {
++ compatible = "cache";
++ cache-size = <0x80000>;
++ cache-line-size = <64>;
++ cache-sets = <512>;
++ cache-level = <2>;
++ cache-unified;
++ };
++
++ C1_L2: l2-cache1 {
++ compatible = "cache";
++ cache-size = <0x80000>;
++ cache-line-size = <64>;
++ cache-sets = <512>;
++ cache-level = <2>;
++ cache-unified;
+ };
+ };
+