Import 80d60e7 from yoctoproject.org meta-arm
To support ARMv8 SoCs.
meta-arm has several patch files. Since they are maintained by the
upstream meta-arm community, add meta-arm to the ignore list in
run-repotest.
Change-Id: Ia87a2e947bbabd347d256eccc47a343e1c885479
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/tc/0007-fix-plat-tc-disable-smmu.patch b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/tc/0007-fix-plat-tc-disable-smmu.patch
new file mode 100644
index 0000000..91f5a9e
--- /dev/null
+++ b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/tc/0007-fix-plat-tc-disable-smmu.patch
@@ -0,0 +1,64 @@
+From 1a051bef6c63f6871edd8d87e969460f073820a7 Mon Sep 17 00:00:00 2001
+From: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+Date: Wed, 27 Apr 2022 18:15:47 +0100
+Subject: [PATCH 7/7] fix(plat/tc): disable smmu
+
+Reserve static shared-dma-pool below 4GB. This removes dependency on
+SMMU driver. As there are stability issues in SMMU driver, it is
+disabled. This change is temporary and will be reverted upon proper
+fix and testing.
+
+Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+Change-Id: I6b1b4c2a0acdf62df8c26007c7ca596774e13710
+Upstream-Status: Pending [Not submitted to upstream yet]
+---
+ fdts/tc.dts | 16 +++-------------
+ 1 file changed, 3 insertions(+), 13 deletions(-)
+
+diff --git a/fdts/tc.dts b/fdts/tc.dts
+index dc86958bf..fbae3e3e8 100644
+--- a/fdts/tc.dts
++++ b/fdts/tc.dts
+@@ -209,12 +209,12 @@
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+- size = <0x0 0x8000000>;
++ reg = <0x0 0xf1000000 0x0 0x8000000>;
+ linux,cma-default;
+ };
+
+- optee@0xf8e00000 {
+- reg = <0x00000000 0xf8e00000 0 0x00200000>;
++ optee@0xf0e00000 {
++ reg = <0x0 0xf0e00000 0 0x00200000>;
+ no-map;
+ };
+ };
+@@ -460,13 +460,6 @@
+ >;
+ };
+
+- smmu: smmu@2ce00000 {
+- #iommu-cells = <1>;
+- compatible = "arm,smmu-v3";
+- reg = <0x0 0x2ce00000 0x0 0x20000>;
+- status = "okay";
+- };
+-
+ dp0: display@2cc00000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+@@ -476,9 +469,6 @@
+ interrupt-names = "DPU";
+ clocks = <&scmi_clk 0>;
+ clock-names = "aclk";
+- iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
+- <&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
+- <&smmu 8>, <&smmu 9>;
+ pl0: pipeline@0 {
+ reg = <0>;
+ clocks = <&scmi_clk 1>;
+--
+2.30.2
+