meta-aspeed: u-boot-aspeed-sdk: Add eMMC ABR ROM patch

Address errata 80 from E2600-11.pdf in a ROM patch for integration into
the OTP image. A otptool configuration file is provided as an example

Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
[AJ: Take 098e7ba124184 from https://github.com/AspeedTech-BMC/openbmc]
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Change-Id: I936c60f9db8e36f3213f426aebeb62b72015303c
diff --git a/meta-aspeed/recipes-bsp/u-boot/files/evbA3_emmc_patch.json b/meta-aspeed/recipes-bsp/u-boot/files/evbA3_emmc_patch.json
new file mode 100644
index 0000000..4afb7b2
--- /dev/null
+++ b/meta-aspeed/recipes-bsp/u-boot/files/evbA3_emmc_patch.json
@@ -0,0 +1,45 @@
+{
+    "name": "evb",
+    "version": "A3",
+    "data_region": {
+        "patch": true,
+        "ecc_region": true,
+        "user_data": [
+            {
+                // dw_hex
+                // bin
+                "types": "dw_hex",
+                "file": "emmc_patch.hex",
+                "offset": "0x1B80"
+            }
+        ]
+    },
+    "config_region": {
+        // OTPCFG0[14]
+        // false: Enable patch code
+        // true : Disable patch code
+        "Disable patch code": false,
+        // OTPCFG14[10-0]
+        "Patch code location": "0x6E0",
+        // OTPCFG14[16-11] 24 DW
+        "Patch code size": "0x18"
+    },
+    "otp_strap": {
+        // OTPSTRAP[1]
+        "Enable boot from eMMC": {
+            // false: Disable boot from eMMC
+            // true : Enable boot from eMMC
+            "value": true,
+            "otp_protect": false,
+            "ignore": false
+        },
+        // OTPSTRAP[43]
+        "Enable boot SPI or eMMC ABR": {
+            // false: Disable boot SPI or eMMC ABR
+            // true : Enable boot SPI or eMMC ABR
+            "value": true,
+            "otp_protect": false,
+            "ignore": false
+        }
+    }
+}
diff --git a/meta-aspeed/recipes-bsp/u-boot/files/user/emmc_patch.hex b/meta-aspeed/recipes-bsp/u-boot/files/user/emmc_patch.hex
new file mode 100644
index 0000000..6679154
--- /dev/null
+++ b/meta-aspeed/recipes-bsp/u-boot/files/user/emmc_patch.hex
@@ -0,0 +1,24 @@
+2c000000
+558000ff
+a4001cf4
+7ab20001
+46b50001
+86a0d888
+d2b82510
+7ab5000b
+46b50001
+86a0d878
+d15920a0
+696a0010
+796b0018
+8560d868
+6a8a001b
+7a94001f
+9e80d85c
+2aa01688
+56b5a8a8
+deb82010
+dc182070
+55600001
+dd792074
+a000189c
diff --git a/meta-aspeed/recipes-bsp/u-boot/u-boot-aspeed-sdk_2019.04.bb b/meta-aspeed/recipes-bsp/u-boot/u-boot-aspeed-sdk_2019.04.bb
index ae85f6b..91297a5 100644
--- a/meta-aspeed/recipes-bsp/u-boot/u-boot-aspeed-sdk_2019.04.bb
+++ b/meta-aspeed/recipes-bsp/u-boot/u-boot-aspeed-sdk_2019.04.bb
@@ -11,12 +11,15 @@
 SRC_URI += " \
             file://rsa_oem_dss_key.pem;sha256sum=64a379979200d39949d3e5b0038e3fdd5548600b2f7077a17e35422336075ad4 \
             file://rsa_pub_oem_dss_key.pem;sha256sum=40132a694a10af2d1b094b1cb5adab4d6b4db2a35e02d848b2b6a85e60738264 \
+            file://user/ \
            "
 
 SOCSEC_SIGN_KEY ?= "${WORKDIR}/rsa_oem_dss_key.pem"
 SOCSEC_SIGN_ALGO ?= "RSA4096_SHA512"
 SOCSEC_SIGN_EXTRA_OPTS ?= "--stack_intersects_verification_region=false --rsa_key_order=big"
 
+OTPTOOL_USER_DIR ?= "${WORKDIR}/user"
+
 inherit socsec-sign
 inherit otptool