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gerrit.openbmc.org / openbmc / openbmc / f96073cab66cd4c26a12710ba692fcc17cb6e33f / . / meta-arm / meta-arm-bsp / recipes-bsp / u-boot / u-boot / corstone1000 / 0002-arm-add-support-to-corstone1000-platform.patch
blob: 4c7c9b1415147331f5e0ae33db0f3d813d8d7473 [file] [log] [blame]
From 3523b1bac430f10f02a31f7d013ea369e29656be Mon Sep 17 00:00:00 2001
From: Rui Miguel Silva <rui.silva@linaro.org>
Date: Tue, 15 Feb 2022 09:44:10 +0000
Subject: [PATCH 02/26] arm: add support to corstone1000 platform
Corstone1000 is a platform from arm, which includes pre
verified Corstone SSE710 sub-system that combines Cortex-A and
Cortex-M processors [0].
This code adds the support for the Cortex-A35 implementation
at host side, it contains also the necessary bits to support
the Corstone 1000 FVP (Fixed Virtual Platform) [1] and also the
FPGA MPS3 board implementation of this platform. [2]
0: https://documentation-service.arm.com/static/619e02b1f45f0b1fbf3a8f16
1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
2: https://documentation-service.arm.com/static/61f3f4d7fa8173727a1b71bf
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Upstream-Status: Accepted [2022.10-rc1]
---
arch/arm/Kconfig | 8 ++
arch/arm/dts/Makefile | 3 +
arch/arm/dts/corstone1000-fvp.dts | 23 +++
arch/arm/dts/corstone1000-mps3.dts | 32 +++++
arch/arm/dts/corstone1000.dtsi | 169 +++++++++++++++++++++++
board/armltd/corstone1000/Kconfig | 12 ++
board/armltd/corstone1000/MAINTAINERS | 7 +
board/armltd/corstone1000/Makefile | 7 +
board/armltd/corstone1000/corstone1000.c | 125 +++++++++++++++++
configs/corstone1000_defconfig | 80 +++++++++++
include/configs/corstone1000.h | 86 ++++++++++++
11 files changed, 552 insertions(+)
create mode 100644 arch/arm/dts/corstone1000-fvp.dts
create mode 100644 arch/arm/dts/corstone1000-mps3.dts
create mode 100644 arch/arm/dts/corstone1000.dtsi
create mode 100644 board/armltd/corstone1000/Kconfig
create mode 100644 board/armltd/corstone1000/MAINTAINERS
create mode 100644 board/armltd/corstone1000/Makefile
create mode 100644 board/armltd/corstone1000/corstone1000.c
create mode 100644 configs/corstone1000_defconfig
create mode 100644 include/configs/corstone1000.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9898c7d68e..2fc2b7d20f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1347,6 +1347,12 @@ config ARCH_VEXPRESS64
select ENV_IS_IN_FLASH if MTD
imply DISTRO_DEFAULTS
+config TARGET_CORSTONE1000
+ bool "Support Corstone1000 Platform"
+ select ARM64
+ select PL01X_SERIAL
+ select DM
+
config TARGET_TOTAL_COMPUTE
bool "Support Total Compute Platform"
select ARM64
@@ -2295,6 +2301,8 @@ source "arch/arm/mach-npcm/Kconfig"
source "board/armltd/total_compute/Kconfig"
+source "board/armltd/corstone1000/Kconfig"
+
source "board/bosch/shc/Kconfig"
source "board/bosch/guardian/Kconfig"
source "board/Marvell/octeontx/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a7e0d9f6c0..8c8f15b6a8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1265,6 +1265,9 @@ dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb
+dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \
+ corstone1000-fvp.dtb
+
include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y)
diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts
new file mode 100644
index 0000000000..1fcc137a49
--- /dev/null
+++ b/arch/arm/dts/corstone1000-fvp.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited. All rights reserved.
+ *
+ */
+
+/dts-v1/;
+
+#include "corstone1000.dtsi"
+
+/ {
+ model = "ARM Corstone1000 FVP (Fixed Virtual Platform)";
+ compatible = "arm,corstone1000-fvp";
+
+ smsc: ethernet@4010000 {
+ compatible = "smsc,lan91c111";
+ reg = <0x40100000 0x10000>;
+ phy-mode = "mii";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <2>;
+ };
+};
diff --git a/arch/arm/dts/corstone1000-mps3.dts b/arch/arm/dts/corstone1000-mps3.dts
new file mode 100644
index 0000000000..e3146747c2
--- /dev/null
+++ b/arch/arm/dts/corstone1000-mps3.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited. All rights reserved.
+ *
+ */
+
+/dts-v1/;
+
+#include "corstone1000.dtsi"
+
+/ {
+ model = "ARM Corstone1000 FPGA MPS3 board";
+ compatible = "arm,corstone1000-mps3";
+
+ smsc: ethernet@4010000 {
+ compatible = "smsc,lan9220", "smsc,lan9115";
+ reg = <0x40100000 0x10000>;
+ phy-mode = "mii";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <2>;
+ smsc,irq-push-pull;
+ };
+
+ usb_host: usb@40200000 {
+ compatible = "nxp,usb-isp1763";
+ reg = <0x40200000 0x100000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ bus-width = <16>;
+ dr_mode = "host";
+ };
+};
diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi
new file mode 100644
index 0000000000..d0194aa893
--- /dev/null
+++ b/arch/arm/dts/corstone1000.dtsi
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited. All rights reserved.
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0>;
+ next-level-cache = <&L2_0>;
+ };
+ };
+
+ memory@88200000 {
+ device_type = "memory";
+ reg = <0x88200000 0x77e00000>;
+ };
+
+ gic: interrupt-controller@1c000000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1c010000 0x1000>,
+ <0x1c02f000 0x2000>,
+ <0x1c04f000 0x1000>,
+ <0x1c06f000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ };
+
+ refclk100mhz: refclk100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "apb_pclk";
+ };
+
+ smbclk: refclk24mhzx2 {
+ /* Reference 24MHz clock x 2 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ clock-output-names = "smclk";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ uartclk: uartclk {
+ /* UART clock - 50MHz */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-output-names = "uartclk";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+ ranges;
+
+ timer@1a220000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x1a220000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clock-frequency = <50000000>;
+ ranges;
+
+ frame@1a230000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x1a230000 0x1000>;
+ };
+ };
+
+ uart0: serial@1a510000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x1a510000 0x1000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uartclk>, <&refclk100mhz>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ uart1: serial@1a520000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x1a520000 0x1000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uartclk>, <&refclk100mhz>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ mhu_hse1: mailbox@1b820000 {
+ compatible = "arm,mhuv2-tx", "arm,primecell";
+ reg = <0x1b820000 0x1000>;
+ clocks = <&refclk100mhz>;
+ clock-names = "apb_pclk";
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ arm,mhuv2-protocols = <0 0>;
+ secure-status = "okay"; /* secure-world-only */
+ status = "disabled";
+ };
+
+ mhu_seh1: mailbox@1b830000 {
+ compatible = "arm,mhuv2-rx", "arm,primecell";
+ reg = <0x1b830000 0x1000>;
+ clocks = <&refclk100mhz>;
+ clock-names = "apb_pclk";
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ arm,mhuv2-protocols = <0 0>;
+ secure-status = "okay"; /* secure-world-only */
+ status = "disabled";
+ };
+ };
+
+ arm_ffa: arm_ffa {
+ compatible = "arm,ffa";
+ method = "smc";
+ };
+};
diff --git a/board/armltd/corstone1000/Kconfig b/board/armltd/corstone1000/Kconfig
new file mode 100644
index 0000000000..709674d4cf
--- /dev/null
+++ b/board/armltd/corstone1000/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CORSTONE1000
+
+config SYS_BOARD
+ default "corstone1000"
+
+config SYS_VENDOR
+ default "armltd"
+
+config SYS_CONFIG_NAME
+ default "corstone1000"
+
+endif
diff --git a/board/armltd/corstone1000/MAINTAINERS b/board/armltd/corstone1000/MAINTAINERS
new file mode 100644
index 0000000000..8c905686de
--- /dev/null
+++ b/board/armltd/corstone1000/MAINTAINERS
@@ -0,0 +1,7 @@
+CORSTONE1000 BOARD
+M: Rui Miguel Silva <rui.silva@linaro.org>
+M: Vishnu Banavath <vishnu.banavath@arm.com>
+S: Maintained
+F: board/armltd/corstone1000/
+F: include/configs/corstone1000.h
+F: configs/corstone1000_defconfig
diff --git a/board/armltd/corstone1000/Makefile b/board/armltd/corstone1000/Makefile
new file mode 100644
index 0000000000..77a82c2892
--- /dev/null
+++ b/board/armltd/corstone1000/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Arm Limited
+# (C) Copyright 2022 Linaro
+# Rui Miguel Silva <rui.silva@linaro.org>
+
+obj-y := corstone1000.o
diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c
new file mode 100644
index 0000000000..2fa485ff37
--- /dev/null
+++ b/board/armltd/corstone1000/corstone1000.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2022 ARM Limited
+ * (C) Copyright 2022 Linaro
+ * Rui Miguel Silva <rui.silva@linaro.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
+
+
+static const struct pl01x_serial_plat serial_plat = {
+ .base = V2M_UART0,
+ .type = TYPE_PL011,
+ .clock = CONFIG_PL011_CLOCK,
+};
+
+U_BOOT_DRVINFO(corstone1000_serials) = {
+ .name = "serial_pl01x",
+ .plat = &serial_plat,
+};
+
+static struct mm_region corstone1000_mem_map[] = {
+ {
+ /* CVM */
+ .virt = 0x02000000UL,
+ .phys = 0x02000000UL,
+ .size = 0x02000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* QSPI */
+ .virt = 0x08000000UL,
+ .phys = 0x08000000UL,
+ .size = 0x08000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* Host Peripherals */
+ .virt = 0x1A000000UL,
+ .phys = 0x1A000000UL,
+ .size = 0x26000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* USB */
+ .virt = 0x40200000UL,
+ .phys = 0x40200000UL,
+ .size = 0x00100000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* ethernet */
+ .virt = 0x40100000UL,
+ .phys = 0x40100000UL,
+ .size = 0x00100000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* OCVM */
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = corstone1000_mem_map;
+
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+/*
+ * Board specific ethernet initialization routine.
+ * */
+int board_eth_init(struct bd_info *bis)
+{
+ int rc = 0;
+
+#ifndef CONFIG_DM_ETH
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+#endif
+
+ return rc;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
new file mode 100644
index 0000000000..02f931b0d4
--- /dev/null
+++ b/configs/corstone1000_defconfig
@@ -0,0 +1,80 @@
+CONFIG_ARM=y
+CONFIG_TARGET_CORSTONE1000=y
+CONFIG_SYS_TEXT_BASE=0x80000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x82100000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_IDENT_STRING=" corstone1000 aarch64 "
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk"
+CONFIG_LOGLEVEL=7
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="corstone1000# "
+# CONFIG_CMD_CONSOLE is not set
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_LOADM=y
+CONFIG_CMD_BOOTEFI=y
+CONFIG_EFI_LOADER=y
+CONFIG_EFI_PARTITION=y
+CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y
+CONFIG_CMD_BOOTEFI_HELLO=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
+CONFIG_CMD_ITEST=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+# CONFIG_MMC is not set
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_EFI_MM_COMM_TEE=y
+# CONFIG_OPTEE is not set
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
+# CONFIG_HEXDUMP is not set
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+# CONFIG_EFI_CAPSULE_ON_DISK_EARLY is not set
+# CONFIG_EFI_CAPSULE_AUTHENTICATE is not set
+CONFIG_EFI_HAVE_CAPSULE_SUPPORT=y
+CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+CONFIG_DM_RTC=y
+CONFIG_CMD_RTC=y
+CONFIG_EFI_GET_TIME=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_RTC_EMULATION=y
+CONFIG_PSCI_RESET=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_CMD_DHCP=y
+CONFIG_SMC911X=y
+CONFIG_SMC911X_BASE=0x40100000
+CONFIG_DM_ETH=y
+CONFIG_PHY_SMSC=y
+CONFIG_CMD_BOOTEFI_SELFTEST=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_PHYLIB=y
+CONFIG_PHY=y
+CONFIG_RAM=y
+CONFIG_ERRNO_STR=y
+CONFIG_CMD_EDITENV=y
+CONFIG_MISC=y
diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h
new file mode 100644
index 0000000000..cf166f107e
--- /dev/null
+++ b/include/configs/corstone1000.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 ARM Limited
+ * (C) Copyright 2022 Linaro
+ * Rui Miguel Silva <rui.silva@linaro.org>
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ *
+ * Configuration for Corstone1000. Parts were derived from other ARM
+ * configurations.
+ */
+
+#ifndef __CORSTONE1000_H
+#define __CORSTONE1000_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SYS_HZ 1000
+
+#define V2M_SRAM0 0x02000000
+#define V2M_QSPI 0x08000000
+
+#define V2M_DEBUG 0x10000000
+#define V2M_BASE_PERIPH 0x1A000000
+
+#define V2M_BASE 0x80000000
+
+#define V2M_PERIPH_OFFSET(x) (x << 16)
+
+#define V2M_SYSID (V2M_BASE_PERIPH)
+#define V2M_SYSCTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(1))
+
+#define V2M_COUNTER_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(32))
+#define V2M_COUNTER_READ (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(33))
+
+#define V2M_TIMER_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(34))
+#define V2M_TIMER_BASE0 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(35))
+
+#define V2M_UART0 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(81))
+#define V2M_UART1 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(82))
+
+#define CONFIG_PL011_CLOCK 50000000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1 (V2M_BASE)
+#define PHYS_SDRAM_1_SIZE 0x80000000
+
+#define CONFIG_ENV_SECT_SIZE SZ_64K
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS 64 /* max command args */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "usb_pgood_delay=250\0" \
+ "boot_bank_flag=0x08002000\0" \
+ "kernel_addr_bank_0=0x083EE000\0" \
+ "kernel_addr_bank_1=0x0936E000\0" \
+ "retrieve_kernel_load_addr=" \
+ "if itest.l *${boot_bank_flag} == 0; then " \
+ "setenv kernel_addr $kernel_addr_bank_0;" \
+ "else " \
+ "setenv kernel_addr $kernel_addr_bank_1;" \
+ "fi;" \
+ "\0" \
+ "kernel_addr_r=0x88200000\0" \
+ "fdt_high=0xffffffff\0"
+
+/*
+ * config_distro_bootcmd define the boot command to distro_bootcmd, but we here
+ * want to first try to load a kernel if exists, override that config then
+ */
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_BOOTCOMMAND \
+ "run retrieve_kernel_load_addr;" \
+ "echo Loading kernel from $kernel_addr to memory ... ;" \
+ "loadm $kernel_addr $kernel_addr_r 0xc00000;" \
+ "usb start; usb reset;" \
+ "run distro_bootcmd;" \
+ "bootefi $kernel_addr_r $fdtcontroladdr;"
+#endif
--
2.17.1