blob: cada4463793ab27873590191e152c7e842f33db2 [file] [log] [blame]
Andrew Jeffery8c8fb8b2022-01-27 10:19:17 +10301{
2 "name": "rainier",
3 "version": "A3",
4 "data_region": {
5 "ecc_region": true,
6 "key": [
7 {
8 "types": "rsa_pub_oem",
9 "key_pem": "rsa_pub_oem_dss_key.pem",
10 "offset": "0x40",
11 "number_id": 0,
12 "sha_mode": "SHA512"
13 },
14 {
15 "types": "rsa_pub_oem",
Andrew Jeffery7ecd9d92022-05-24 10:08:30 +093016 "key_pem": "P10BMCAspeedSBPubKey_2.pem",
Andrew Jeffery8c8fb8b2022-01-27 10:19:17 +103017 "offset": "0x240",
18 "number_id": 1,
19 "sha_mode": "SHA512"
20 },
21 {
22 "types": "rsa_pub_oem",
Andrew Jeffery7ecd9d92022-05-24 10:08:30 +093023 "key_pem": "P10BMCAspeedSBPubKey_3.pem",
Andrew Jeffery8c8fb8b2022-01-27 10:19:17 +103024 "offset": "0x440",
25 "number_id": 2,
26 "sha_mode": "SHA512"
Andrew Jeffery8c8fb8b2022-01-27 10:19:17 +103027 }
28 ]
29 },
30 "config_region": {
31 "Disable OTP Memory BIST Mode": true,
32 "Enable Secure Boot": false,
33 "User region ECC enable": true,
34 "Secure Region ECC enable": false,
35 "Disable low security key": false,
36 "Ignore Secure Boot hardware strap": false,
37 "Secure Boot Mode": "Mode_2",
38 "Disable Uart Message of ROM code": false,
39 "Secure crypto RSA length": "RSA4096",
40 "Hash mode": "SHA512",
41 "Disable patch code": true,
42 "Disable Boot from Uart": false,
43 "Secure Region size": "0x0",
44 "Write Protect: Secure Region": true,
45 "Write Protect: User region": true,
46 "Write Protect: Configure region": true,
47 "Write Protect: OTP strap region": true,
48 "Copy Boot Image to Internal SRAM": true,
49 "Enable image encryption": false,
50 "Enable write Protect of OTP key retire bits": false,
51 "Disable Auto Boot from UART or VUART": false,
52 "OTP memory lock enable": false,
53 "Key Revision": "0x0",
54 "Secure boot header offset": "0x0",
55 "Boot From UART Port Selection": "UART5",
56 "Disable Auto Boot from UART": false,
57 "Disable Auto Boot from VUART2 over PCIE": true,
58 "Disable Auto Boot from VUART2 over LPC": true,
59 "Disable ROM code based programming control": true,
60 "Rollback prevention shift bit number": "0x0",
61 "Extra Data Write Protection Region Size": "0x0",
62 "Erase signature data after secure boot check": false,
63 "Erase RSA public key after secure boot check": false,
64 "Keys Retire ID": 0,
65 "User define data: random number low": "0x0",
66 "User define data: random number high": "0x0",
67 "Manifest ID": "0x0",
68 "Patch code location": "0x0",
69 "Patch code size": "0x0"
70 },
71 "otp_strap": {
72 "Enable secure boot": { "value": false },
73 "Enable boot from eMMC": { "value": true },
74 "Boot from debug SPI": { "value": false },
75 "Disable ARM CM3": { "value": true },
76 "Enable dedicated VGA BIOS ROM": { "value": false },
77 "MAC 1 RMII mode": { "value": "RMII/NCSI" },
78 "MAC 2 RMII mode": { "value": "RMII/NCSI" },
79 "CPU frequency": { "value": "1.2GHz" },
80 "HCLK ratio": { "value": "default" },
81 "VGA memory size": { "value": "16MB" },
82 "CPU/AXI clock ratio": { "value": "2:1" },
83 "Disable ARM JTAG debug": { "value": true },
84 "VGA class code": { "value": "vga_device" },
85 "Disable debug 0": { "value": false },
86 "Boot from eMMC speed mode": { "value": "normal" },
87 "Enable PCIe EHCI": { "value": false },
88 "Disable ARM JTAG trust world debug": { "value": true },
89 "Disable dedicated BMC function": { "value": false },
90 "Enable dedicate PCIe RC reset": { "value": false },
91 "Disable watchdog to reset full chip": { "value": false },
92 "Internal bridge speed selection": { "value": "1x" },
93 "Disable RVAS function": { "value": false },
94 "MAC 3 RMII mode": { "value": "RMII/NCSI" },
95 "MAC 4 RMII mode": { "value": "RMII/NCSI" },
96 "SuperIO configuration address selection": { "value": "0x2e" },
97 "Disable LPC to decode SuperIO": { "value": true },
98 "Disable debug 1": { "value": false },
99 "Enable ACPI": { "value": false },
100 "Select LPC/eSPI": { "value": "LPC" },
101 "Enable SAFS": { "value": false },
102 "Enable boot from uart5": { "value": false },
103 "Enable boot SPI 3B address mode auto-clear": { "value": false },
104 "Enable SPI 3B/4B address mode auto detection": { "value": false },
105 "Enable boot SPI or eMMC ABR": { "value": true },
106 "Boot SPI ABR Mode": { "value": "dual" },
107 "Boot SPI flash size": { "value": "0" },
108 "Enable host SPI ABR": { "value": false },
109 "Enable host SPI ABR mode select pin": { "value": false },
110 "Host SPI ABR Mode": { "value": "dual" },
111 "Host SPI flash size": { "value": "0" },
112 "Enable boot SPI auxiliary control pins": { "value": false },
113 "Boot SPI CRTM size": { "value": "0" },
114 "Host SPI CRTM size": { "value": "0" },
115 "Enable host SPI auxiliary control pins": { "value": false },
116 "Enable GPIO Pass Through": { "value": false },
117 "Enable Dedicate GPIO Strap Pins": { "value": false }
118 }
119}