Get pib target for processor register access
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I4eeb4b7b79653724db67eaa881a5362072eef763
diff --git a/analyzer/hei_user_interface.cpp b/analyzer/hei_user_interface.cpp
index a0b3ba6..ee87f79 100644
--- a/analyzer/hei_user_interface.cpp
+++ b/analyzer/hei_user_interface.cpp
@@ -15,6 +15,86 @@
namespace libhei
{
+const char* __regType(RegisterType_t i_regType)
+{
+ const char* str = "";
+ switch (i_regType)
+ {
+ case REG_TYPE_SCOM:
+ str = "SCOM";
+ break;
+ case REG_TYPE_ID_SCOM:
+ str = "ID_SCOM";
+ break;
+ default:
+ trace::err("Unsupported register type: i_regType=0x%02x",
+ i_regType);
+ assert(0);
+ }
+ return str;
+}
+
+//------------------------------------------------------------------------------
+
+bool __readProc(pdbg_target* i_procTrgt, RegisterType_t i_regType,
+ uint64_t i_address, uint64_t& o_value)
+{
+ bool accessFailure = false;
+
+ // The processor PIB target is required for SCOM access.
+ char path[16];
+ sprintf(path, "/proc%d/pib", pdbg_target_index(i_procTrgt));
+ pdbg_target* scomTrgt = pdbg_target_from_path(nullptr, path);
+ assert(nullptr != scomTrgt);
+
+ switch (i_regType)
+ {
+ case REG_TYPE_SCOM:
+ case REG_TYPE_ID_SCOM:
+ // Read the 64-bit SCOM register.
+ accessFailure = (0 != pib_read(scomTrgt, i_address, &o_value));
+ break;
+
+ default:
+ trace::err("Unsupported register type: trgt=%s regType=0x%02x "
+ "addr=0x%0" PRIx64,
+ pdbg_target_path(i_procTrgt), i_regType, i_address);
+ assert(0); // an unsupported register type
+ }
+
+ return accessFailure;
+}
+
+//------------------------------------------------------------------------------
+
+bool __readOcmb(pdbg_target* i_obmcTrgt, RegisterType_t i_regType,
+ uint64_t i_address, uint64_t& o_value)
+{
+ bool accessFailure = false;
+
+ /* TODO: ocmb_getscom() currently does not exist upstream.
+ // The OCMB target is used for SCOM access.
+ pdbg_target* scomTrgt = i_obmcTrgt;
+
+ switch (i_regType)
+ {
+ case REG_TYPE_SCOM:
+ case REG_TYPE_ID_SCOM:
+ // Read the 64-bit SCOM register.
+ accessFailure = (0 != ocmb_getscom(scomTrgt, i_address, &o_value));
+ break;
+
+ default:
+ trace::err("Unsupported register type: trgt=%s regType=0x%02x "
+ "addr=0x%0" PRIx64,
+ pdbg_target_path(i_obmcTrgt), i_regType, i_address);
+ assert(0);
+ }
+ */
+
+ return accessFailure;
+}
+
//------------------------------------------------------------------------------
bool registerRead(const Chip& i_chip, RegisterType_t i_regType,
@@ -24,23 +104,29 @@
auto trgt = (pdbg_target*)(i_chip.getChip());
- switch (i_regType)
+ uint8_t trgtType = 0;
+ pdbg_target_get_attribute(trgt, "ATTR_TYPE", 1, 1, &trgtType);
+
+ switch (trgtType)
{
- case REG_TYPE_SCOM:
- case REG_TYPE_ID_SCOM:
- // Read the 64-bit SCOM register.
- accessFailure = (0 != pib_read(trgt, i_address, &o_value));
+ case 0x05: // PROC
+ accessFailure = __readProc(trgt, i_regType, i_address, o_value);
+ break;
+
+ case 0x4b: // OCMB_CHIP
+ accessFailure = __readOcmb(trgt, i_regType, i_address, o_value);
break;
default:
- assert(0); // an unsupported register type
+ trace::err("Unsupported target type: trgt=%s trgtType=0x%02x",
+ pdbg_target_path(trgt), trgtType);
+ assert(0);
}
if (accessFailure)
{
- trace::err("Register read failed: chip=%s type=0x%0" PRIx8
- "addr=0x%0" PRIx64,
- pdbg_target_path(trgt), i_regType, i_address);
+ trace::err("%s failure: trgt=%s addr=0x%0" PRIx64, __regType(i_regType),
+ pdbg_target_path(trgt), i_address);
o_value = 0; // just in case
}