diff --git a/analyzer/plugins/p10-plugins.cpp b/analyzer/plugins/p10-plugins.cpp
index dd14457..7e20d2d 100644
--- a/analyzer/plugins/p10-plugins.cpp
+++ b/analyzer/plugins/p10-plugins.cpp
@@ -1,5 +1,7 @@
 
 #include <analyzer/plugins/plugin.hpp>
+#include <hei_util.hpp>
+#include <util/pdbg.hpp>
 #include <util/trace.hpp>
 
 namespace analyzer
@@ -17,10 +19,44 @@
  *  clock, the clock is called out with high priority. Otherwise, the clock
  *  callout priority is medium.
  */
-void pll_unlock(unsigned int i_instance, const libhei::Chip&, ServiceData&)
+void pll_unlock(unsigned int i_instance, const libhei::Chip&,
+                ServiceData& io_servData)
 {
-    // TODO
-    trace::inf("pll_unlock plugin: i_instance=%u", i_instance);
+    auto nodeId = libhei::hash<libhei::NodeId_t>("PLL_UNLOCK");
+
+    auto sigList = io_servData.getIsolationData().getSignatureList();
+
+    // The PLL list is initially the same size of the signature list.
+    std::vector<libhei::Signature> pllList{sigList.size()};
+
+    // Copy all signatures that match the node ID and bit position. Note that
+    // in this case the bit position is the same as the plugin instance.
+    auto itr = std::copy_if(sigList.begin(), sigList.end(), pllList.begin(),
+                            [&nodeId, &i_instance](const auto& s) {
+                                return (nodeId == s.getId() &&
+                                        i_instance == s.getBit());
+                            });
+
+    // Shrink the size of the PLL list if necessary.
+    pllList.resize(std::distance(pllList.begin(), itr));
+
+    // The clock callout priority is dependent on the number of chips with PLL
+    // unlock attentions.
+    auto clockPriority =
+        (1 < pllList.size()) ? callout::Priority::HIGH : callout::Priority::MED;
+
+    // Callout the clock.
+    auto clockCallout = (0 == i_instance) ? callout::ClockType::OSC_REF_CLOCK_0
+                                          : callout::ClockType::OSC_REF_CLOCK_1;
+    io_servData.calloutClock(clockCallout, clockPriority, true);
+
+    // Callout the processors connected to this clock that are reporting PLL
+    // unlock attentions. Always a medium callout and no guarding.
+    for (const auto& sig : pllList)
+    {
+        io_servData.calloutTarget(util::pdbg::getTrgt(sig.getChip()),
+                                  callout::Priority::MED, false);
+    }
 }
 
 } // namespace P10
diff --git a/analyzer/ras-data/data/ras-data-p10-10.json b/analyzer/ras-data/data/ras-data-p10-10.json
index d31ddc5..3c8f88c 100644
--- a/analyzer/ras-data/data/ras-data-p10-10.json
+++ b/analyzer/ras-data/data/ras-data-p10-10.json
@@ -936,12 +936,10 @@
             { "type": "action", "name": "self_L" }
         ],
         "pll_unlock_0": [
-            { "type": "plugin", "name": "pll_unlock", "instance": 0 },
-            { "type": "callout_self", "priority": "MED", "guard": false }
+            { "type": "plugin", "name": "pll_unlock", "instance": 0 }
         ],
         "pll_unlock_1": [
-            { "type": "plugin", "name": "pll_unlock", "instance": 1 },
-            { "type": "callout_self", "priority": "MED", "guard": false }
+            { "type": "plugin", "name": "pll_unlock", "instance": 1 }
         ],
         "pcb_slave_parity": [
             { "type": "action", "name": "self_H" }
diff --git a/analyzer/ras-data/data/ras-data-p10-20.json b/analyzer/ras-data/data/ras-data-p10-20.json
index 8ed5f00..a9dc314 100644
--- a/analyzer/ras-data/data/ras-data-p10-20.json
+++ b/analyzer/ras-data/data/ras-data-p10-20.json
@@ -936,12 +936,10 @@
             { "type": "action", "name": "self_L" }
         ],
         "pll_unlock_0": [
-            { "type": "plugin", "name": "pll_unlock", "instance": 0 },
-            { "type": "callout_self", "priority": "MED", "guard": false }
+            { "type": "plugin", "name": "pll_unlock", "instance": 0 }
         ],
         "pll_unlock_1": [
-            { "type": "plugin", "name": "pll_unlock", "instance": 1 },
-            { "type": "callout_self", "priority": "MED", "guard": false }
+            { "type": "plugin", "name": "pll_unlock", "instance": 1 }
         ],
         "pcb_slave_parity": [
             { "type": "action", "name": "self_H" }