Attn: Do not always trace hostboot registers
Only trace hostboot registers if we are handling a checkstop or TI.
Signed-off-by: Ben Tyner <ben.tyner@ibm.com>
Change-Id: I66f234b424dbd36e8789c64c9a9e82a3a0e75d44
diff --git a/attn/attn_common.cpp b/attn/attn_common.cpp
index fce3d54..4f333e8 100644
--- a/attn/attn_common.cpp
+++ b/attn/attn_common.cpp
@@ -1,8 +1,12 @@
#include <libpdbg.h>
#include <attn/attn_common.hpp>
+#include <attn/attn_logging.hpp>
#include <sdbusplus/bus.hpp>
+#include <util/pdbg.hpp>
+#include <iomanip>
+#include <iostream>
#include <map>
namespace attn
@@ -34,4 +38,76 @@
bus.call_noreply(method); // start the service
}
+/** @brief Traces some regs for hostboot */
+void addHbStatusRegs()
+{
+ // Only do this for P10 systems
+ if (util::pdbg::queryHardwareAnalysisSupported())
+ {
+ // We only need this for PRIMARY processor
+ pdbg_target* pibTarget = pdbg_target_from_path(nullptr, "/proc0/pib");
+ pdbg_target* fsiTarget = pdbg_target_from_path(nullptr, "/proc0/fsi");
+
+ uint32_t l_cfamData = 0xFFFFFFFF;
+ uint64_t l_scomData1 = 0xFFFFFFFFFFFFFFFFull;
+ uint64_t l_scomData2 = 0xFFFFFFFFFFFFFFFFull;
+ uint32_t l_cfamAddr = 0x283C;
+ uint64_t l_scomAddr1 = 0x4602F489;
+ uint64_t l_scomAddr2 = 0x4602F487;
+
+ if ((nullptr != fsiTarget) && (nullptr != pibTarget))
+ {
+ // get first debug reg (CFAM)
+ if (RC_SUCCESS != fsi_read(fsiTarget, l_cfamAddr, &l_cfamData))
+ {
+ eventAttentionFail((int)AttnSection::addHbStatusRegs |
+ ATTN_PDBG_CFAM);
+ l_cfamData = 0xFFFFFFFF;
+ }
+
+ // Get SCOM regs next (just 2 of them)
+ if (RC_SUCCESS != pib_read(pibTarget, l_scomAddr1, &l_scomData1))
+ {
+ eventAttentionFail((int)AttnSection::addHbStatusRegs |
+ ATTN_PDBG_SCOM);
+ l_scomData1 = 0xFFFFFFFFFFFFFFFFull;
+ }
+
+ if (RC_SUCCESS != pib_read(pibTarget, l_scomAddr2, &l_scomData2))
+ {
+ eventAttentionFail((int)AttnSection::addHbStatusRegs |
+ ATTN_PDBG_SCOM);
+ l_scomData2 = 0xFFFFFFFFFFFFFFFFull;
+ }
+ }
+
+ // Trace out the results here of all 3 regs
+ // (Format should resemble FSP: HostBoot Reg:0000283C Data:AA801504
+ // 00000000 Proc:00050001 )
+ std::stringstream ss1, ss2, ss3;
+
+ ss1 << "HostBoot Reg:" << std::setw(8) << std::setfill('0') << std::hex
+ << l_cfamAddr << " Data:" << l_cfamData << " Proc:00000000";
+
+ ss2 << "HostBoot Reg:" << std::setw(8) << std::setfill('0') << std::hex
+ << l_scomAddr1 << " Data:" << std::setw(16) << l_scomData1
+ << " Proc:00000000";
+
+ ss3 << "HostBoot Reg:" << std::setw(8) << std::setfill('0') << std::hex
+ << l_scomAddr2 << " Data:" << std::setw(16) << l_scomData2
+ << " Proc:00000000";
+
+ std::string strobj1 = ss1.str();
+ std::string strobj2 = ss2.str();
+ std::string strobj3 = ss3.str();
+
+ trace<level::INFO>(strobj1.c_str());
+ trace<level::INFO>(strobj2.c_str());
+ trace<level::INFO>(strobj3.c_str());
+ }
+
+ return;
+
+} // end addHbStatusRegs
+
} // namespace attn
diff --git a/attn/attn_common.hpp b/attn/attn_common.hpp
index 7d8ed34..67d3f71 100644
--- a/attn/attn_common.hpp
+++ b/attn/attn_common.hpp
@@ -3,6 +3,36 @@
namespace attn
{
+/** @brief Attention handler return codes */
+enum ReturnCodes
+{
+ RC_SUCCESS = 0,
+ RC_NOT_HANDLED = 1,
+ RC_ANALYZER_ERROR = 2,
+ RC_CFAM_ERROR = 3,
+ RC_DBUS_ERROR = 4
+};
+
+/** @brief Code seciton for error reporing */
+enum class AttnSection
+{
+ reserved = 0x0000,
+ attnHandler = 0x0100,
+ tiHandler = 0x0200,
+ handlePhypTi = 0x0300,
+ handleHbTi = 0x0400,
+ addHbStatusRegs = 0x0500
+};
+
+/** @brief Attention handler error reason codes */
+enum AttnCodes
+{
+ ATTN_NO_ERROR = 0,
+ ATTN_INFO_NULL = 1,
+ ATTN_PDBG_CFAM = 2,
+ ATTN_PDBG_SCOM = 3
+};
+
enum class HostState
{
Quiesce,
@@ -19,4 +49,16 @@
*/
void transitionHost(const HostState i_hostState);
+/**
+ * @brief Traces some regs for hostboot
+ *
+ * When we receive a Checkstop or special Attention Term Immediate,
+ * hostboot wants some regs added to the error log. We will do this
+ * by tracing them and then the traces will get added to the error
+ * log later.
+ *
+ * @return nothing
+ */
+void addHbStatusRegs();
+
} // namespace attn
diff --git a/attn/attn_dbus.cpp b/attn/attn_dbus.cpp
index faf5e1f..a82e5ce 100644
--- a/attn/attn_dbus.cpp
+++ b/attn/attn_dbus.cpp
@@ -1,5 +1,5 @@
+#include <attn_common.hpp>
#include <attn_dbus.hpp>
-#include <attn_handler.hpp>
#include <attn_logging.hpp>
#include <xyz/openbmc_project/State/Boot/Progress/server.hpp>
diff --git a/attn/attn_handler.cpp b/attn/attn_handler.cpp
index b1fa27b..c1a4b48 100644
--- a/attn/attn_handler.cpp
+++ b/attn/attn_handler.cpp
@@ -47,18 +47,6 @@
bool activeAttn(uint32_t i_val, uint32_t i_mask, uint32_t i_attn);
/**
- * @brief Traces some regs for hostboot
- *
- * @param i_procIndex - processor number (used in traces)
- * @param i_pibTarget - target used for doing SCOMs to the processor
- * @param i_fsiTarget - target used for doing CFAMs to the processor
- *
- * @return nothing
- */
-void addHbStatusRegs(uint32_t i_procIndex, pdbg_target* i_pibTarget,
- pdbg_target* i_fsiTarget);
-
-/**
* @brief The main attention handler logic
*
* @param i_breakpoints true = breakpoint special attn handling enabled
@@ -165,15 +153,6 @@
handleVital, target,
i_config);
}
- else
- {
- // Hostboot wants some debug regs on Checkstops/TIs.
- // Don't bother on SBE Vitals (scoms will fail).
- // Only need to do on primary proc if you know what
- // it is, but eBMC may not so we will dump all
- // procs.
- addHbStatusRegs(proc, pibTarget, fsiTarget);
- } // Not SBE Vital attention
// Checkstop attention active and not masked?
if (true ==
@@ -235,6 +214,9 @@
trace<level::INFO>("checkstop handler started");
+ // capture some additional data for logs/traces
+ addHbStatusRegs();
+
// if checkstop handling enabled, handle checkstop attention
if (false == (i_attention->getConfig()->getFlag(enCheckstop)))
{
@@ -470,80 +452,4 @@
return rc;
}
-
-/**
- * @brief Traces some regs for hostboot
- *
- * When we receive a Checkstop or special Attention Term Immediate,
- * hostboot wants some regs added to the error log. We will do this
- * by tracing them here and then the traces will get added to
- * the error log later
- *
- * @param i_procIndex - processor number (used in traces)
- * @param i_pibTarget - target used for doing SCOMs to the processor
- * @param i_fsiTarget - target used for doing CFAMs to the processor
- *
- * @return nothing
- */
-void addHbStatusRegs(uint32_t i_procIndex, pdbg_target* i_pibTarget,
- pdbg_target* i_fsiTarget)
-{
- uint32_t l_cfamData = 0xFFFFFFFF;
- uint64_t l_scomData1 = 0xFFFFFFFFFFFFFFFFull;
- uint64_t l_scomData2 = 0xFFFFFFFFFFFFFFFFull;
- uint32_t l_cfamAddr = 0x283C;
- uint64_t l_scomAddr1 = 0x4602F489;
- uint64_t l_scomAddr2 = 0x4602F487;
-
- // We only need this for PRIMARY proc, but will just do on all procs for
- // now. All attentions handled are fatal (except for plain breakpoints). Not
- // going to sweat the plain breakpoint case since this is lab only using
- // cronus.
-
- // get first debug reg (CFAM)
- if (RC_SUCCESS != fsi_read(i_fsiTarget, l_cfamAddr, &l_cfamData))
- {
- l_cfamData = 0xFFFFFFFF;
- }
-
- // Get SCOM regs next (just 2 of them)
- if (RC_SUCCESS != pib_read(i_pibTarget, l_scomAddr1, &l_scomData1))
- {
- l_scomData1 = 0xFFFFFFFFFFFFFFFFull;
- }
-
- if (RC_SUCCESS != pib_read(i_pibTarget, l_scomAddr2, &l_scomData2))
- {
- l_scomData2 = 0xFFFFFFFFFFFFFFFFull;
- }
-
- // Trace out the results here of all 3 regs
- // (Format should resemble FSP: HostBoot Reg:0000283C Data:AA801504
- // 00000000 Proc:00050001 )
- std::stringstream ss1, ss2, ss3;
-
- ss1 << "HostBoot Reg:" << std::setw(8) << std::setfill('0') << std::hex
- << l_cfamAddr << " Data:" << l_cfamData << " Proc:" << std::setw(8)
- << i_procIndex;
-
- ss2 << "HostBoot Reg:" << std::setw(8) << std::setfill('0') << std::hex
- << l_scomAddr1 << " Data:" << std::setw(16) << l_scomData1
- << " Proc:" << std::setw(8) << i_procIndex;
-
- ss3 << "HostBoot Reg:" << std::setw(8) << std::setfill('0') << std::hex
- << l_scomAddr2 << " Data:" << std::setw(16) << l_scomData2
- << " Proc:" << std::setw(8) << i_procIndex;
-
- std::string strobj1 = ss1.str();
- std::string strobj2 = ss2.str();
- std::string strobj3 = ss3.str();
-
- trace<level::INFO>(strobj1.c_str());
- trace<level::INFO>(strobj2.c_str());
- trace<level::INFO>(strobj3.c_str());
-
- return;
-
-} // end addHbStatusRegs
-
} // namespace attn
diff --git a/attn/attn_handler.hpp b/attn/attn_handler.hpp
index 770f6e9..41ed409 100644
--- a/attn/attn_handler.hpp
+++ b/attn/attn_handler.hpp
@@ -5,34 +5,6 @@
namespace attn
{
-/** @brief Attention handler return codes */
-enum ReturnCodes
-{
- RC_SUCCESS = 0,
- RC_NOT_HANDLED = 1,
- RC_ANALYZER_ERROR = 2,
- RC_CFAM_ERROR = 3,
- RC_DBUS_ERROR = 4
-};
-
-/** @brief Code seciton for error reporing */
-enum class AttnSection
-{
- reserved = 0x0000,
- attnHandler = 0x0100,
- tiHandler = 0x0200,
- handlePhypTi = 0x0300,
- handleHbTi = 0x0400
-};
-
-/** @brief Attention handler error reason codes */
-enum AttnCodes
-{
- ATTN_NO_ERROR = 0,
- ATTN_INFO_NULL = 1,
- ATTN_PDBG_CFAM = 2
-};
-
/** @brief Attention global status bits */
constexpr uint32_t SBE_ATTN = 0x00000002;
constexpr uint32_t CHECKSTOP_ATTN = 0x40000000;
diff --git a/attn/bp_handler.cpp b/attn/bp_handler.cpp
index 408fe58..1e36526 100644
--- a/attn/bp_handler.cpp
+++ b/attn/bp_handler.cpp
@@ -1,4 +1,4 @@
-#include <attn/attn_handler.hpp>
+#include <attn/attn_common.hpp>
#include <attn/attn_logging.hpp>
#include <sdbusplus/bus.hpp>
diff --git a/attn/ti_handler.cpp b/attn/ti_handler.cpp
index 8ecb64b..2000331 100644
--- a/attn/ti_handler.cpp
+++ b/attn/ti_handler.cpp
@@ -1,6 +1,5 @@
#include <attn/attn_common.hpp>
#include <attn/attn_dbus.hpp>
-#include <attn/attn_handler.hpp>
#include <attn/attn_logging.hpp>
#include <attn/pel/pel_common.hpp>
#include <attn/ti_handler.hpp>
@@ -25,6 +24,9 @@
{
int rc = RC_SUCCESS;
+ // capture some additional data for logs/traces
+ addHbStatusRegs();
+
// check TI data area if it is available
if (nullptr != i_tiDataArea)
{
diff --git a/attn/vital_handler.cpp b/attn/vital_handler.cpp
index 15a7a68..b0a771e 100644
--- a/attn/vital_handler.cpp
+++ b/attn/vital_handler.cpp
@@ -1,6 +1,5 @@
#include <attn/attention.hpp>
#include <attn/attn_common.hpp>
-#include <attn/attn_handler.hpp>
#include <attn/attn_logging.hpp>
#include <sdbusplus/bus.hpp>
diff --git a/test/end2end/vital_handler.cpp b/test/end2end/vital_handler.cpp
index 177a0ae..5866d71 100644
--- a/test/end2end/vital_handler.cpp
+++ b/test/end2end/vital_handler.cpp
@@ -1,5 +1,5 @@
#include <attn/attention.hpp> // for Attention
-#include <attn/attn_handler.hpp> // for RC_SUCCESS
+#include <attn/attn_common.hpp> // for RC_SUCCESS
#include <attn/attn_logging.hpp> // for trace
namespace attn