Add Hostboot scratch registers to PEL
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I8f095b49ec204e6e33afc0ab300beeab5d3759a9
diff --git a/util/pdbg.cpp b/util/pdbg.cpp
index fb36a8e..d4170a7 100644
--- a/util/pdbg.cpp
+++ b/util/pdbg.cpp
@@ -107,6 +107,27 @@
//------------------------------------------------------------------------------
+int getScom(pdbg_target* i_trgt, uint64_t i_addr, uint64_t& o_val)
+{
+ // Only processor targets are supported.
+ // TODO: Will need to add OCMB support later.
+ assert(TYPE_PROC == getTrgtType(i_trgt));
+
+ auto pibTrgt = util::pdbg::getPibTrgt(i_trgt);
+
+ int rc = pib_read(pibTrgt, i_addr, &o_val);
+
+ if (0 != rc)
+ {
+ trace::err("pib_read failure: target=%s addr=0x%0" PRIx64,
+ util::pdbg::getPath(pibTrgt), i_addr);
+ }
+
+ return rc;
+}
+
+//------------------------------------------------------------------------------
+
int getCfam(pdbg_target* i_trgt, uint32_t i_addr, uint32_t& o_val)
{
// Only processor targets are supported.
@@ -118,7 +139,7 @@
if (0 != rc)
{
- trace::err("fsi_read failure: trgt=%s addr=0x%08x",
+ trace::err("fsi_read failure: target=%s addr=0x%08x",
util::pdbg::getPath(fsiTrgt), i_addr);
}
@@ -230,6 +251,16 @@
//------------------------------------------------------------------------------
+pdbg_target* getPrimaryProcessor()
+{
+ // TODO: For at least P10, the primary processor (the one connected directly
+ // to the BMC), will always be PROC 0. We will need to update this
+ // later if we ever support an alternate primary processor.
+ return getTrgt("/proc0");
+}
+
+//------------------------------------------------------------------------------
+
bool queryHardwareAnalysisSupported()
{
// Hardware analysis is only supported on P10 systems and up.