Add Hostboot scratch registers to PEL
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I8f095b49ec204e6e33afc0ab300beeab5d3759a9
diff --git a/util/pdbg.hpp b/util/pdbg.hpp
index 2fabcf3..6c604ac 100644
--- a/util/pdbg.hpp
+++ b/util/pdbg.hpp
@@ -67,6 +67,16 @@
pdbg_target* getFsiTrgt(pdbg_target* i_procTrgt);
/**
+ * @brief Reads a SCOM register.
+ * @param i_trgt Given target.
+ * @param i_addr Given address.
+ * @param o_val The returned value of the register.
+ * @return 0 if successful, non-0 otherwise.
+ * @note Will assert the given target is a proc target.
+ */
+int getScom(pdbg_target* i_trgt, uint64_t i_addr, uint64_t& o_val);
+
+/**
* @brief Reads a CFAM FSI register.
* @param i_trgt Given target.
* @param i_addr Given address.
@@ -83,6 +93,11 @@
void getActiveChips(std::vector<libhei::Chip>& o_chips);
/**
+ * @return The primary processor (i.e. the processor connected to the BMC).
+ */
+pdbg_target* getPrimaryProcessor();
+
+/**
* @return True, if hardware analysis is supported on this system. False,
* otherwise.
* @note Support for hardware analysis from the BMC started with P10 systems