Updated analyzer root cause filtering for Odyssey special cases

This updates the RAS data analyzer's root cause filtering
to handle special cases for Odyssey OCMBs, in particular
ODP data corruption root causes, and firmware initiated
channel fails due to IUE threshold.

Signed-off-by: Caleb Palmer <cnpalmer@us.ibm.com>
Change-Id: Id22dd07b19a68007be0be3881d669eeee3a8078f
diff --git a/analyzer/filter-root-cause.cpp b/analyzer/filter-root-cause.cpp
index 4efcff0..5c4edf9 100644
--- a/analyzer/filter-root-cause.cpp
+++ b/analyzer/filter-root-cause.cpp
@@ -74,27 +74,6 @@
 
 //------------------------------------------------------------------------------
 
-bool __findIueTh(const std::vector<libhei::Signature>& i_list,
-                 libhei::Signature& o_rootCause)
-{
-    // TODO: These bit values propbably changed in Odyssey. Will need to
-    //       consider flags instead of arbitrary values.
-    auto itr = std::find_if(i_list.begin(), i_list.end(), [&](const auto& t) {
-        return (libhei::hash<libhei::NodeId_t>("RDFFIR") == t.getId() &&
-                (17 == t.getBit() || 37 == t.getBit()));
-    });
-
-    if (i_list.end() != itr)
-    {
-        o_rootCause = *itr;
-        return true;
-    }
-
-    return false;
-}
-
-//------------------------------------------------------------------------------
-
 bool __findMemoryChannelFailure(const std::vector<libhei::Signature>& i_list,
                                 libhei::Signature& o_rootCause,
                                 const RasDataParser& i_rasData)
@@ -107,7 +86,6 @@
     static const auto mc_dstl_fir = __hash("MC_DSTL_FIR");
     static const auto mc_ustl_fir = __hash("MC_USTL_FIR");
     static const auto mc_omi_dl_err_rpt = __hash("MC_OMI_DL_ERR_RPT");
-    static const auto srqfir = __hash("SRQFIR");
 
     // First, look for any chip checkstops from the connected OCMBs.
     for (const auto& s : i_list)
@@ -124,18 +102,6 @@
         if (libhei::ATTN_TYPE_CHIP_CS == s.getAttnType() ||
             libhei::ATTN_TYPE_UNIT_CS == s.getAttnType())
         {
-            // Special Case:
-            // If the channel fail was specifically a firmware initiated
-            // channel fail (SRQFIR[25]) check for any IUE bits that are on
-            // that would have caused that (RDFFIR[17,37]).
-            // TODO: These bit values probably changed in Odyssey. Will need to
-            //       consider flags instead of arbitrary values.
-            if ((srqfir == s.getId() && 25 == s.getBit()) &&
-                __findIueTh(i_list, o_rootCause))
-            {
-                return true;
-            }
-
             o_rootCause = s;
             return true;
         }
@@ -671,10 +637,9 @@
 
 //------------------------------------------------------------------------------
 
-bool filterRootCause(AnalysisType i_type,
-                     const libhei::IsolationData& i_isoData,
-                     libhei::Signature& o_rootCause,
-                     const RasDataParser& i_rasData)
+bool findRootCause(AnalysisType i_type, const libhei::IsolationData& i_isoData,
+                   libhei::Signature& o_rootCause,
+                   const RasDataParser& i_rasData)
 {
     // We'll need to make a copy of the list so that the original list is
     // maintained for the PEL.
@@ -776,4 +741,97 @@
 
 //------------------------------------------------------------------------------
 
+bool __findIueTh(const std::vector<libhei::Signature>& i_list,
+                 libhei::Signature& o_rootCause)
+{
+    auto itr = std::find_if(i_list.begin(), i_list.end(), [&](const auto& t) {
+        return (libhei::hash<libhei::NodeId_t>("RDFFIR") == t.getId() &&
+                (17 == t.getBit() || 37 == t.getBit())) ||
+               (libhei::hash<libhei::NodeId_t>("RDF_FIR") == t.getId() &&
+                (18 == t.getBit() || 38 == t.getBit()));
+    });
+
+    if (i_list.end() != itr)
+    {
+        o_rootCause = *itr;
+        return true;
+    }
+
+    return false;
+}
+
+//------------------------------------------------------------------------------
+
+void rootCauseSpecialCases(const libhei::IsolationData& i_isoData,
+                           libhei::Signature& o_rootCause,
+                           const RasDataParser& i_rasData)
+{
+    using func = libhei::NodeId_t (*)(const std::string& i_str);
+    func __hash = libhei::hash<libhei::NodeId_t>;
+
+    // Check for any special cases that exist for specific FIR bits.
+
+    // If the channel fail was specifically a firmware initiated channel fail
+    // (SRQFIR[25] for Explorer OCMBs, SRQ_FIR[46] for Odyssey OCMBs) check for
+    // any IUE bits that are on that would have caused the channel fail
+    // (RDFFIR[17,37] for Explorer OCMBs, RDF_FIR_0[18,38] or RDF_FIR_1[18,38]
+    // for Odyssey OCMBs).
+
+    // Explorer SRQFIR
+    static const auto srqfir = __hash("SRQFIR");
+    // Odyssey SRQ_FIR
+    static const auto srq_fir = __hash("SRQ_FIR");
+
+    std::vector<libhei::Signature> list{i_isoData.getSignatureList()};
+
+    if (((srqfir == o_rootCause.getId() && 25 == o_rootCause.getBit()) ||
+         (srq_fir == o_rootCause.getId() && 46 == o_rootCause.getBit())) &&
+        __findIueTh(list, o_rootCause))
+    {
+        // If __findIueTh returned true, o_rootCause was updated, return.
+        return;
+    }
+
+    // Check if the root cause found was a potential side effect of an
+    // ODP data corruption error. If it was, check if any other signature
+    // in the signature list was a potential root cause.
+    auto OdpSide = RasDataParser::RasDataFlags::ODP_DATA_CORRUPT_SIDE_EFFECT;
+    auto OdpRoot = RasDataParser::RasDataFlags::ODP_DATA_CORRUPT_ROOT_CAUSE;
+    if (i_rasData.isFlagSet(o_rootCause, OdpSide))
+    {
+        for (const auto& s : list)
+        {
+            if (i_rasData.isFlagSet(s, OdpRoot))
+            {
+                // ODP data corruption root cause found, return.
+                o_rootCause = s;
+                return;
+            }
+        }
+    }
+}
+
+//------------------------------------------------------------------------------
+
+bool filterRootCause(AnalysisType i_type,
+                     const libhei::IsolationData& i_isoData,
+                     libhei::Signature& o_rootCause,
+                     const RasDataParser& i_rasData)
+{
+    // Find the initial root cause attention based on common rules for FIR
+    // isolation.
+    bool rc = findRootCause(i_type, i_isoData, o_rootCause, i_rasData);
+
+    // If some root cause was found, handle any special cases for specific FIR
+    // bits that require additional logic to determine the root cause.
+    if (true == rc)
+    {
+        rootCauseSpecialCases(i_isoData, o_rootCause, i_rasData);
+    }
+
+    return rc;
+}
+
+//------------------------------------------------------------------------------
+
 } // namespace analyzer
diff --git a/analyzer/ras-data/data/ras-data-odyssey-10.json b/analyzer/ras-data/data/ras-data-odyssey-10.json
index e870eb5..3679c69 100644
--- a/analyzer/ras-data/data/ras-data-odyssey-10.json
+++ b/analyzer/ras-data/data/ras-data-odyssey-10.json
@@ -2,11 +2,11 @@
     "actions": {
         "TBD": [
             {
-                "name": "level2_M_th1",
+                "name": "level2_M_th_1",
                 "type": "action"
             }
         ],
-        "dimm0_H_mem_port0_L_th1": [
+        "dimm0_H_mem_port0_L_th_1": [
             {
                 "guard": true,
                 "name": "dimm0",
@@ -50,7 +50,7 @@
                 "type": "callout_unit"
             }
         ],
-        "dimm0_M_th1": [
+        "dimm0_M_th_1": [
             {
                 "name": "dimm0_M",
                 "type": "action"
@@ -60,7 +60,7 @@
                 "type": "action"
             }
         ],
-        "dimm1_H_mem_port1_L_th1": [
+        "dimm1_H_mem_port1_L_th_1": [
             {
                 "guard": true,
                 "name": "dimm1",
@@ -104,7 +104,7 @@
                 "type": "callout_unit"
             }
         ],
-        "dimm1_M_th1": [
+        "dimm1_M_th_1": [
             {
                 "name": "dimm1_M",
                 "type": "action"
@@ -116,7 +116,7 @@
         ],
         "downstream_attn": [
             {
-                "name": "level2_M_th1",
+                "name": "level2_M_th_1",
                 "type": "action"
             }
         ],
@@ -127,7 +127,7 @@
                 "type": "callout_procedure"
             }
         ],
-        "level2_M_ocmb_L_th1": [
+        "level2_M_ocmb_L_th_1": [
             {
                 "name": "level2_M",
                 "type": "action"
@@ -142,7 +142,7 @@
                 "type": "action"
             }
         ],
-        "level2_M_th1": [
+        "level2_M_th_1": [
             {
                 "name": "level2_M",
                 "type": "action"
@@ -154,61 +154,61 @@
         ],
         "mainline_iue_handling_0": [
             {
-                "name": "dimm0_M_th1",
+                "name": "dimm0_M_th_1",
                 "type": "action"
             }
         ],
         "mainline_iue_handling_1": [
             {
-                "name": "dimm1_M_th1",
+                "name": "dimm1_M_th_1",
                 "type": "action"
             }
         ],
         "mainline_nce_tce_handling": [
             {
-                "name": "ocmb_M_th1",
+                "name": "ocmb_M_th_1",
                 "type": "action"
             }
         ],
         "mainline_ue_handling_0": [
             {
-                "name": "dimm0_M_th1",
+                "name": "dimm0_M_th_1",
                 "type": "action"
             }
         ],
         "mainline_ue_handling_1": [
             {
-                "name": "dimm1_M_th1",
+                "name": "dimm1_M_th_1",
                 "type": "action"
             }
         ],
         "maintenance_aue_handling_0": [
             {
-                "name": "dimm0_H_mem_port0_L_th1",
+                "name": "dimm0_H_mem_port0_L_th_1",
                 "type": "action"
             }
         ],
         "maintenance_aue_handling_1": [
             {
-                "name": "dimm1_H_mem_port1_L_th1",
+                "name": "dimm1_H_mem_port1_L_th_1",
                 "type": "action"
             }
         ],
         "maintenance_iue_handling_0": [
             {
-                "name": "dimm0_M_th1",
+                "name": "dimm0_M_th_1",
                 "type": "action"
             }
         ],
         "maintenance_iue_handling_1": [
             {
-                "name": "dimm1_M_th1",
+                "name": "dimm1_M_th_1",
                 "type": "action"
             }
         ],
         "mcbist_program_complete": [
             {
-                "name": "level2_M_th1",
+                "name": "level2_M_th_1",
                 "type": "action"
             }
         ],
@@ -230,7 +230,7 @@
                 "type": "flag"
             }
         ],
-        "mem_port0_M_th1": [
+        "mem_port0_M_th_1": [
             {
                 "name": "mem_port0_M",
                 "type": "action"
@@ -268,7 +268,7 @@
                 "type": "flag"
             }
         ],
-        "mem_port1_M_th1": [
+        "mem_port1_M_th_1": [
             {
                 "name": "mem_port1_M",
                 "type": "action"
@@ -290,17 +290,17 @@
         ],
         "memory_impe_handling_0": [
             {
-                "name": "dimm0_M_th1",
+                "name": "dimm0_M_th_1",
                 "type": "action"
             }
         ],
         "memory_impe_handling_1": [
             {
-                "name": "dimm1_M_th1",
+                "name": "dimm1_M_th_1",
                 "type": "action"
             }
         ],
-        "ocmb_H_omi_L_th1": [
+        "ocmb_H_omi_L_th_1": [
             {
                 "guard": true,
                 "priority": "HIGH",
@@ -334,9 +334,9 @@
                 "type": "flag"
             }
         ],
-        "ocmb_M_info_only_th1": [
+        "ocmb_M_info_only_th_1": [
             {
-                "name": "ocmb_M_th1",
+                "name": "ocmb_M_th_1",
                 "type": "action"
             },
             {
@@ -344,7 +344,7 @@
                 "type": "flag"
             }
         ],
-        "ocmb_M_level2_L_th1": [
+        "ocmb_M_level2_L_th_1": [
             {
                 "name": "ocmb_M",
                 "type": "action"
@@ -359,7 +359,7 @@
                 "type": "action"
             }
         ],
-        "ocmb_M_th1": [
+        "ocmb_M_th_1": [
             {
                 "name": "ocmb_M",
                 "type": "action"
@@ -387,7 +387,7 @@
                 "type": "callout_connected"
             }
         ],
-        "omi_M_th1": [
+        "omi_M_th_1": [
             {
                 "name": "omi_M",
                 "type": "action"
@@ -436,7 +436,7 @@
                 "type": "flag"
             }
         ],
-        "omi_bus_th1": [
+        "omi_bus_th_1": [
             {
                 "name": "omi_bus",
                 "type": "action"
@@ -458,7 +458,7 @@
         ],
         "omi_degraded_mode": [
             {
-                "name": "omi_bus_th1",
+                "name": "omi_bus_th_1",
                 "type": "action"
             }
         ],
@@ -481,19 +481,19 @@
         ],
         "srq_rcd_parity_error_0": [
             {
-                "name": "dimm0_H_mem_port0_L_th1",
+                "name": "dimm0_H_mem_port0_L_th_1",
                 "type": "action"
             }
         ],
         "srq_rcd_parity_error_1": [
             {
-                "name": "dimm1_H_mem_port1_L_th1",
+                "name": "dimm1_H_mem_port1_L_th_1",
                 "type": "action"
             }
         ],
         "srq_recov_parity_error": [
             {
-                "name": "ocmb_M_th1",
+                "name": "ocmb_M_th_1",
                 "type": "action"
             }
         ],
@@ -506,49 +506,49 @@
         ],
         "verify_chip_mark_0": [
             {
-                "name": "ocmb_M_th1",
+                "name": "ocmb_M_th_1",
                 "type": "action"
             }
         ],
         "verify_chip_mark_1": [
             {
-                "name": "ocmb_M_th1",
+                "name": "ocmb_M_th_1",
                 "type": "action"
             }
         ],
         "verify_chip_mark_2": [
             {
-                "name": "ocmb_M_th1",
+                "name": "ocmb_M_th_1",
                 "type": "action"
             }
         ],
         "verify_chip_mark_3": [
             {
-                "name": "ocmb_M_th1",
+                "name": "ocmb_M_th_1",
                 "type": "action"
             }
         ],
         "verify_chip_mark_4": [
             {
-                "name": "ocmb_M_th1",
+                "name": "ocmb_M_th_1",
                 "type": "action"
             }
         ],
         "verify_chip_mark_5": [
             {
-                "name": "ocmb_M_th1",
+                "name": "ocmb_M_th_1",
                 "type": "action"
             }
         ],
         "verify_chip_mark_6": [
             {
-                "name": "ocmb_M_th1",
+                "name": "ocmb_M_th_1",
                 "type": "action"
             }
         ],
         "verify_chip_mark_7": [
             {
-                "name": "ocmb_M_th1",
+                "name": "ocmb_M_th_1",
                 "type": "action"
             }
         ]
@@ -562,225 +562,225 @@
     "signatures": {
         "0cbf": {
             "00": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "01": {
-                "00": "mem_port0_M_th1",
-                "01": "mem_port1_M_th1"
+                "00": "mem_port0_M_th_1",
+                "01": "mem_port1_M_th_1"
             },
             "02": {
-                "00": "mem_port0_M_th1",
-                "01": "mem_port1_M_th1"
+                "00": "mem_port0_M_th_1",
+                "01": "mem_port1_M_th_1"
             },
             "03": {
-                "00": "mem_port0_M_th1",
-                "01": "mem_port1_M_th1"
+                "00": "mem_port0_M_th_1",
+                "01": "mem_port1_M_th_1"
             },
             "04": {
-                "00": "mem_port0_M_th1",
-                "01": "mem_port1_M_th1"
+                "00": "mem_port0_M_th_1",
+                "01": "mem_port1_M_th_1"
             },
             "05": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "06": {
-                "00": "mem_port0_M_th1",
-                "01": "mem_port1_M_th1",
+                "00": "mem_port0_M_th_1",
+                "01": "mem_port1_M_th_1",
                 "flags": ["odp_data_corrupt_root_cause", "mask_but_dont_clear"]
             },
             "07": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "08": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "09": {
-                "00": "mem_port0_M_th1",
-                "01": "mem_port1_M_th1",
+                "00": "mem_port0_M_th_1",
+                "01": "mem_port1_M_th_1",
                 "flags": ["odp_data_corrupt_root_cause", "mask_but_dont_clear"]
             },
             "0a": {
-                "00": "mem_port0_M_th1",
-                "01": "mem_port1_M_th1",
+                "00": "mem_port0_M_th_1",
+                "01": "mem_port1_M_th_1",
                 "flags": ["odp_data_corrupt_root_cause", "mask_but_dont_clear"]
             },
             "0b": {
-                "00": "mem_port0_M_th1",
-                "01": "mem_port1_M_th1",
+                "00": "mem_port0_M_th_1",
+                "01": "mem_port1_M_th_1",
                 "flags": ["odp_data_corrupt_root_cause", "mask_but_dont_clear"]
             },
             "0c": {
-                "00": "mem_port0_M_th1",
-                "01": "mem_port1_M_th1",
+                "00": "mem_port0_M_th_1",
+                "01": "mem_port1_M_th_1",
                 "flags": ["odp_data_corrupt_root_cause", "mask_but_dont_clear"]
             },
             "0d": {
-                "00": "mem_port0_M_th1",
-                "01": "mem_port1_M_th1",
+                "00": "mem_port0_M_th_1",
+                "01": "mem_port1_M_th_1",
                 "flags": ["odp_data_corrupt_root_cause", "mask_but_dont_clear"]
             },
             "0e": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "0f": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "10": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "11": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "12": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "13": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "14": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "15": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             }
         },
         "18ff": {
             "00": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "01": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "02": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "03": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "04": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "05": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "06": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "07": {
-                "00": "ocmb_M_th1"
+                "00": "ocmb_M_th_1"
             },
             "08": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "09": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0a": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0b": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0c": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             }
         },
         "1ff7": {
             "00": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "01": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "02": {
                 "00": "mem_port0_M_th_32perDay"
             },
             "03": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "04": {
                 "00": "srq_rcd_parity_error_0"
             },
             "05": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "06": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "07": {
-                "00": "mem_port0_M_th1",
+                "00": "mem_port0_M_th_1",
                 "flags": ["sue_source"]
             },
             "08": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "09": {
-                "00": "mem_port0_M_th1"
+                "00": "mem_port0_M_th_1"
             },
             "0a": {
-                "00": "mem_port0_M_th1",
+                "00": "mem_port0_M_th_1",
                 "flags": ["sue_source"]
             },
             "0b": {
-                "00": "mem_port0_M_th1",
+                "00": "mem_port0_M_th_1",
                 "flags": ["sue_source"]
             },
             "0c": {
-                "00": "mem_port0_M_th1",
+                "00": "mem_port0_M_th_1",
                 "flags": ["sue_source"]
             },
             "0d": {
-                "00": "dimm0_H_mem_port0_L_th1",
+                "00": "dimm0_H_mem_port0_L_th_1",
                 "flags": ["sue_source"]
             },
             "0e": {
                 "00": "ocmb_M_info_only"
             },
             "0f": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "10": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "11": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "12": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "13": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "14": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "15": {
-                "00": "ocmb_M_th1"
+                "00": "ocmb_M_th_1"
             },
             "16": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "17": {
@@ -793,24 +793,24 @@
                 "00": "mem_port0_M_th_32perDay"
             },
             "1a": {
-                "00": "mem_port0_M_th1",
+                "00": "mem_port0_M_th_1",
                 "flags": ["sue_source"]
             },
             "1b": {
-                "00": "mem_port1_M_th1",
+                "00": "mem_port1_M_th_1",
                 "flags": ["sue_source"]
             },
             "1c": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "1d": {
                 "00": "srq_recov_parity_error"
             },
             "1e": {
-                "00": "mem_port0_M_th1"
+                "00": "mem_port0_M_th_1"
             },
             "1f": {
-                "00": "mem_port0_M_th1",
+                "00": "mem_port0_M_th_1",
                 "flags": ["sue_source"]
             },
             "20": {
@@ -820,28 +820,28 @@
                 "00": "srq_rcd_parity_error_1"
             },
             "22": {
-                "00": "mem_port1_M_th1"
+                "00": "mem_port1_M_th_1"
             },
             "23": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "24": {
-                "00": "mem_port1_M_th1"
+                "00": "mem_port1_M_th_1"
             },
             "25": {
-                "00": "mem_port1_M_th1",
+                "00": "mem_port1_M_th_1",
                 "flags": ["sue_source"]
             },
             "26": {
-                "00": "mem_port1_M_th1",
+                "00": "mem_port1_M_th_1",
                 "flags": ["sue_source"]
             },
             "27": {
-                "00": "mem_port1_M_th1",
+                "00": "mem_port1_M_th_1",
                 "flags": ["sue_source"]
             },
             "28": {
-                "00": "dimm1_H_mem_port1_L_th1",
+                "00": "dimm1_H_mem_port1_L_th_1",
                 "flags": ["sue_source"]
             },
             "29": {
@@ -851,136 +851,137 @@
                 "00": "mem_port1_M_th_32perDay"
             },
             "2b": {
-                "00": "mem_port1_M_th1",
+                "00": "mem_port1_M_th_1",
                 "flags": ["sue_source"]
             },
             "2c": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "2d": {
-                "00": "mem_port1_M_th1",
+                "00": "mem_port1_M_th_1",
                 "flags": ["sue_source"]
             },
             "2e": {
-                "00": "level2_M_th1"
+                "00": "ocmb_M_th_1",
+                "flags": ["informational_only", "sue_source"]
             },
             "2f": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "30": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             }
         },
         "38df": {
             "00": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "01": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "02": {
-                "00": "omi_bus_th1",
+                "00": "omi_bus_th_1",
                 "flags": ["sue_source"]
             },
             "03": {
-                "00": "omi_bus_th1",
+                "00": "omi_bus_th_1",
                 "flags": ["sue_source"]
             },
             "04": {
-                "00": "omi_bus_th1",
+                "00": "omi_bus_th_1",
                 "flags": ["sue_source"]
             },
             "05": {
-                "00": "omi_bus_th1",
+                "00": "omi_bus_th_1",
                 "flags": ["sue_source"]
             },
             "06": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "07": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "08": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "09": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "0a": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "0b": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "0c": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "0d": {
                 "00": "ocmb_M_info_only"
             },
             "0e": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "0f": {
-                "00": "ocmb_M_th1"
+                "00": "ocmb_M_th_1"
             },
             "10": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "11": {
-                "00": "omi_bus_th1",
+                "00": "omi_bus_th_1",
                 "flags": ["sue_source"]
             },
             "12": {
-                "00": "omi_bus_th1",
+                "00": "omi_bus_th_1",
                 "flags": ["sue_source"]
             },
             "13": {
-                "00": "omi_bus_th1",
+                "00": "omi_bus_th_1",
                 "flags": ["sue_source"]
             },
             "14": {
-                "00": "omi_bus_th1",
+                "00": "omi_bus_th_1",
                 "flags": ["sue_source"]
             },
             "15": {
-                "00": "omi_bus_th1",
+                "00": "omi_bus_th_1",
                 "flags": ["sue_source"]
             },
             "16": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "17": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "18": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "19": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "1a": {
                 "00": "ocmb_M_th_32perDay"
             },
             "1b": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             }
         },
         "3b5b": {
             "00": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "01": {
                 "00": "ocmb_M_info_only"
@@ -1004,284 +1005,284 @@
                 "00": "ocmb_M_info_only"
             },
             "08": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "09": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0a": {
                 "00": "ocmb_M_info_only"
             },
             "0b": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0c": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0d": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0e": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0f": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "10": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "11": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "12": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "13": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "14": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "15": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "16": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "17": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "18": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "19": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "1a": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "1b": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "1c": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "1d": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "1e": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "1f": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "20": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "21": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "22": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "23": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "24": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "25": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "26": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "27": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "28": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "29": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "2a": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "2b": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "2c": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "2d": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "2e": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "2f": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "30": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "31": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "32": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "33": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "34": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "35": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "36": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "37": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "38": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "39": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "3a": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "3b": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "3c": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "3d": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "3e": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "3f": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             }
         },
         "58a8": {
             "34": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "35": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "36": {
-                "00": "omi_bus_th1",
+                "00": "omi_bus_th_1",
                 "flags": ["sue_source"]
             },
             "37": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "38": {
-                "00": "omi_bus_th1",
+                "00": "omi_bus_th_1",
                 "flags": ["sue_source"]
             },
             "39": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "3a": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "3b": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "3c": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "3d": {
-                "00": "omi_bus_th1",
+                "00": "omi_bus_th_1",
                 "flags": ["sue_source"]
             },
             "3e": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "3f": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             }
         },
         "8d4d": {
             "00": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "01": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "02": {
-                "00": "ocmb_M_th1"
+                "00": "ocmb_M_th_1"
             },
             "03": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "04": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "05": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "06": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "07": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "08": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "09": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0a": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0b": {
                 "00": "mcbist_program_complete"
             },
             "0c": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0d": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0e": {
-                "00": "ocmb_M_th1"
+                "00": "ocmb_M_th_1"
             },
             "0f": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "10": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "11": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "12": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             }
         },
         "9ecb": {
@@ -1291,85 +1292,85 @@
         },
         "bc05": {
             "00": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "01": {
-                "00": "ocmb_M_info_only_th1",
+                "00": "ocmb_M_info_only_th_1",
                 "flags": ["crc_root_cause", "mask_but_dont_clear"]
             },
             "02": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "03": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "04": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "05": {
-                "00": "ocmb_M_info_only_th1",
+                "00": "ocmb_M_info_only_th_1",
                 "flags": ["crc_root_cause", "mask_but_dont_clear"]
             },
             "06": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "07": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "08": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "09": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0a": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0b": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0c": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0d": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["crc_root_cause", "mask_but_dont_clear"]
             },
             "0e": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["crc_root_cause", "mask_but_dont_clear"]
             },
             "0f": {
-                "00": "ocmb_M_level2_L_th1",
+                "00": "ocmb_M_level2_L_th_1",
                 "flags": ["crc_root_cause", "mask_but_dont_clear"]
             },
             "10": {
-                "00": "level2_M_ocmb_L_th1",
+                "00": "level2_M_ocmb_L_th_1",
                 "flags": ["crc_root_cause", "mask_but_dont_clear"]
             },
             "11": {
-                "00": "ocmb_M_level2_L_th1",
+                "00": "ocmb_M_level2_L_th_1",
                 "flags": ["crc_root_cause", "mask_but_dont_clear"]
             },
             "12": {
-                "00": "ocmb_M_level2_L_th1",
+                "00": "ocmb_M_level2_L_th_1",
                 "flags": ["crc_root_cause", "mask_but_dont_clear"]
             },
             "13": {
                 "00": "ocmb_M_info_only"
             },
             "14": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["crc_root_cause", "mask_but_dont_clear"]
             },
             "15": {
                 "00": "ocmb_M_th_32perDay"
             },
             "16": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "17": {
-                "00": "level2_M_ocmb_L_th1",
+                "00": "level2_M_ocmb_L_th_1",
                 "flags": ["crc_root_cause", "mask_but_dont_clear"]
             },
             "18": {
@@ -1377,26 +1378,26 @@
                 "flags": ["mnfg_informational_only"]
             },
             "19": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "1a": {
-                "00": "level2_M_ocmb_L_th1",
+                "00": "level2_M_ocmb_L_th_1",
                 "flags": ["crc_root_cause", "mask_but_dont_clear"]
             },
             "1b": {
-                "00": "level2_M_ocmb_L_th1",
+                "00": "level2_M_ocmb_L_th_1",
                 "flags": ["crc_root_cause", "mask_but_dont_clear"]
             },
             "1c": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "1d": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             }
         },
         "df2a": {
             "00": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "01": {
                 "00": "ocmb_M_info_only"
@@ -1420,10 +1421,10 @@
                 "00": "ocmb_M_info_only"
             },
             "08": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "09": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0a": {
                 "00": "ocmb_M_info_only"
@@ -1441,163 +1442,163 @@
                 "00": "ocmb_M_info_only"
             },
             "0f": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "10": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "11": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "12": {
                 "00": "pcb_slave_parity"
             },
             "13": {
-                "00": "ocmb_M_th1"
+                "00": "ocmb_M_th_1"
             },
             "14": {
-                "00": "ocmb_M_th1"
+                "00": "ocmb_M_th_1"
             },
             "15": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "16": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "17": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "18": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "19": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "1a": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "1b": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "1c": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "1d": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "1e": {
-                "00": "level2_M_ocmb_L_th1"
+                "00": "level2_M_ocmb_L_th_1"
             },
             "1f": {
-                "00": "ocmb_M_th1"
+                "00": "ocmb_M_th_1"
             },
             "20": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "21": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "22": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "23": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "24": {
-                "00": "ocmb_M_th1"
+                "00": "ocmb_M_th_1"
             },
             "25": {
-                "00": "ocmb_M_th1"
+                "00": "ocmb_M_th_1"
             },
             "26": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "27": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "28": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "29": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "2a": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "2b": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "2c": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "2d": {
-                "00": "ocmb_M_th1"
+                "00": "ocmb_M_th_1"
             },
             "2e": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "2f": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "30": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "31": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "32": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "33": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "34": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "35": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "36": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "37": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "38": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "39": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "3a": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "3b": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "3c": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "3d": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "3e": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "3f": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             }
         },
         "f8df": {
             "00": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "01": {
                 "00": "downstream_attn",
                 "flags": ["sue_source"]
             },
             "02": {
-                "00": "ocmb_M_th1",
+                "00": "ocmb_M_th_1",
                 "flags": ["sue_source"]
             },
             "03": {
@@ -1608,7 +1609,7 @@
                 "flags": ["crc_related_err"]
             },
             "05": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "06": {
                 "00": "omi_degraded_mode",
@@ -1623,7 +1624,7 @@
                 "flags": ["crc_related_err"]
             },
             "09": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0a": {
                 "00": "omi_bus_th_32perDay"
@@ -1633,110 +1634,110 @@
                 "flags": ["crc_related_err"]
             },
             "0c": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0d": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0e": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "0f": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "10": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "11": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "12": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "13": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "14": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "15": {
-                "00": "ocmb_M_info_only_th1",
+                "00": "ocmb_M_info_only_th_1",
                 "flags": ["crc_root_cause", "mask_but_dont_clear"]
             },
             "16": {
                 "00": "omi_bus_th_32perDay"
             },
             "17": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "18": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "19": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "1a": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "1b": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "1c": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "1d": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "1e": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "1f": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "20": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "21": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "22": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "23": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "24": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "25": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "26": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "27": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "28": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "29": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "2a": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "2b": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             },
             "2c": {
-                "00": "level2_M_th1"
+                "00": "level2_M_th_1"
             }
         },
         "fabf": {
             "00": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "01": {
                 "00": "verify_chip_mark_0",
@@ -1779,35 +1780,35 @@
                 "01": "mainline_nce_tce_handling"
             },
             "0b": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "0c": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "0d": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "0e": {
-                "00": "dimm0_H_mem_port0_L_th1",
-                "01": "dimm1_H_mem_port1_L_th1",
+                "00": "dimm0_H_mem_port0_L_th_1",
+                "01": "dimm1_H_mem_port1_L_th_1",
                 "flags": ["odp_data_corrupt_side_effect", "sue_source"]
             },
             "0f": {
                 "00": "mainline_ue_handling_0",
                 "01": "mainline_ue_handling_1",
-                "flags": ["odp_data_corrupt_side_effect"]
+                "flags": ["odp_data_corrupt_side_effect", "sue_source"]
             },
             "10": {
-                "00": "dimm0_H_mem_port0_L_th1",
-                "01": "dimm1_H_mem_port1_L_th1",
+                "00": "dimm0_H_mem_port0_L_th_1",
+                "01": "dimm1_H_mem_port1_L_th_1",
                 "flags": ["sue_source"]
             },
             "11": {
-                "00": "dimm0_H_mem_port0_L_th1",
-                "01": "dimm1_H_mem_port1_L_th1",
+                "00": "dimm0_H_mem_port0_L_th_1",
+                "01": "dimm1_H_mem_port1_L_th_1",
                 "flags": ["odp_data_corrupt_side_effect", "sue_source"]
             },
             "12": {
@@ -1824,73 +1825,73 @@
                 "01": "memory_impe_handling_1"
             },
             "15": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "16": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "17": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "18": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "19": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "1a": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "1b": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "1c": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "1d": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "1e": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "1f": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "20": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "21": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "22": {
-                "00": "dimm0_H_mem_port0_L_th1",
-                "01": "dimm1_H_mem_port1_L_th1",
+                "00": "dimm0_H_mem_port0_L_th_1",
+                "01": "dimm1_H_mem_port1_L_th_1",
                 "flags": ["odp_data_corrupt_side_effect", "sue_source"]
             },
             "23": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "24": {
-                "00": "dimm0_H_mem_port0_L_th1",
-                "01": "dimm1_H_mem_port1_L_th1"
+                "00": "dimm0_H_mem_port0_L_th_1",
+                "01": "dimm1_H_mem_port1_L_th_1"
             },
             "25": {
-                "00": "dimm0_H_mem_port0_L_th1",
-                "01": "dimm1_H_mem_port1_L_th1",
+                "00": "dimm0_H_mem_port0_L_th_1",
+                "01": "dimm1_H_mem_port1_L_th_1",
                 "flags": ["odp_data_corrupt_side_effect", "sue_source"]
             },
             "26": {
@@ -1915,17 +1916,17 @@
                 "01": "mem_port1_M_info_only"
             },
             "2b": {
-                "00": "mem_port0_M_th1",
-                "01": "mem_port1_M_th1"
+                "00": "mem_port0_M_th_1",
+                "01": "mem_port1_M_th_1"
             },
             "2c": {
-                "00": "mem_port0_M_th1",
-                "01": "mem_port1_M_th1",
+                "00": "mem_port0_M_th_1",
+                "01": "mem_port1_M_th_1",
                 "flags": ["sue_source"]
             },
             "2d": {
-                "00": "mem_port0_M_th1",
-                "01": "mem_port1_M_th1",
+                "00": "mem_port0_M_th_1",
+                "01": "mem_port1_M_th_1",
                 "flags": ["sue_source"]
             },
             "2e": {
@@ -1937,67 +1938,67 @@
                 "01": "mem_port1_M_th_32perDay"
             },
             "30": {
-                "00": "mem_port0_M_th1",
-                "01": "mem_port1_M_th1",
+                "00": "mem_port0_M_th_1",
+                "01": "mem_port1_M_th_1",
                 "flags": ["sue_source"]
             },
             "31": {
-                "00": "mem_port0_M_th1",
-                "01": "mem_port1_M_th1",
+                "00": "mem_port0_M_th_1",
+                "01": "mem_port1_M_th_1",
                 "flags": ["sue_source"]
             },
             "32": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "33": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "34": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "35": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "36": {
-                "00": "mem_port0_M_th1",
-                "01": "mem_port1_M_th1",
+                "00": "mem_port0_M_th_1",
+                "01": "mem_port1_M_th_1",
                 "flags": ["sue_source"]
             },
             "37": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "38": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "39": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "3a": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "3b": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "3c": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "3d": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             },
             "3e": {
-                "00": "level2_M_th1",
-                "01": "level2_M_th1"
+                "00": "level2_M_th_1",
+                "01": "level2_M_th_1"
             }
         }
     },
diff --git a/test/test-root-cause-filter.cpp b/test/test-root-cause-filter.cpp
index 34d80fe..02d7ca6 100644
--- a/test/test-root-cause-filter.cpp
+++ b/test/test-root-cause-filter.cpp
@@ -20,14 +20,26 @@
 
 using namespace analyzer;
 
+// Processor side FIRs
 static const auto eqCoreFir = static_cast<libhei::NodeId_t>(
     libhei::hash<libhei::NodeId_t>("EQ_CORE_FIR"));
 
+static const auto mc_dstl_fir = static_cast<libhei::NodeId_t>(
+    libhei::hash<libhei::NodeId_t>("MC_DSTL_FIR"));
+
+// Explorer OCMB FIRs
 static const auto rdfFir =
     static_cast<libhei::NodeId_t>(libhei::hash<libhei::NodeId_t>("RDFFIR"));
 
-static const auto mc_dstl_fir = static_cast<libhei::NodeId_t>(
-    libhei::hash<libhei::NodeId_t>("MC_DSTL_FIR"));
+// Odyssey OCMB FIRs
+static const auto srq_fir =
+    static_cast<libhei::NodeId_t>(libhei::hash<libhei::NodeId_t>("SRQ_FIR"));
+
+static const auto rdf_fir =
+    static_cast<libhei::NodeId_t>(libhei::hash<libhei::NodeId_t>("RDF_FIR"));
+
+static const auto odp_fir =
+    static_cast<libhei::NodeId_t>(libhei::hash<libhei::NodeId_t>("ODP_FIR"));
 
 TEST(RootCauseFilter, Filter1)
 {
@@ -112,4 +124,39 @@
                                 rootCause, rasData);
     EXPECT_TRUE(attnFound);
     EXPECT_EQ(checkstopSig.toUint32(), rootCause.toUint32());
+
+    // Test 5: Test a firmware initiated channel fail due to an IUE threshold on
+    // a Odyssey OCMB
+    libhei::Chip odyChip0{ocmb0, ODYSSEY_10};
+
+    libhei::Signature fwInitChnlFail{odyChip0, srq_fir, 0, 46,
+                                     libhei::ATTN_TYPE_CHIP_CS};
+    libhei::Signature mainlineIue{odyChip0, rdf_fir, 0, 18,
+                                  libhei::ATTN_TYPE_RECOVERABLE};
+
+    isoData.flush();
+    isoData.addSignature(fwInitChnlFail);
+    isoData.addSignature(mainlineIue);
+
+    attnFound = filterRootCause(AnalysisType::SYSTEM_CHECKSTOP, isoData,
+                                rootCause, rasData);
+    EXPECT_TRUE(attnFound);
+    EXPECT_EQ(mainlineIue.toUint32(), rootCause.toUint32());
+
+    // Test 6: Test a UE that is the side effect of an ODP data corruption error
+    // on an Odyssey OCMB
+    libhei::Signature mainlineUe{odyChip0, rdf_fir, 0, 15,
+                                 libhei::ATTN_TYPE_RECOVERABLE};
+    libhei::Signature odpRootCause{odyChip0, odp_fir, 0, 6,
+                                   libhei::ATTN_TYPE_RECOVERABLE};
+
+    isoData.flush();
+    isoData.addSignature(mainlineUe);
+    isoData.addSignature(odpRootCause);
+
+    attnFound = filterRootCause(AnalysisType::SYSTEM_CHECKSTOP, isoData,
+                                rootCause, rasData);
+
+    EXPECT_TRUE(attnFound);
+    EXPECT_EQ(odpRootCause.toUint32(), rootCause.toUint32());
 }