diff --git a/xml/p10/node_gfir_cs.xml b/xml/p10/node_gfir_cs.xml
index 9b1cd40..bacd3b5 100644
--- a/xml/p10/node_gfir_cs.xml
+++ b/xml/p10/node_gfir_cs.xml
@@ -1,38 +1,38 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <attn_node model_ec="P10_10,P10_20" name="GFIR_CS" reg_type="SCOM">
-    <register name="GFIR_REG_CS">
+    <register name="GFIR_CS">
         <instance addr="0x570F001C" reg_inst="0"/>
     </register>
     <rule attn_type="CS" node_inst="0">
-        <expr type="reg" value1="GFIR_REG_CS"/>
+        <expr type="reg" value1="GFIR_CS"/>
     </rule>
-    <bit child_node="CFIR_TP_CS_RE" node_inst="0" pos="1">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_N0_CS_RE" node_inst="0" pos="2">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_N1_CS" node_inst="0" pos="3">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PCI_CS_RE" node_inst="0" pos="8">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PCI_CS_RE" node_inst="1" pos="9">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="0" pos="12">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="1" pos="13">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="2" pos="14">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="3" pos="15">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PAUE_CS_RE" node_inst="0" pos="16">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PAUE_CS_RE" node_inst="1" pos="17">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PAUW_CS_RE" node_inst="0" pos="18">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PAUW_CS_RE" node_inst="1" pos="19">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="0" pos="24">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="1" pos="25">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="2" pos="26">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="3" pos="27">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="4" pos="28">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="5" pos="29">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="6" pos="30">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="7" pos="31">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_CS" node_inst="0" pos="32">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_CS" node_inst="1" pos="33">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_CS" node_inst="2" pos="34">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_CS" node_inst="3" pos="35">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_CS" node_inst="4" pos="36">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_CS" node_inst="5" pos="37">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_CS" node_inst="6" pos="38">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_CS" node_inst="7" pos="39">XSTOP Register - after masking - OLD XFIR</bit>
+    <bit child_node="CFIR_TP_CS_RE" node_inst="0" pos="1">Attention from TP chiplet</bit>
+    <bit child_node="CFIR_N0_CS_RE" node_inst="0" pos="2">Attention from N0 chiplet</bit>
+    <bit child_node="CFIR_N1_CS" node_inst="0" pos="3">Attention from N1 chiplet</bit>
+    <bit child_node="CFIR_PCI_CS_RE" node_inst="0" pos="8">Attention from PCI 0 chiplet</bit>
+    <bit child_node="CFIR_PCI_CS_RE" node_inst="1" pos="9">Attention from PCI 1 chiplet</bit>
+    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="0" pos="12">Attention from MC 0 chiplet</bit>
+    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="1" pos="13">Attention from MC 1 chiplet</bit>
+    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="2" pos="14">Attention from MC 2 chiplet</bit>
+    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="3" pos="15">Attention from MC 3 chiplet</bit>
+    <bit child_node="CFIR_PAUE_CS_RE" node_inst="0" pos="16">Attention from PAU 0 chiplet</bit>
+    <bit child_node="CFIR_PAUE_CS_RE" node_inst="1" pos="17">Attention from PAU 1 chiplet</bit>
+    <bit child_node="CFIR_PAUW_CS_RE" node_inst="0" pos="18">Attention from PAU 2 chiplet</bit>
+    <bit child_node="CFIR_PAUW_CS_RE" node_inst="1" pos="19">Attention from PAU 3 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="0" pos="24">Attention from IOHS 0 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="1" pos="25">Attention from IOHS 1 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="2" pos="26">Attention from IOHS 2 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="3" pos="27">Attention from IOHS 3 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="4" pos="28">Attention from IOHS 4 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="5" pos="29">Attention from IOHS 5 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="6" pos="30">Attention from IOHS 6 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="7" pos="31">Attention from IOHS 7 chiplet</bit>
+    <bit child_node="CFIR_EQ_CS" node_inst="0" pos="32">Attention from EQ 0 chiplet</bit>
+    <bit child_node="CFIR_EQ_CS" node_inst="1" pos="33">Attention from EQ 1 chiplet</bit>
+    <bit child_node="CFIR_EQ_CS" node_inst="2" pos="34">Attention from EQ 2 chiplet</bit>
+    <bit child_node="CFIR_EQ_CS" node_inst="3" pos="35">Attention from EQ 3 chiplet</bit>
+    <bit child_node="CFIR_EQ_CS" node_inst="4" pos="36">Attention from EQ 4 chiplet</bit>
+    <bit child_node="CFIR_EQ_CS" node_inst="5" pos="37">Attention from EQ 5 chiplet</bit>
+    <bit child_node="CFIR_EQ_CS" node_inst="6" pos="38">Attention from EQ 6 chiplet</bit>
+    <bit child_node="CFIR_EQ_CS" node_inst="7" pos="39">Attention from EQ 7 chiplet</bit>
 </attn_node>
diff --git a/xml/p10/node_gfir_ha.xml b/xml/p10/node_gfir_ha.xml
index adbcdd1..d3b96b2 100644
--- a/xml/p10/node_gfir_ha.xml
+++ b/xml/p10/node_gfir_ha.xml
@@ -1,38 +1,38 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <attn_node model_ec="P10_10,P10_20" name="GFIR_HA" reg_type="SCOM">
-    <register name="GFIR_REG_HA">
+    <register name="GFIR_HA">
         <instance addr="0x570F002B" reg_inst="0"/>
     </register>
     <rule attn_type="HA" node_inst="0">
-        <expr type="reg" value1="GFIR_REG_HA"/>
+        <expr type="reg" value1="GFIR_HA"/>
     </rule>
-    <bit child_node="CFIR_TP_SPA_UCS_HA" node_inst="0" pos="1">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_N0_HA" node_inst="0" pos="2">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_N1_HA" node_inst="0" pos="3">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PCI_SPA_HA" node_inst="0" pos="8">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PCI_SPA_HA" node_inst="1" pos="9">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_MC_UCS_HA" node_inst="0" pos="12">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_MC_UCS_HA" node_inst="1" pos="13">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_MC_UCS_HA" node_inst="2" pos="14">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_MC_UCS_HA" node_inst="3" pos="15">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PAUE_HA" node_inst="0" pos="16">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PAUE_HA" node_inst="1" pos="17">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PAUW_HA" node_inst="0" pos="18">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PAUW_HA" node_inst="1" pos="19">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="0" pos="24">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="1" pos="25">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="2" pos="26">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="3" pos="27">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="4" pos="28">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="5" pos="29">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="6" pos="30">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="7" pos="31">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_HA" node_inst="0" pos="32">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_HA" node_inst="1" pos="33">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_HA" node_inst="2" pos="34">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_HA" node_inst="3" pos="35">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_HA" node_inst="4" pos="36">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_HA" node_inst="5" pos="37">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_HA" node_inst="6" pos="38">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_HA" node_inst="7" pos="39">XSTOP Register - after masking - OLD XFIR</bit>
+    <bit child_node="CFIR_TP_SPA_UCS_HA" node_inst="0" pos="1">Attention from TP chiplet</bit>
+    <bit child_node="CFIR_N0_HA" node_inst="0" pos="2">Attention from N0 chiplet</bit>
+    <bit child_node="CFIR_N1_HA" node_inst="0" pos="3">Attention from N1 chiplet</bit>
+    <bit child_node="CFIR_PCI_SPA_HA" node_inst="0" pos="8">Attention from PCI 0 chiplet</bit>
+    <bit child_node="CFIR_PCI_SPA_HA" node_inst="1" pos="9">Attention from PCI 1 chiplet</bit>
+    <bit child_node="CFIR_MC_UCS_HA" node_inst="0" pos="12">Attention from MC 0 chiplet</bit>
+    <bit child_node="CFIR_MC_UCS_HA" node_inst="1" pos="13">Attention from MC 1 chiplet</bit>
+    <bit child_node="CFIR_MC_UCS_HA" node_inst="2" pos="14">Attention from MC 2 chiplet</bit>
+    <bit child_node="CFIR_MC_UCS_HA" node_inst="3" pos="15">Attention from MC 3 chiplet</bit>
+    <bit child_node="CFIR_PAUE_HA" node_inst="0" pos="16">Attention from PAU 0 chiplet</bit>
+    <bit child_node="CFIR_PAUE_HA" node_inst="1" pos="17">Attention from PAU 1 chiplet</bit>
+    <bit child_node="CFIR_PAUW_HA" node_inst="0" pos="18">Attention from PAU 2 chiplet</bit>
+    <bit child_node="CFIR_PAUW_HA" node_inst="1" pos="19">Attention from PAU 3 chiplet</bit>
+    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="0" pos="24">Attention from IOHS 0 chiplet</bit>
+    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="1" pos="25">Attention from IOHS 1 chiplet</bit>
+    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="2" pos="26">Attention from IOHS 2 chiplet</bit>
+    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="3" pos="27">Attention from IOHS 3 chiplet</bit>
+    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="4" pos="28">Attention from IOHS 4 chiplet</bit>
+    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="5" pos="29">Attention from IOHS 5 chiplet</bit>
+    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="6" pos="30">Attention from IOHS 6 chiplet</bit>
+    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="7" pos="31">Attention from IOHS 7 chiplet</bit>
+    <bit child_node="CFIR_EQ_HA" node_inst="0" pos="32">Attention from EQ 0 chiplet</bit>
+    <bit child_node="CFIR_EQ_HA" node_inst="1" pos="33">Attention from EQ 1 chiplet</bit>
+    <bit child_node="CFIR_EQ_HA" node_inst="2" pos="34">Attention from EQ 2 chiplet</bit>
+    <bit child_node="CFIR_EQ_HA" node_inst="3" pos="35">Attention from EQ 3 chiplet</bit>
+    <bit child_node="CFIR_EQ_HA" node_inst="4" pos="36">Attention from EQ 4 chiplet</bit>
+    <bit child_node="CFIR_EQ_HA" node_inst="5" pos="37">Attention from EQ 5 chiplet</bit>
+    <bit child_node="CFIR_EQ_HA" node_inst="6" pos="38">Attention from EQ 6 chiplet</bit>
+    <bit child_node="CFIR_EQ_HA" node_inst="7" pos="39">Attention from EQ 7 chiplet</bit>
 </attn_node>
diff --git a/xml/p10/node_gfir_re.xml b/xml/p10/node_gfir_re.xml
index 9ba583b..a02e9e8 100644
--- a/xml/p10/node_gfir_re.xml
+++ b/xml/p10/node_gfir_re.xml
@@ -1,38 +1,38 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <attn_node model_ec="P10_10,P10_20" name="GFIR_RE" reg_type="SCOM">
-    <register name="GFIR_REG_RE">
+    <register name="GFIR_RE">
         <instance addr="0x570F001B" reg_inst="0"/>
     </register>
     <rule attn_type="RE" node_inst="0">
-        <expr type="reg" value1="GFIR_REG_RE"/>
+        <expr type="reg" value1="GFIR_RE"/>
     </rule>
-    <bit child_node="CFIR_TP_CS_RE" node_inst="0" pos="1">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_N0_CS_RE" node_inst="0" pos="2">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_N1_RE" node_inst="0" pos="3">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PCI_CS_RE" node_inst="0" pos="8">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PCI_CS_RE" node_inst="1" pos="9">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="0" pos="12">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="1" pos="13">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="2" pos="14">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="3" pos="15">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PAUE_CS_RE" node_inst="0" pos="16">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PAUE_CS_RE" node_inst="1" pos="17">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PAUW_CS_RE" node_inst="0" pos="18">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PAUW_CS_RE" node_inst="1" pos="19">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="0" pos="24">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="1" pos="25">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="2" pos="26">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="3" pos="27">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="4" pos="28">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="5" pos="29">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="6" pos="30">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="7" pos="31">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_RE" node_inst="0" pos="32">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_RE" node_inst="1" pos="33">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_RE" node_inst="2" pos="34">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_RE" node_inst="3" pos="35">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_RE" node_inst="4" pos="36">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_RE" node_inst="5" pos="37">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_RE" node_inst="6" pos="38">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_RE" node_inst="7" pos="39">XSTOP Register - after masking - OLD XFIR</bit>
+    <bit child_node="CFIR_TP_CS_RE" node_inst="0" pos="1">Attention from TP chiplet</bit>
+    <bit child_node="CFIR_N0_CS_RE" node_inst="0" pos="2">Attention from N0 chiplet</bit>
+    <bit child_node="CFIR_N1_RE" node_inst="0" pos="3">Attention from N1 chiplet</bit>
+    <bit child_node="CFIR_PCI_CS_RE" node_inst="0" pos="8">Attention from PCI 0 chiplet</bit>
+    <bit child_node="CFIR_PCI_CS_RE" node_inst="1" pos="9">Attention from PCI 1 chiplet</bit>
+    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="0" pos="12">Attention from MC 0 chiplet</bit>
+    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="1" pos="13">Attention from MC 1 chiplet</bit>
+    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="2" pos="14">Attention from MC 2 chiplet</bit>
+    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="3" pos="15">Attention from MC 3 chiplet</bit>
+    <bit child_node="CFIR_PAUE_CS_RE" node_inst="0" pos="16">Attention from PAU 0 chiplet</bit>
+    <bit child_node="CFIR_PAUE_CS_RE" node_inst="1" pos="17">Attention from PAU 1 chiplet</bit>
+    <bit child_node="CFIR_PAUW_CS_RE" node_inst="0" pos="18">Attention from PAU 2 chiplet</bit>
+    <bit child_node="CFIR_PAUW_CS_RE" node_inst="1" pos="19">Attention from PAU 3 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="0" pos="24">Attention from IOHS 0 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="1" pos="25">Attention from IOHS 1 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="2" pos="26">Attention from IOHS 2 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="3" pos="27">Attention from IOHS 3 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="4" pos="28">Attention from IOHS 4 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="5" pos="29">Attention from IOHS 5 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="6" pos="30">Attention from IOHS 6 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="7" pos="31">Attention from IOHS 7 chiplet</bit>
+    <bit child_node="CFIR_EQ_RE" node_inst="0" pos="32">Attention from EQ 0 chiplet</bit>
+    <bit child_node="CFIR_EQ_RE" node_inst="1" pos="33">Attention from EQ 1 chiplet</bit>
+    <bit child_node="CFIR_EQ_RE" node_inst="2" pos="34">Attention from EQ 2 chiplet</bit>
+    <bit child_node="CFIR_EQ_RE" node_inst="3" pos="35">Attention from EQ 3 chiplet</bit>
+    <bit child_node="CFIR_EQ_RE" node_inst="4" pos="36">Attention from EQ 4 chiplet</bit>
+    <bit child_node="CFIR_EQ_RE" node_inst="5" pos="37">Attention from EQ 5 chiplet</bit>
+    <bit child_node="CFIR_EQ_RE" node_inst="6" pos="38">Attention from EQ 6 chiplet</bit>
+    <bit child_node="CFIR_EQ_RE" node_inst="7" pos="39">Attention from EQ 7 chiplet</bit>
 </attn_node>
diff --git a/xml/p10/node_gfir_spa.xml b/xml/p10/node_gfir_spa.xml
index cc7112a..cdfd1a1 100644
--- a/xml/p10/node_gfir_spa.xml
+++ b/xml/p10/node_gfir_spa.xml
@@ -1,38 +1,38 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <attn_node model_ec="P10_10,P10_20" name="GFIR_SPA" reg_type="SCOM">
-    <register name="GFIR_REG_SPA">
+    <register name="GFIR_SPA">
         <instance addr="0x570F001A" reg_inst="0"/>
     </register>
     <rule attn_type="SPA" node_inst="0">
-        <expr type="reg" value1="GFIR_REG_SPA"/>
+        <expr type="reg" value1="GFIR_SPA"/>
     </rule>
-    <bit child_node="CFIR_TP_SPA_UCS_HA" node_inst="0" pos="1">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_N0_SPA" node_inst="0" pos="2">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_N1_SPA" node_inst="0" pos="3">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PCI_SPA_HA" node_inst="0" pos="8">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PCI_SPA_HA" node_inst="1" pos="9">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="0" pos="12">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="1" pos="13">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="2" pos="14">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="3" pos="15">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PAUE_SPA" node_inst="0" pos="16">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PAUE_SPA" node_inst="1" pos="17">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PAUW_SPA" node_inst="0" pos="18">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PAUW_SPA" node_inst="1" pos="19">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="0" pos="24">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="1" pos="25">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="2" pos="26">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="3" pos="27">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="4" pos="28">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="5" pos="29">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="6" pos="30">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="7" pos="31">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_SPA" node_inst="0" pos="32">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_SPA" node_inst="1" pos="33">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_SPA" node_inst="2" pos="34">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_SPA" node_inst="3" pos="35">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_SPA" node_inst="4" pos="36">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_SPA" node_inst="5" pos="37">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_SPA" node_inst="6" pos="38">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_SPA" node_inst="7" pos="39">XSTOP Register - after masking - OLD XFIR</bit>
+    <bit child_node="CFIR_TP_SPA_UCS_HA" node_inst="0" pos="1">Attention from TP chiplet</bit>
+    <bit child_node="CFIR_N0_SPA" node_inst="0" pos="2">Attention from N0 chiplet</bit>
+    <bit child_node="CFIR_N1_SPA" node_inst="0" pos="3">Attention from N1 chiplet</bit>
+    <bit child_node="CFIR_PCI_SPA_HA" node_inst="0" pos="8">Attention from PCI 0 chiplet</bit>
+    <bit child_node="CFIR_PCI_SPA_HA" node_inst="1" pos="9">Attention from PCI 1 chiplet</bit>
+    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="0" pos="12">Attention from MC 0 chiplet</bit>
+    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="1" pos="13">Attention from MC 1 chiplet</bit>
+    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="2" pos="14">Attention from MC 2 chiplet</bit>
+    <bit child_node="CFIR_MC_CS_RE_SPA" node_inst="3" pos="15">Attention from MC 3 chiplet</bit>
+    <bit child_node="CFIR_PAUE_SPA" node_inst="0" pos="16">Attention from PAU 0 chiplet</bit>
+    <bit child_node="CFIR_PAUE_SPA" node_inst="1" pos="17">Attention from PAU 1 chiplet</bit>
+    <bit child_node="CFIR_PAUW_SPA" node_inst="0" pos="18">Attention from PAU 2 chiplet</bit>
+    <bit child_node="CFIR_PAUW_SPA" node_inst="1" pos="19">Attention from PAU 3 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="0" pos="24">Attention from IOHS 0 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="1" pos="25">Attention from IOHS 1 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="2" pos="26">Attention from IOHS 2 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="3" pos="27">Attention from IOHS 3 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="4" pos="28">Attention from IOHS 4 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="5" pos="29">Attention from IOHS 5 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="6" pos="30">Attention from IOHS 6 chiplet</bit>
+    <bit child_node="CFIR_IOHS_CS_RE_SPA" node_inst="7" pos="31">Attention from IOHS 7 chiplet</bit>
+    <bit child_node="CFIR_EQ_SPA" node_inst="0" pos="32">Attention from EQ 0 chiplet</bit>
+    <bit child_node="CFIR_EQ_SPA" node_inst="1" pos="33">Attention from EQ 1 chiplet</bit>
+    <bit child_node="CFIR_EQ_SPA" node_inst="2" pos="34">Attention from EQ 2 chiplet</bit>
+    <bit child_node="CFIR_EQ_SPA" node_inst="3" pos="35">Attention from EQ 3 chiplet</bit>
+    <bit child_node="CFIR_EQ_SPA" node_inst="4" pos="36">Attention from EQ 4 chiplet</bit>
+    <bit child_node="CFIR_EQ_SPA" node_inst="5" pos="37">Attention from EQ 5 chiplet</bit>
+    <bit child_node="CFIR_EQ_SPA" node_inst="6" pos="38">Attention from EQ 6 chiplet</bit>
+    <bit child_node="CFIR_EQ_SPA" node_inst="7" pos="39">Attention from EQ 7 chiplet</bit>
 </attn_node>
diff --git a/xml/p10/node_gfir_ucs.xml b/xml/p10/node_gfir_ucs.xml
index 259456b..3e19406 100644
--- a/xml/p10/node_gfir_ucs.xml
+++ b/xml/p10/node_gfir_ucs.xml
@@ -1,38 +1,38 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <attn_node model_ec="P10_10,P10_20" name="GFIR_UCS" reg_type="SCOM">
-    <register name="GFIR_REG_UCS">
+    <register name="GFIR_UCS">
         <instance addr="0x570F002A" reg_inst="0"/>
     </register>
     <rule attn_type="UCS" node_inst="0">
-        <expr type="reg" value1="GFIR_REG_UCS"/>
+        <expr type="reg" value1="GFIR_UCS"/>
     </rule>
-    <bit child_node="CFIR_TP_SPA_UCS_HA" node_inst="0" pos="1">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_N0_UCS" node_inst="0" pos="2">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_N1_UCS" node_inst="0" pos="3">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PCI_UCS" node_inst="0" pos="8">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PCI_UCS" node_inst="1" pos="9">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_MC_UCS_HA" node_inst="0" pos="12">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_MC_UCS_HA" node_inst="1" pos="13">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_MC_UCS_HA" node_inst="2" pos="14">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_MC_UCS_HA" node_inst="3" pos="15">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PAUE_UCS" node_inst="0" pos="16">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PAUE_UCS" node_inst="1" pos="17">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PAUW_UCS" node_inst="0" pos="18">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_PAUW_UCS" node_inst="1" pos="19">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="0" pos="24">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="1" pos="25">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="2" pos="26">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="3" pos="27">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="4" pos="28">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="5" pos="29">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="6" pos="30">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="7" pos="31">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_UCS" node_inst="0" pos="32">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_UCS" node_inst="1" pos="33">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_UCS" node_inst="2" pos="34">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_UCS" node_inst="3" pos="35">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_UCS" node_inst="4" pos="36">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_UCS" node_inst="5" pos="37">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_UCS" node_inst="6" pos="38">XSTOP Register - after masking - OLD XFIR</bit>
-    <bit child_node="CFIR_EQ_UCS" node_inst="7" pos="39">XSTOP Register - after masking - OLD XFIR</bit>
+    <bit child_node="CFIR_TP_SPA_UCS_HA" node_inst="0" pos="1">Attention from TP chiplet</bit>
+    <bit child_node="CFIR_N0_UCS" node_inst="0" pos="2">Attention from N0 chiplet</bit>
+    <bit child_node="CFIR_N1_UCS" node_inst="0" pos="3">Attention from N1 chiplet</bit>
+    <bit child_node="CFIR_PCI_UCS" node_inst="0" pos="8">Attention from PCI 0 chiplet</bit>
+    <bit child_node="CFIR_PCI_UCS" node_inst="1" pos="9">Attention from PCI 1 chiplet</bit>
+    <bit child_node="CFIR_MC_UCS_HA" node_inst="0" pos="12">Attention from MC 0 chiplet</bit>
+    <bit child_node="CFIR_MC_UCS_HA" node_inst="1" pos="13">Attention from MC 1 chiplet</bit>
+    <bit child_node="CFIR_MC_UCS_HA" node_inst="2" pos="14">Attention from MC 2 chiplet</bit>
+    <bit child_node="CFIR_MC_UCS_HA" node_inst="3" pos="15">Attention from MC 3 chiplet</bit>
+    <bit child_node="CFIR_PAUE_UCS" node_inst="0" pos="16">Attention from PAU 0 chiplet</bit>
+    <bit child_node="CFIR_PAUE_UCS" node_inst="1" pos="17">Attention from PAU 1 chiplet</bit>
+    <bit child_node="CFIR_PAUW_UCS" node_inst="0" pos="18">Attention from PAU 2 chiplet</bit>
+    <bit child_node="CFIR_PAUW_UCS" node_inst="1" pos="19">Attention from PAU 3 chiplet</bit>
+    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="0" pos="24">Attention from IOHS 0 chiplet</bit>
+    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="1" pos="25">Attention from IOHS 1 chiplet</bit>
+    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="2" pos="26">Attention from IOHS 2 chiplet</bit>
+    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="3" pos="27">Attention from IOHS 3 chiplet</bit>
+    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="4" pos="28">Attention from IOHS 4 chiplet</bit>
+    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="5" pos="29">Attention from IOHS 5 chiplet</bit>
+    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="6" pos="30">Attention from IOHS 6 chiplet</bit>
+    <bit child_node="CFIR_IOHS_UCS_HA" node_inst="7" pos="31">Attention from IOHS 7 chiplet</bit>
+    <bit child_node="CFIR_EQ_UCS" node_inst="0" pos="32">Attention from EQ 0 chiplet</bit>
+    <bit child_node="CFIR_EQ_UCS" node_inst="1" pos="33">Attention from EQ 1 chiplet</bit>
+    <bit child_node="CFIR_EQ_UCS" node_inst="2" pos="34">Attention from EQ 2 chiplet</bit>
+    <bit child_node="CFIR_EQ_UCS" node_inst="3" pos="35">Attention from EQ 3 chiplet</bit>
+    <bit child_node="CFIR_EQ_UCS" node_inst="4" pos="36">Attention from EQ 4 chiplet</bit>
+    <bit child_node="CFIR_EQ_UCS" node_inst="5" pos="37">Attention from EQ 5 chiplet</bit>
+    <bit child_node="CFIR_EQ_UCS" node_inst="6" pos="38">Attention from EQ 6 chiplet</bit>
+    <bit child_node="CFIR_EQ_UCS" node_inst="7" pos="39">Attention from EQ 7 chiplet</bit>
 </attn_node>